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| 2 | pj | 1 | /* |
| 2 | * Project: S.Ha.R.K. |
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| 3 | * |
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| 4 | * Coordinators: |
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| 5 | * Giorgio Buttazzo <giorgio@sssup.it> |
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| 6 | * Paolo Gai <pj@gandalf.sssup.it> |
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| 7 | * |
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| 8 | * Authors : |
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| 9 | * Paolo Gai <pj@gandalf.sssup.it> |
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| 10 | * Massimiliano Giorgi <massy@gandalf.sssup.it> |
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| 11 | * Luca Abeni <luca@gandalf.sssup.it> |
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| 12 | * (see the web pages for full authors list) |
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| 13 | * |
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| 14 | * ReTiS Lab (Scuola Superiore S.Anna - Pisa - Italy) |
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| 15 | * |
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| 16 | * http://www.sssup.it |
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| 17 | * http://retis.sssup.it |
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| 18 | * http://shark.sssup.it |
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| 19 | */ |
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| 20 | |||
| 21 | /** |
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| 22 | ------------ |
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| 23 | CVS : $Id: _rtc.h,v 1.1.1.1 2002-03-29 14:12:49 pj Exp $ |
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| 24 | |||
| 25 | File: $File$ |
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| 26 | Revision: $Revision: 1.1.1.1 $ |
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| 27 | Last update: $Date: 2002-03-29 14:12:49 $ |
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| 28 | ------------ |
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| 29 | |||
| 30 | Author: Massimiliano Giorgi |
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| 31 | |||
| 32 | A source from Linux 2.2.9 modified to work with S.Ha.R.K. |
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| 33 | |||
| 34 | mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM |
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| 35 | Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 |
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| 36 | derived from Data Sheet, Copyright Motorola 1984 (!). |
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| 37 | It was written to be part of the Linux operating system. |
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| 38 | |||
| 39 | **/ |
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| 40 | |||
| 41 | /* |
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| 42 | * Copyright (C) 2000 Paolo Gai |
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| 43 | * |
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| 44 | * This program is free software; you can redistribute it and/or modify |
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| 45 | * it under the terms of the GNU General Public License as published by |
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| 46 | * the Free Software Foundation; either version 2 of the License, or |
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| 47 | * (at your option) any later version. |
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| 48 | * |
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| 49 | * This program is distributed in the hope that it will be useful, |
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| 50 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 51 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 52 | * GNU General Public License for more details. |
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| 53 | * |
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| 54 | * You should have received a copy of the GNU General Public License |
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| 55 | * along with this program; if not, write to the Free Software |
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| 56 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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| 57 | * |
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| 58 | */ |
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| 59 | |||
| 60 | #ifndef _MC146818RTC_H |
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| 61 | #define _MC146818RTC_H |
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| 62 | |||
| 63 | #include <drivers/rtc.h> |
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| 64 | |||
| 65 | #ifndef RTC_PORT |
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| 66 | #define RTC_PORT(x) (0x70 + (x)) |
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| 67 | #define RTC_ALWAYS_BCD 1 |
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| 68 | #endif |
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| 69 | |||
| 70 | /********************************************************************** |
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| 71 | * register summary |
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| 72 | **********************************************************************/ |
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| 73 | #define RTC_SECONDS 0 |
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| 74 | #define RTC_SECONDS_ALARM 1 |
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| 75 | #define RTC_MINUTES 2 |
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| 76 | #define RTC_MINUTES_ALARM 3 |
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| 77 | #define RTC_HOURS 4 |
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| 78 | #define RTC_HOURS_ALARM 5 |
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| 79 | /* RTC_*_alarm is always true if 2 MSBs are set */ |
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| 80 | # define RTC_ALARM_DONT_CARE 0xC0 |
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| 81 | |||
| 82 | #define RTC_DAY_OF_WEEK 6 |
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| 83 | #define RTC_DAY_OF_MONTH 7 |
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| 84 | #define RTC_MONTH 8 |
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| 85 | #define RTC_YEAR 9 |
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| 86 | |||
| 87 | /* control registers - Moto names |
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| 88 | */ |
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| 89 | #define RTC_REG_A 10 |
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| 90 | #define RTC_REG_B 11 |
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| 91 | #define RTC_REG_C 12 |
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| 92 | #define RTC_REG_D 13 |
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| 93 | |||
| 94 | /********************************************************************** |
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| 95 | * register details |
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| 96 | **********************************************************************/ |
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| 97 | #define RTC_FREQ_SELECT RTC_REG_A |
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| 98 | |||
| 99 | /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, |
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| 100 | * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, |
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| 101 | * totalling to a max high interval of 2.228 ms. |
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| 102 | */ |
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| 103 | # define RTC_UIP 0x80 |
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| 104 | # define RTC_DIV_CTL 0x70 |
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| 105 | /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ |
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| 106 | # define RTC_REF_CLCK_4MHZ 0x00 |
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| 107 | # define RTC_REF_CLCK_1MHZ 0x10 |
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| 108 | # define RTC_REF_CLCK_32KHZ 0x20 |
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| 109 | /* 2 values for divider stage reset, others for "testing purposes only" */ |
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| 110 | # define RTC_DIV_RESET1 0x60 |
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| 111 | # define RTC_DIV_RESET2 0x70 |
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| 112 | /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ |
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| 113 | # define RTC_RATE_SELECT 0x0F |
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| 114 | |||
| 115 | /**********************************************************************/ |
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| 116 | #define RTC_CONTROL RTC_REG_B |
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| 117 | # define RTC_SET 0x80 /* disable updates for clock setting */ |
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| 118 | # define RTC_PIE 0x40 /* periodic interrupt enable */ |
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| 119 | # define RTC_AIE 0x20 /* alarm interrupt enable */ |
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| 120 | # define RTC_UIE 0x10 /* update-finished interrupt enable */ |
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| 121 | # define RTC_SQWE 0x08 /* enable square-wave output */ |
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| 122 | # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ |
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| 123 | # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ |
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| 124 | # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ |
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| 125 | |||
| 126 | /**********************************************************************/ |
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| 127 | #define RTC_INTR_FLAGS RTC_REG_C |
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| 128 | /* caution - cleared by read */ |
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| 129 | # define RTC_IRQF 0x80 /* any of the following 3 is active */ |
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| 130 | # define RTC_PF 0x40 |
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| 131 | # define RTC_AF 0x20 |
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| 132 | # define RTC_UF 0x10 |
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| 133 | |||
| 134 | /**********************************************************************/ |
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| 135 | #define RTC_VALID RTC_REG_D |
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| 136 | # define RTC_VRT 0x80 /* valid RAM and time */ |
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| 137 | /**********************************************************************/ |
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| 138 | |||
| 139 | /* example: !(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) |
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| 140 | * determines if the following two #defines are needed |
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| 141 | */ |
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| 142 | #ifndef BCD_TO_BIN |
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| 143 | #define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) |
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| 144 | #endif |
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| 145 | |||
| 146 | #ifndef BIN_TO_BCD |
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| 147 | #define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) |
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| 148 | #endif |
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| 149 | |||
| 150 | /* |
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| 151 | * ioctl calls that are permitted to the /dev/rtc interface, if |
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| 152 | * CONFIG_RTC was enabled. |
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| 153 | */ |
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| 154 | |||
| 155 | #define RTC_AIE_ON _IO('p', 0x01) /* Alarm int. enable on */ |
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| 156 | #define RTC_AIE_OFF _IO('p', 0x02) /* ... off */ |
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| 157 | #define RTC_UIE_ON _IO('p', 0x03) /* Update int. enable on */ |
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| 158 | #define RTC_UIE_OFF _IO('p', 0x04) /* ... off */ |
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| 159 | #define RTC_PIE_ON _IO('p', 0x05) /* Periodic int. enable on */ |
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| 160 | #define RTC_PIE_OFF _IO('p', 0x06) /* ... off */ |
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| 161 | |||
| 162 | #define RTC_ALM_SET _IOW('p', 0x07, struct rtc_time) /* Set alarm time */ |
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| 163 | #define RTC_ALM_READ _IOR('p', 0x08, struct rtc_time) /* Read alarm time */ |
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| 164 | #define RTC_RD_TIME _IOR('p', 0x09, struct rtc_time) /* Read RTC time */ |
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| 165 | #define RTC_SET_TIME _IOW('p', 0x0a, struct rtc_time) /* Set RTC time */ |
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| 166 | #define RTC_IRQP_READ _IOR('p', 0x0b, unsigned long) /* Read IRQ rate */ |
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| 167 | #define RTC_IRQP_SET _IOW('p', 0x0c, unsigned long) /* Set IRQ rate */ |
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| 168 | #define RTC_EPOCH_READ _IOR('p', 0x0d, unsigned long) /* Read epoch */ |
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| 169 | #define RTC_EPOCH_SET _IOW('p', 0x0e, unsigned long) /* Set epoch */ |
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| 170 | |||
| 171 | |||
| 172 | #endif /* _MC146818RTC_H */ |