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2 | pj | 1 | /***************************************************************************** |
2 | * Filename: pci6025e.h * |
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3 | * Author: Ziglioli Marco * |
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4 | * Date: 15/03/2001 * |
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5 | * Last update: * |
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6 | * Description: Header file which contains declaration of structure variables * |
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7 | * and routines used to interface with PCI6025E * |
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8 | *----------------------------------------------------------------------------* |
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9 | * Notes: Based on National C Routines * |
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10 | *****************************************************************************/ |
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11 | |||
12 | /* This file is part of the S.Ha.R.K. Project - http://shark.sssup.it |
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13 | * |
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14 | * Copyright (C) 2001 Marco Ziglioli |
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15 | * |
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16 | * This program is free software; you can redistribute it and/or modify |
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17 | * it under the terms of the GNU General Public License as published by |
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18 | * the Free Software Foundation; either version 2 of the License, or |
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19 | * (at your option) any later version. |
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20 | * |
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21 | * This program is distributed in the hope that it will be useful, |
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22 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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23 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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24 | * GNU General Public License for more details. |
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25 | * |
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26 | * You should have received a copy of the GNU General Public License |
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27 | * along with this program; if not, write to the Free Software |
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28 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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29 | * |
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30 | */ |
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31 | |||
32 | #ifndef _MY_PCI6025E_ |
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33 | #define _MY_PCI6025E_ |
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34 | |||
35 | #include <kernel/kern.h> |
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36 | #include <drivers/pci.h> |
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37 | #include <ll/i386/hw-instr.h> |
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38 | |||
39 | #include "regconst.h" |
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40 | |||
41 | //#define __REG_DEBUG__ //enable this in debug mode to see |
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42 | //configuration registers value |
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43 | |||
44 | #define NI_CODE 0x1093 //NI Vendor_ID board code |
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45 | |||
46 | #define Board_Address STC_Base_Address |
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47 | |||
48 | #define BAR0 0xE8000L //New address of MITE |
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49 | #define BAR1 0xEA000L //New address of STC |
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50 | |||
51 | #define INT_NO NIDevice_info[0].InterruptLevel |
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52 | |||
53 | struct pci6025e_deviceinfo { |
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54 | WORD DEVID; |
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55 | BYTE DevFunction; |
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56 | BYTE BusNumber; |
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57 | DWORD BAR0Value; |
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58 | DWORD IntLineRegValue; |
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59 | DWORD RevisionID; |
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60 | BYTE InterruptLevel; |
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61 | }; |
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62 | |||
63 | extern struct pci6025e_deviceinfo NIDevice_info[10]; |
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64 | extern DWORD *IntLinestructptr; |
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65 | extern DWORD *BAR0structptr; |
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66 | extern DWORD *RevID; |
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67 | |||
68 | extern DWORD STC_Base_Address, MITE_Base_Address; |
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69 | |||
70 | #define set(b,p) b|=(0x01 << p) //set p-th bit of byte b to 1 |
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71 | #define clr(b,p) b&=~(0x01 << p) //set p-th bit of byte b to 0 |
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72 | |||
73 | //scan PCI bus to find board and remap it on memory above 1MB |
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74 | BYTE find_NI_Device(void); |
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75 | BYTE reMap(void); |
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76 | |||
77 | //IO Windowed access board registers |
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78 | void DAQ_STC_Windowed_Mode_Write(WORD reg_addr, WORD value); |
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79 | WORD DAQ_STC_Windowed_Mode_Read(WORD reg_addr); |
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80 | |||
81 | //On board clock |
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82 | BYTE setIntClock(BYTE, BYTE, BYTE); |
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83 | |||
84 | //PFI programming |
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85 | void PFIprogramming(WORD); |
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86 | |||
87 | //Interrupt management |
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88 | void INT_personalize(BYTE); |
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89 | void INT_setup(BYTE, BYTE); |
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90 | |||
91 | //needful macros |
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92 | #define Immediate_Readb(addr) *((BYTE *)(Board_Address + (addr))) |
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93 | #define Immediate_Readw(addr) *((WORD *)(Board_Address + (addr))) |
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94 | #define Immediate_Writeb(addr, val) *((BYTE *)(Board_Address + (addr)))=(val) |
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95 | #define Immediate_Writew(addr, val) *((WORD *)(Board_Address + (addr)))=(val) |
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96 | |||
97 | void bitfield(BYTE dim, DWORD value); |
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98 | void TEST_bitfield(BYTE dim, DWORD value, char *str); |
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99 | |||
100 | //Software copy of STC general registers |
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101 | extern WORD joint_reset, interrupt_a_enable, interrupt_a_ack, |
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102 | interrupt_b_enable, interrupt_b_ack, clock_and_fout; |
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103 | |||
104 | #endif |
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105 | /*End of File: Pci6025e.h*/ |