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2 | pj | 1 | /***************************************************************************** |
2 | * Filename: Regconst.h * |
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3 | * Author: Ziglioli Marco * |
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4 | * Date: 23/03/2001 * |
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5 | * Description: Symbolic constant names of registers used in STC and on board * |
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6 | *****************************************************************************/ |
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7 | |||
8 | /* This file is part of the S.Ha.R.K. Project - http://shark.sssup.it |
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9 | * |
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10 | * Copyright (C) 2001 Marco Ziglioli |
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11 | * |
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12 | * This program is free software; you can redistribute it and/or modify |
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13 | * it under the terms of the GNU General Public License as published by |
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14 | * the Free Software Foundation; either version 2 of the License, or |
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15 | * (at your option) any later version. |
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16 | * |
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17 | * This program is distributed in the hope that it will be useful, |
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18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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20 | * GNU General Public License for more details. |
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21 | * |
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22 | * You should have received a copy of the GNU General Public License |
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23 | * along with this program; if not, write to the Free Software |
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24 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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25 | * |
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26 | */ |
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27 | |||
28 | |||
29 | #ifndef _MY_REGCONST_H_ |
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30 | #define _MY_REGCONST_H_ |
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31 | |||
32 | //DAQ STC registers (see file REG-DES.txt for bitfield description) |
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33 | #define WIN_ADDR_REG (0x00) * 2 //Write-only |
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34 | #define WIN_DATA_WR_REG (0x01) * 2 //Write-only |
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35 | #define WIN_DATA_RD_REG (0x01) * 2 //Read-only |
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36 | |||
37 | #define INTERRUPT_A_ACK 0x02 //Write-only |
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38 | #define AI_STATUS_1 0x02 //Read-only |
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39 | #define INTERRUPT_B_ACK 0x03 //Write-only |
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40 | #define AO_STATUS_1 0x03 //Read-only |
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41 | #define AI_COMMAND_2 0x04 //Write-only |
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42 | #define G_STATUS 0x04 //Read-only |
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43 | #define AI_STATUS_2 0x05 //Read-only |
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44 | #define AO_COMMAND_2 0x05 //Write-only |
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45 | #define AO_STATUS_2 0x06 //Read-only |
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46 | #define G0_COMMAND 0x06 //Write-only |
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47 | #define DIO_PARALLEL_INPUT 0x07 //Read-only |
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48 | #define G1_COMMAND 0x07 //Write-only |
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49 | #define AI_COMMAND_1 0x08 //Write-only |
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50 | #define G0_HW_SAVE_HI 0x08 //Read-only |
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51 | #define AO_COMMAND_1 0x09 //Write-only |
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52 | #define G0_HW_SAVE_LO 0x09 //Read-only |
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53 | #define DIO_OUTPUT 0x0A //Write-only |
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54 | #define G1_HW_SAVE_HI 0x0A //Read-only |
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55 | #define DIO_CONTROL 0x0B //Write-only |
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56 | #define G1_HW_SAVE_LO 0x0B //Read-only |
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57 | #define AI_MODE_1 0x0C //Write-only |
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58 | #define G0_SAVE_HI 0x0C //Read-only |
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59 | #define AI_MODE_2 0x0D //Write-only |
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60 | #define G0_SAVE_LO 0x0D //Read-only |
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61 | #define AI_SI_LOAD_A_HI 0x0E //Write-only |
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62 | #define G1_SAVE_HI 0x0E //Read-only |
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63 | #define AI_SI_LOAD_A_LO 0x0F //Write-only |
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64 | #define G1_SAVE_LO 0x0F //Read-only |
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65 | #define AI_SI_LOAD_B_HI 0x10 //Write-only |
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66 | #define AO_UI_SAVE_HI 0x10 //Read-only |
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67 | #define AI_SI_LOAD_B_LO 0x11 //Write-only |
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68 | #define AO_UI_SAVE_LO 0x11 //Read-only |
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69 | #define AI_SC_LOAD_A_HI 0x12 //Write-only |
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70 | #define AO_BC_SAVE_HI 0x12 //Read-only |
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71 | #define AI_SC_LOAD_A_LO 0x13 //Write-only |
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72 | #define AO_BC_SAVE_LO 0x13 //Read-only |
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73 | #define AI_SC_LOAD_B_HI 0x14 //Write-only |
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74 | #define AO_UC_SAVE_HI 0x14 //Read-only |
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75 | #define AI_SC_LOAD_B_LO 0x15 //Write-only |
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76 | #define AO_UC_SAVE_LO 0x15 //Read-only |
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77 | |||
78 | #define AI_SI2_LOAD_A 0x17 //Write-only |
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79 | #define AO_UI2_SAVE 0x17 //Read-only |
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80 | #define AI_SI2_LOAD_B 0x19 //Write-only |
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81 | #define AI_SI2_SAVE 0x19 //Read-only |
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82 | #define G0_MODE 0x1A //Write-only |
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83 | #define AI_DIV_SAVE 0x1A //Read-only |
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84 | #define G1_MODE 0x1B //Write-only |
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85 | #define JOINT_STATUS_1 0x1B //Read-only |
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86 | #define DIO_SERIAL_INPUT 0x1C //Read-only |
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87 | #define G0_LOAD_A_HI 0x1C //Write-only |
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88 | #define G0_LOAD_A_LO 0x1D //Write-only |
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89 | #define JOINT_STATUS_2 0x1D //Read-only |
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90 | #define G0_LOAD_B_HI 0x1E //Write-only |
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91 | #define G0_LOAD_B_LO 0x1F //Write-only |
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92 | #define G1_LOAD_A_HI 0x20 //Write-only |
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93 | #define G1_LOAD_A_LO 0x21 //Write-only |
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94 | #define G1_LOAD_B_HI 0x22 //Write-only |
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95 | #define G1_LOAD_B_LO 0x23 //Write-only |
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96 | #define G1_INPUT_SELECT 0x25 //Write-only |
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97 | #define G0_INPUT_SELECT 0x24 //Write-only |
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98 | #define AO_MODE_1 0x26 //Write-only |
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99 | #define AO_MODE_2 0x27 //Write-only |
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100 | #define AO_UI_LOAD_A_HI 0x28 //Write-only |
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101 | #define AO_UI_LOAD_A_LO 0x29 //Write-only |
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102 | #define AO_UI_LOAD_B_HI 0x2A //Write-only |
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103 | #define AO_UI_LOAD_B_LO 0x2B //Write-only |
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104 | #define AO_BC_LOAD_A_HI 0x2C //Write-only |
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105 | #define AO_BC_LOAD_A_LO 0x2D //Write-only |
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106 | #define AO_BC_LOAD_B_HI 0x2E //Write-only |
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107 | #define AO_BC_LOAD_B_LO 0x2F //Write-only |
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108 | #define AO_UC_LOAD_A_HI 0x30 //Write-only |
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109 | #define AO_UC_LOAD_A_LO 0x31 //Write-only |
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110 | #define AO_UC_LOAD_B_HI 0x32 //Write-only |
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111 | #define AO_UC_LOAD_B_LO 0x33 //Write-only |
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112 | #define AO_UI2_LOAD_A 0x35 //Write-only |
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113 | #define AO_UI2_LOAD_B 0x37 //Write-only |
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114 | #define CLOCK_AND_FOUT 0x38 //Write-only |
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115 | #define IO_BIDIRECTION_PIN 0x39 //Write-only |
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116 | #define RTSI_TRIG_DIRECTION 0x3A //Write-only |
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117 | #define INTERRUPT_CONTROL 0x3B //Write-only |
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118 | #define AI_OUTPUT_CONTROL 0x3C //Write-only |
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119 | #define ANALOG_TRIGGER_ETC 0x3D //Write-only |
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120 | #define AI_START_STOP_SELECT 0x3E //Write-only |
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121 | #define AI_TRIGGER_SELECT 0x3F //Write-only |
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122 | #define AI_DIV_LOAD_A 0x40 //Write-only |
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123 | #define AI_SI_SAVE_HI 0x40 //Read-only |
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124 | #define AI_SI_SAVE_LO 0x41 //Read-only |
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125 | #define AI_SC_SAVE_HI 0x42 //Read-only |
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126 | #define AO_START_SELECT 0x42 //Write-only |
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127 | #define AI_SC_SAVE_LO 0x43 //Read-only |
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128 | #define AO_TRIGGER_SELECT 0x43 //Write-only |
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129 | #define G0_AUTOINCREMENT 0x44 //Write-only |
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130 | #define G1_AUTOINCREMENT 0x45 //Write-only |
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131 | #define AO_MODE_3 0x46 //Write-only |
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132 | #define GENERIC_CONTROL 0x47 //Write-only |
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133 | #define JOINT_RESET 0x48 //Write-only |
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134 | #define INTERRUPT_A_ENABLE 0x49 //Write-only |
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135 | #define SECOND_IRQ_A_ENABLE 0x4A //Write-only |
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136 | #define INTERRUPT_B_ENABLE 0x4B //Write-only |
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137 | #define SECOND_IRQ_B_ENABLE 0x4C //Write-only |
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138 | #define AI_PERSONAL 0x4D //Write-only |
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139 | #define AO_PERSONAL 0x4E //Write-only |
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140 | #define RTSI_TRIG_A_OUTPUT 0x4F //Write-only |
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141 | #define RTSI_TRIG_B_OUTPUT 0x50 //Write-only |
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142 | #define RTSI_BOARD 0x51 //Write-only |
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143 | #define WRITE_STROBE_0 0x52 //Write-only |
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144 | #define WRITE_STROBE_1 0x53 //Write-only |
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145 | #define WRITE_STROBE_2 0x54 //Write-only |
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146 | #define WRITE_STROBE_3 0x55 //Write-only |
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147 | #define AO_OUTPUT_CONTROL 0x56 //Write-only |
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148 | #define AI_MODE_3 0x57 //Write-only |
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149 | |||
150 | //Analog Input Registers Group |
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151 | #define ADC_CONFIG_HI 0x12 //Write-only |
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152 | #define ADC_CONFIG_LO 0x10 //Write-only |
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153 | #define ADC_DATA_READ 0x1C //Read-only |
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154 | |||
155 | //Analog Output Registers Group |
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156 | #define DAC_CONFIG 0x16 //Write-only |
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157 | #define DAC_FIFO 0x1E //Write-only |
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158 | #define DAC0_DATA 0x18 //Write-only |
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159 | #define DAC1_DATA 0x1A //Write-only |
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160 | |||
161 | /*PPI OKI82C55A MSM registers: |
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162 | Finally I found this walues writing a cycle which scanned board registers |
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163 | and check for some test lines value. I don't know why but these aren't |
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164 | unique right values. Also 19 1B 1D 1F and 59 5B 5D 5F and 99 9B 9D 9F work |
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165 | so if you have collision problems with other address try to change these |
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166 | values. |
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167 | */ |
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168 | #define PPI_PORT_A 0xD9 //PORT_A of 8255 |
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169 | #define PPI_PORT_B 0xDB //PORT_B of 8255 |
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170 | #define PPI_PORT_C 0xDD //PORT_C of 8255 |
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171 | #define PPI_CFG_REG 0xDF //Configuration Register |
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172 | |||
173 | |||
174 | #endif |
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175 | /*End of file: regconst.h*/ |