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/* Project:     OSLib
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 * Description: The OS Construction Kit
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 * Date:                1.6.2000
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 * Idea by:             Luca Abeni & Gerardo Lamastra
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 *
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 * OSLib is an SO project aimed at developing a common, easy-to-use
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 * low-level infrastructure for developing OS kernels and Embedded
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 * Applications; it partially derives from the HARTIK project but it
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 * currently is independently developed.
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 *
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 * OSLib is distributed under GPL License, and some of its code has
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 * been derived from the Linux kernel source; also some important
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 * ideas come from studying the DJGPP go32 extender.
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 *
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 * We acknowledge the Linux Community, Free Software Foundation,
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 * D.J. Delorie and all the other developers who believe in the
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 * freedom of software and ideas.
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 *
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 * For legalese, check out the included GPL license.
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 */
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/*      PIC management code & data      */
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#include <ll/i386/hw-instr.h>
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FILE(IRQ);
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#define ICW1_M  0x020           /* Master PIC (8259) register settings */
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#define ICW2_M  0x021
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#define ICW3_M  0x021
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#define ICW4_M  0x021
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#define OCW1_M  0x021
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#define OCW2_M  0x020
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#define OCW3_M  0x020
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#define ICW1_S  0x0A0           /* Slave PIC register setting */
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#define ICW2_S  0x0A1
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#define ICW3_S  0x0A1
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#define ICW4_S  0x0A1
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#define OCW1_S  0x0A1
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#define OCW2_S  0x0A0
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#define OCW3_S  0x0A0
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#define PIC1_BASE 0x040         /* Interrupt base for each PIC in HARTIK 3.0 */
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#define PIC2_BASE 0x070
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#define EOI       0x020         /* End Of Interrupt code for PIC! */
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#define bit_on(v,b)     ((v) |= (1 << (b)))
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#define bit_off(v,b)    ((v) &= ~(1 << (b)))
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/* PIC interrupt mask */
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BYTE ll_PIC_master_mask = 0xFE;
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BYTE ll_PIC_slave_mask = 0xFE;
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void PIC_init(void)
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{
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    outp(ICW1_M, 0x11);
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    outp(ICW2_M, PIC1_BASE);
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    outp(ICW3_M, 0x04);
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    outp(ICW4_M, 0x01);
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    outp(OCW1_M, 0xFF);
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    outp(ICW1_S, 0x11);
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    outp(ICW2_S, PIC2_BASE);
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    outp(ICW3_S, 0x02);
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    outp(ICW4_S, 0x01);
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    outp(OCW1_S, 0xFF);
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}
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void PIC_end(void)
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{
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    outp(ICW1_M, 0x11);
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    outp(ICW2_M, 0x08);
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    outp(ICW3_M, 0x04);
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    outp(ICW4_M, 0x01);
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    outp(OCW1_M, 0xFF);
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    outp(ICW1_S, 0x11);
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    outp(ICW2_S, 0x70);
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    outp(ICW3_S, 0x02);
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    outp(ICW4_S, 0x01);
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    outp(OCW1_S, 0xFF);
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}
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void irq_mask(WORD irqno)
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{
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    /* Cannot mask timer interrupt! */
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    if (irqno == 0)
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        return;
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    /* Interrupt is on master PIC */
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    if (irqno < 8) {
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        bit_on(ll_PIC_master_mask, irqno);
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        outp(0x21, ll_PIC_master_mask);
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    } else if (irqno < 16) {
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        /* Interrupt on slave PIC */
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        bit_on(ll_PIC_slave_mask, irqno - 8);
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        outp(0xA1, ll_PIC_slave_mask);
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        /* If the slave PIC is completely off   */
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        /* Then turn off cascading line (Irq #2) */
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        if (ll_PIC_slave_mask == 0xFF && !(ll_PIC_master_mask & 0x04)) {
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            bit_on(ll_PIC_master_mask, 2);
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            outp(0x21, ll_PIC_master_mask);
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        }
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    }
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}
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void irq_unmask(WORD irqno)
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{
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    /* It is a nonsense to unmask the timer interrupt */
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    if (irqno == 0)
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        return;
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    /* Interrupt is on master PIC */
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    if (irqno < 8) {
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        bit_off(ll_PIC_master_mask, irqno);
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        outp(0x21, ll_PIC_master_mask);
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    } else if (irqno < 16) {
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        /* Interrupt on slave PIC */
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        bit_off(ll_PIC_slave_mask, irqno - 8);
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        outp(0xA1, ll_PIC_slave_mask);
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        /* If the cascading irq line was off */
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        /* Then activate it also!            */
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        if (ll_PIC_master_mask & 0x04) {
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            bit_off(ll_PIC_master_mask, 2);
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            outp(0x21, ll_PIC_master_mask);
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        }
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    }
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}