Details | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
||
| 3 | * Date: 1.6.2000 |
||
| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
||
| 5 | * |
||
| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
||
| 7 | * low-level infrastructure for developing OS kernels and Embedded |
||
| 8 | * Applications; it partially derives from the HARTIK project but it |
||
| 9 | * currently is independently developed. |
||
| 10 | * |
||
| 11 | * OSLib is distributed under GPL License, and some of its code has |
||
| 12 | * been derived from the Linux kernel source; also some important |
||
| 13 | * ideas come from studying the DJGPP go32 extender. |
||
| 14 | * |
||
| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
||
| 16 | * D.J. Delorie and all the other developers who believe in the |
||
| 17 | * freedom of software and ideas. |
||
| 18 | * |
||
| 19 | * For legalese, check out the included GPL license. |
||
| 20 | */ |
||
| 21 | |||
| 22 | /* PIC management code & data */ |
||
| 23 | |||
| 24 | #include <ll/i386/hw-instr.h> |
||
| 25 | |||
| 26 | FILE(IRQ); |
||
| 27 | |||
| 28 | #define ICW1_M 0x020 /* Master PIC (8259) register settings */ |
||
| 29 | #define ICW2_M 0x021 |
||
| 30 | #define ICW3_M 0x021 |
||
| 31 | #define ICW4_M 0x021 |
||
| 32 | #define OCW1_M 0x021 |
||
| 33 | #define OCW2_M 0x020 |
||
| 34 | #define OCW3_M 0x020 |
||
| 35 | |||
| 36 | #define ICW1_S 0x0A0 /* Slave PIC register setting */ |
||
| 37 | #define ICW2_S 0x0A1 |
||
| 38 | #define ICW3_S 0x0A1 |
||
| 39 | #define ICW4_S 0x0A1 |
||
| 40 | #define OCW1_S 0x0A1 |
||
| 41 | #define OCW2_S 0x0A0 |
||
| 42 | #define OCW3_S 0x0A0 |
||
| 43 | |||
| 44 | #define PIC1_BASE 0x040 /* Interrupt base for each PIC in HARTIK 3.0 */ |
||
| 45 | #define PIC2_BASE 0x070 |
||
| 46 | #define EOI 0x020 /* End Of Interrupt code for PIC! */ |
||
| 47 | |||
| 48 | #define bit_on(v,b) ((v) |= (1 << (b))) |
||
| 49 | #define bit_off(v,b) ((v) &= ~(1 << (b))) |
||
| 50 | |||
| 51 | /* PIC interrupt mask */ |
||
| 52 | BYTE ll_PIC_master_mask = 0xFE; |
||
| 53 | BYTE ll_PIC_slave_mask = 0xFE; |
||
| 54 | |||
| 55 | |||
| 56 | void PIC_init(void) |
||
| 57 | { |
||
| 58 | outp(ICW1_M, 0x11); |
||
| 59 | outp(ICW2_M, PIC1_BASE); |
||
| 60 | outp(ICW3_M, 0x04); |
||
| 61 | outp(ICW4_M, 0x01); |
||
| 62 | outp(OCW1_M, 0xFF); |
||
| 63 | |||
| 64 | outp(ICW1_S, 0x11); |
||
| 65 | outp(ICW2_S, PIC2_BASE); |
||
| 66 | outp(ICW3_S, 0x02); |
||
| 67 | outp(ICW4_S, 0x01); |
||
| 68 | outp(OCW1_S, 0xFF); |
||
| 69 | } |
||
| 70 | |||
| 71 | void PIC_end(void) |
||
| 72 | { |
||
| 73 | outp(ICW1_M, 0x11); |
||
| 74 | outp(ICW2_M, 0x08); |
||
| 75 | outp(ICW3_M, 0x04); |
||
| 76 | outp(ICW4_M, 0x01); |
||
| 77 | outp(OCW1_M, 0xFF); |
||
| 78 | |||
| 79 | outp(ICW1_S, 0x11); |
||
| 80 | outp(ICW2_S, 0x70); |
||
| 81 | outp(ICW3_S, 0x02); |
||
| 82 | outp(ICW4_S, 0x01); |
||
| 83 | outp(OCW1_S, 0xFF); |
||
| 84 | } |
||
| 85 | |||
| 86 | void irq_mask(WORD irqno) |
||
| 87 | { |
||
| 88 | /* Cannot mask timer interrupt! */ |
||
| 89 | if (irqno == 0) |
||
| 90 | return; |
||
| 91 | /* Interrupt is on master PIC */ |
||
| 92 | if (irqno < 8) { |
||
| 93 | bit_on(ll_PIC_master_mask, irqno); |
||
| 94 | outp(0x21, ll_PIC_master_mask); |
||
| 95 | } else if (irqno < 16) { |
||
| 96 | /* Interrupt on slave PIC */ |
||
| 97 | bit_on(ll_PIC_slave_mask, irqno - 8); |
||
| 98 | outp(0xA1, ll_PIC_slave_mask); |
||
| 99 | /* If the slave PIC is completely off */ |
||
| 100 | /* Then turn off cascading line (Irq #2) */ |
||
| 101 | if (ll_PIC_slave_mask == 0xFF && !(ll_PIC_master_mask & 0x04)) { |
||
| 102 | bit_on(ll_PIC_master_mask, 2); |
||
| 103 | outp(0x21, ll_PIC_master_mask); |
||
| 104 | } |
||
| 105 | } |
||
| 106 | } |
||
| 107 | |||
| 108 | void irq_unmask(WORD irqno) |
||
| 109 | { |
||
| 110 | /* It is a nonsense to unmask the timer interrupt */ |
||
| 111 | if (irqno == 0) |
||
| 112 | return; |
||
| 113 | /* Interrupt is on master PIC */ |
||
| 114 | if (irqno < 8) { |
||
| 115 | bit_off(ll_PIC_master_mask, irqno); |
||
| 116 | outp(0x21, ll_PIC_master_mask); |
||
| 117 | } else if (irqno < 16) { |
||
| 118 | /* Interrupt on slave PIC */ |
||
| 119 | bit_off(ll_PIC_slave_mask, irqno - 8); |
||
| 120 | outp(0xA1, ll_PIC_slave_mask); |
||
| 121 | /* If the cascading irq line was off */ |
||
| 122 | /* Then activate it also! */ |
||
| 123 | if (ll_PIC_master_mask & 0x04) { |
||
| 124 | bit_off(ll_PIC_master_mask, 2); |
||
| 125 | outp(0x21, ll_PIC_master_mask); |
||
| 126 | } |
||
| 127 | } |
||
| 128 | } |