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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
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| 3 | * Date: 1.6.2000 |
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| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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| 5 | * |
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| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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| 7 | * low-level infrastructure for developing OS kernels and Embedded |
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| 8 | * Applications; it partially derives from the HARTIK project but it |
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| 9 | * currently is independently developed. |
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| 10 | * |
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| 11 | * OSLib is distributed under GPL License, and some of its code has |
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| 12 | * been derived from the Linux kernel source; also some important |
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| 13 | * ideas come from studying the DJGPP go32 extender. |
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| 14 | * |
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| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
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| 16 | * D.J. Delorie and all the other developers who believe in the |
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| 17 | * freedom of software and ideas. |
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| 18 | * |
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| 19 | * For legalese, check out the included GPL license. |
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| 20 | */ |
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| 21 | |||
| 22 | /* Xlib initialization code */ |
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| 23 | |||
| 24 | #include <ll/i386/mem.h> |
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| 25 | #include <ll/i386/cons.h> |
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| 26 | #include <ll/i386/mb-info.h> |
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| 27 | #include <ll/i386/error.h> |
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| 28 | #include <ll/i386/pit.h> |
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| 29 | #include <ll/i386/pic.h> |
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| 30 | |||
| 31 | #include <ll/i386/tss-ctx.h> |
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| 32 | #include <ll/i386/hw-arch.h> |
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| 33 | |||
| 34 | FILE(X - Init); |
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| 35 | |||
| 36 | extern DWORD ll_irq_table[16]; |
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| 37 | extern DWORD ll_exc_table[16]; |
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| 38 | |||
| 39 | #ifdef __VIRCSW__ |
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| 40 | int activeInt = 0; |
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| 41 | #endif |
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| 42 | |||
| 43 | /* Architecture definition */ |
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| 44 | LL_ARCH ll_arch; |
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| 45 | |||
| 46 | /* These are declared in llCx32b.C */ |
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| 47 | TSS TSS_table[TSSMax]; |
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| 48 | WORD TSS_control[TSSMax]; |
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| 49 | BYTE ll_FPU_stdctx[FPU_CONTEXT_SIZE]; |
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| 50 | |||
| 51 | /* The following stuff is in llCxA.Asm/S */ |
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| 52 | |||
| 53 | /* Assembly external routines! */ |
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| 54 | /* Setup the TR register of the 80386, to initialize context switch */ |
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| 55 | |||
| 56 | extern void init_TR(WORD v); |
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| 57 | |||
| 58 | /* ll hardware interrupt hooks */ |
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| 59 | extern void h1(void); |
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| 60 | extern void h2(void); |
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| 61 | extern void h3(void); |
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| 62 | extern void h4(void); |
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| 63 | extern void h5(void); |
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| 64 | extern void h6(void); |
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| 65 | extern void h7(void); |
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| 66 | extern void h8(void); |
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| 67 | extern void h9(void); |
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| 68 | extern void h10(void); |
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| 69 | extern void h11(void); |
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| 70 | extern void h12(void); |
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| 71 | extern void h13(void); |
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| 72 | extern void h13_bis(void); |
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| 73 | extern void h14(void); |
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| 74 | extern void h15(void); |
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| 75 | |||
| 76 | /* ll hardware exception hooks */ |
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| 77 | /* In llCtx1.Asm/s */ |
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| 78 | extern void exc0(void); |
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| 79 | extern void exc1(void); |
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| 80 | extern void exc2(void); |
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| 81 | extern void exc3(void); |
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| 82 | extern void exc4(void); |
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| 83 | extern void exc5(void); |
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| 84 | extern void exc6(void); |
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| 85 | extern void exc7(void); |
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| 86 | extern void exc8(void); |
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| 87 | extern void exc9(void); |
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| 88 | extern void exc10(void); |
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| 89 | extern void exc11(void); |
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| 90 | extern void exc12(void); |
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| 91 | extern void exc13(void); |
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| 92 | extern void exc14(void); |
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| 93 | extern void exc15(void); |
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| 94 | extern void exc16(void); |
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| 95 | |||
| 96 | static void dummyfun(int i) |
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| 97 | { |
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| 98 | cputs("Unhandled Exc or Int occured!!!\n"); |
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| 99 | /* |
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| 100 | message("Unhandled Exc or Int %d occured!!!\n", i); |
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| 101 | */ |
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| 102 | halt(); |
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| 103 | } |
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| 104 | |||
| 105 | void l1_exc_bind(int i, void (*f) (int n)) |
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| 106 | { |
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| 107 | ll_exc_table[i] = (DWORD) f; |
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| 108 | } |
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| 109 | |||
| 110 | void l1_irq_bind(int i, void (*f) (int n)) |
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| 111 | { |
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| 112 | ll_irq_table[i] = (DWORD) f; |
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| 113 | } |
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| 114 | |||
| 115 | void *l1_init(void) |
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| 116 | { |
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| 117 | register int i; |
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| 118 | struct ll_cpuInfo cpuInfo; |
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| 119 | LIN_ADDR b; |
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| 120 | extern BYTE X86_fpu; |
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| 121 | |||
| 122 | TSS dummy_tss; /* Very dirty, but we need it, in order to |
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| 123 | get an initial value for the FPU |
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| 124 | context... |
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| 125 | */ |
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| 126 | |||
| 127 | |||
| 128 | /* First of all, init the exc and irq tables... */ |
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| 129 | for (i = 0; i < 16; i++) { |
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| 130 | ll_irq_table[i] = (DWORD) dummyfun; |
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| 131 | ll_exc_table[i] = (DWORD) dummyfun; |
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| 132 | } |
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| 133 | |||
| 134 | X86_get_CPU(&cpuInfo); |
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| 135 | X86_get_FPU(); |
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| 136 | ll_arch.x86.arch = __LL_ARCH__; |
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| 137 | ll_arch.x86.cpu = cpuInfo.X86_cpu; |
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| 138 | ll_arch.x86.fpu = X86_fpu; |
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| 139 | memcpy(&(ll_arch.x86.vendor), &(cpuInfo.X86_vendor_1), 12); |
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| 140 | |||
| 141 | /* TODO! Need to map featuresXXX & Signature onto ll_arch! */ |
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| 142 | /* TODO! Need to check for CPU bugs!! */ |
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| 143 | |||
| 144 | #ifdef __LL_DEBUG__ |
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| 145 | message("LL Architecture: %s\n", __LL_ARCH__); |
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| 146 | message("CPU : %u\nFPU : %u\n", cpuInfo.X86_cpu, X86_fpu); |
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| 147 | message("Signature : 0x%lx\nVendor: %s\n", cpuInfo.X86_signature, |
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| 148 | ll_arch.x86.vendor); |
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| 149 | message("Features #1: 0x%lx\n", cpuInfo.X86_IntelFeature_1); |
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| 150 | message("Features #2: 0x%lx\n", cpuInfo.X86_IntelFeature_2); |
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| 151 | message("Features #3: 0x%lx\n", cpuInfo.X86_StandardFeature); |
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| 152 | #endif /* __LL_DEBUG__ */ |
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| 153 | |||
| 154 | /* Insert the Exceptions handler into IDT */ |
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| 155 | IDT_place(0x00, exc0); |
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| 156 | IDT_place(0x01, exc1); |
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| 157 | IDT_place(0x02, exc2); |
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| 158 | IDT_place(0x03, exc3); |
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| 159 | IDT_place(0x04, exc4); |
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| 160 | IDT_place(0x05, exc5); |
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| 161 | IDT_place(0x06, exc6); |
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| 162 | IDT_place(0x07, exc7); |
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| 163 | IDT_place(0x08, exc8); |
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| 164 | IDT_place(0x09, exc9); |
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| 165 | IDT_place(0x0A, exc10); |
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| 166 | IDT_place(0x0B, exc11); |
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| 167 | IDT_place(0x0C, exc12); |
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| 168 | IDT_place(0x0D, exc13); |
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| 169 | IDT_place(0x0E, exc14); |
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| 170 | IDT_place(0x0F, exc15); |
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| 171 | IDT_place(0x10, exc16); |
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| 172 | /* Insert HW timer handler into IDT */ |
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| 173 | /* Now it is done in event.c |
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| 174 | IDT_place(0x40,ll_timer); |
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| 175 | */ |
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| 176 | IDT_place(0x41, h1); |
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| 177 | IDT_place(0x42, h2); |
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| 178 | IDT_place(0x43, h3); |
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| 179 | IDT_place(0x44, h4); |
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| 180 | IDT_place(0x45, h5); |
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| 181 | IDT_place(0x46, h6); |
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| 182 | IDT_place(0x47, h7); |
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| 183 | IDT_place(0x70, h8); |
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| 184 | IDT_place(0x71, h9); |
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| 185 | IDT_place(0x72, h10); |
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| 186 | IDT_place(0x73, h11); |
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| 187 | IDT_place(0x74, h12); |
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| 188 | |||
| 189 | #if 0 |
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| 190 | /* If FPU is on-chip IRQ #13 is free to use */ |
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| 191 | /* Else IRQ #13 vectors the coprocessor errors */ |
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| 192 | if (check_fpu()) |
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| 193 | ll_arch.x86.capabilities |= LL_X86_INTERNAL_FPU; |
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| 194 | |||
| 195 | #ifdef __LL_DEBUG__ |
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| 196 | message("Check FPU : %s\n", |
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| 197 | ll_arch.x86. |
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| 198 | capabilities & LL_X86_INTERNAL_FPU ? "Internal" : "External"); |
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| 199 | #endif |
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| 200 | |||
| 201 | if (ll_arch.x86.capabilities & LL_X86_INTERNAL_FPU) { |
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| 202 | /* Install the generic handler */ |
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| 203 | IDT_place(0x75, h13); |
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| 204 | } else { |
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| 205 | /* Install the external FPU error handler */ |
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| 206 | IDT_place(0x75, h13_bis); |
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| 207 | irq_unmask(13); |
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| 208 | } |
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| 209 | #else |
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| 210 | IDT_place(0x75, h13); |
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| 211 | #endif |
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| 212 | IDT_place(0x76, h14); |
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| 213 | IDT_place(0x77, h15); |
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| 214 | |||
| 215 | /* Init TSS table & put the corrispondent selectors into GDT */ |
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| 216 | TSS_control[TSSMain] |= TSS_USED; |
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| 217 | for (i = 0; i < TSSMax; i++) { |
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| 218 | /* b = appl2linear(&TSS_table[i]); */ |
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| 219 | b = (LIN_ADDR) (&TSS_table[i]); |
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| 220 | GDT_place(TSSindex2sel(i), (DWORD) b, sizeof(TSS), FREE_TSS386, |
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| 221 | GRAN_16); |
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| 222 | } |
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| 223 | /* Set the TR initial value */ |
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| 224 | init_TR(TSSindex2sel(TSSMain)); |
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| 225 | |||
| 226 | /* Init coprocessor & assign it to main() */ |
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| 227 | /* OK... Now I know the sense of all this... : |
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| 228 | We need a initial value for the FPU context (to be used for creating |
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| 229 | new FPU contexts, as init value)... |
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| 230 | ... And we get it in this strange way!!!! |
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| 231 | */ |
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| 232 | reset_fpu(); |
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| 233 | #if 0 |
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| 234 | ll_FPU_save(); |
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| 235 | memcpy(ll_FPU_stdctx, ll_FPU_savearea, FPU_CONTEXT_SIZE); |
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| 236 | #else |
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| 237 | save_fpu(&dummy_tss); /* OK??? */ |
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| 238 | memcpy(ll_FPU_stdctx, dummy_tss.ctx_FPU, FPU_CONTEXT_SIZE); |
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| 239 | #endif |
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| 240 | init_fpu(); |
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| 241 | |||
| 242 | /* Init PIC controllers & unmask timer */ |
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| 243 | PIC_init(); |
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| 244 | |||
| 245 | return mbi_address(); |
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| 246 | } |
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| 247 | |||
| 248 | |||
| 249 | void l1_end(void) |
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| 250 | { |
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| 251 | outp(0x21, 0xFF); |
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| 252 | outp(0xA1, 0xFF); |
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| 253 | /* Back to DOS settings */ |
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| 254 | PIC_end(); |
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| 255 | /* Reset the timer chip according DOS specification */ |
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| 256 | /* Mode: Binary/Mode 3/16 bit Time_const/Counter 0 */ |
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| 257 | #if 0 |
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| 258 | outp(0x43, 0x36); |
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| 259 | /* Time_const = 65536; write 0 in CTR */ |
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| 260 | outp(0x40, 0); |
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| 261 | outp(0x40, 0); |
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| 262 | #endif |
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| 263 | pit_init(0, TMR_MD3, 0); /* Timer 0, Mode 3, Time constant 0 */ |
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| 264 | if (ll_arch.x86.cpu > 4) { |
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| 265 | pit_init(1, TMR_MD2, 18); |
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| 266 | } else { |
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| 267 | pit_init(2, TMR_MD0, 0); |
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| 268 | outp(0x61, 0); /* Stop channel 2 */ |
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| 269 | } |
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| 270 | } |