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| Rev | Author | Line No. | Line |
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| 2 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
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| 3 | * Date: 1.6.2000 |
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| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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| 5 | * |
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| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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| 7 | * low-level infrastructure for developing OS kernels and Embedded |
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| 8 | * Applications; it partially derives from the HARTIK project but it |
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| 9 | * currently is independently developed. |
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| 10 | * |
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| 11 | * OSLib is distributed under GPL License, and some of its code has |
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| 12 | * been derived from the Linux kernel source; also some important |
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| 13 | * ideas come from studying the DJGPP go32 extender. |
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| 14 | * |
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| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
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| 16 | * D.J. Delorie and all the other developers who believe in the |
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| 17 | * freedom of software and ideas. |
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| 18 | * |
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| 19 | * For legalese, check out the included GPL license. |
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| 20 | */ |
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| 21 | |||
| 22 | /* PIC management code & data */ |
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| 23 | |||
| 24 | #include <ll/i386/hw-instr.h> |
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| 40 | pj | 25 | #include <ll/i386/pic.h> |
| 2 | pj | 26 | |
| 27 | FILE(IRQ); |
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| 28 | |||
| 40 | pj | 29 | #define ICW1_M 0x020 /* Master PIC (8259) register settings */ |
| 2 | pj | 30 | #define ICW2_M 0x021 |
| 31 | #define ICW3_M 0x021 |
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| 32 | #define ICW4_M 0x021 |
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| 33 | #define OCW1_M 0x021 |
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| 34 | #define OCW2_M 0x020 |
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| 35 | #define OCW3_M 0x020 |
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| 36 | |||
| 40 | pj | 37 | #define ICW1_S 0x0A0 /* Slave PIC register setting */ |
| 2 | pj | 38 | #define ICW2_S 0x0A1 |
| 39 | #define ICW3_S 0x0A1 |
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| 40 | #define ICW4_S 0x0A1 |
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| 41 | #define OCW1_S 0x0A1 |
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| 42 | #define OCW2_S 0x0A0 |
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| 43 | #define OCW3_S 0x0A0 |
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| 44 | |||
| 40 | pj | 45 | #define EOI 0x020 /* End Of Interrupt code for PIC! */ |
| 2 | pj | 46 | |
| 47 | #define bit_on(v,b) ((v) |= (1 << (b))) |
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| 48 | #define bit_off(v,b) ((v) &= ~(1 << (b))) |
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| 49 | |||
| 50 | /* PIC interrupt mask */ |
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| 40 | pj | 51 | BYTE ll_PIC_master_mask = 0xFF; |
| 52 | BYTE ll_PIC_slave_mask = 0xFF; |
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| 2 | pj | 53 | |
| 54 | |||
| 55 | void PIC_init(void) |
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| 56 | { |
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| 40 | pj | 57 | outp(ICW1_M,0x11); |
| 58 | outp(ICW2_M,PIC1_BASE); |
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| 59 | outp(ICW3_M,0x04); |
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| 60 | outp(ICW4_M,0x01); |
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| 61 | outp(OCW1_M,0xFF); |
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| 2 | pj | 62 | |
| 40 | pj | 63 | outp(ICW1_S,0x11); |
| 64 | outp(ICW2_S,PIC2_BASE); |
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| 65 | outp(ICW3_S,0x02); |
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| 66 | outp(ICW4_S,0x01); |
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| 67 | outp(OCW1_S,0xFF); |
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| 2 | pj | 68 | } |
| 69 | |||
| 70 | void PIC_end(void) |
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| 71 | { |
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| 40 | pj | 72 | outp(ICW1_M,0x11); |
| 73 | outp(ICW2_M,0x08); |
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| 74 | outp(ICW3_M,0x04); |
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| 75 | outp(ICW4_M,0x01); |
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| 76 | outp(OCW1_M,0xFF); |
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| 2 | pj | 77 | |
| 40 | pj | 78 | outp(ICW1_S,0x11); |
| 79 | outp(ICW2_S,0x70); |
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| 80 | outp(ICW3_S,0x02); |
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| 81 | outp(ICW4_S,0x01); |
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| 82 | outp(OCW1_S,0xFF); |
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| 2 | pj | 83 | } |
| 84 | |||
| 85 | void irq_mask(WORD irqno) |
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| 86 | { |
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| 87 | /* Interrupt is on master PIC */ |
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| 88 | if (irqno < 8) { |
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| 40 | pj | 89 | bit_on(ll_PIC_master_mask,irqno); |
| 90 | outp(0x21,ll_PIC_master_mask); |
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| 2 | pj | 91 | } else if (irqno < 16) { |
| 92 | /* Interrupt on slave PIC */ |
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| 40 | pj | 93 | bit_on(ll_PIC_slave_mask,irqno-8); |
| 94 | outp(0xA1,ll_PIC_slave_mask); |
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| 2 | pj | 95 | /* If the slave PIC is completely off */ |
| 40 | pj | 96 | /* Then turn off cascading line (Irq #2)*/ |
| 2 | pj | 97 | if (ll_PIC_slave_mask == 0xFF && !(ll_PIC_master_mask & 0x04)) { |
| 40 | pj | 98 | bit_on(ll_PIC_master_mask,2); |
| 99 | outp(0x21,ll_PIC_master_mask); |
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| 2 | pj | 100 | } |
| 101 | } |
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| 102 | } |
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| 103 | |||
| 104 | void irq_unmask(WORD irqno) |
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| 105 | { |
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| 106 | /* Interrupt is on master PIC */ |
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| 107 | if (irqno < 8) { |
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| 40 | pj | 108 | bit_off(ll_PIC_master_mask,irqno); |
| 109 | outp(0x21,ll_PIC_master_mask); |
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| 2 | pj | 110 | } else if (irqno < 16) { |
| 111 | /* Interrupt on slave PIC */ |
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| 40 | pj | 112 | bit_off(ll_PIC_slave_mask,irqno-8); |
| 113 | outp(0xA1,ll_PIC_slave_mask); |
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| 2 | pj | 114 | /* If the cascading irq line was off */ |
| 115 | /* Then activate it also! */ |
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| 116 | if (ll_PIC_master_mask & 0x04) { |
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| 40 | pj | 117 | bit_off(ll_PIC_master_mask,2); |
| 118 | outp(0x21,ll_PIC_master_mask); |
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| 2 | pj | 119 | } |
| 120 | } |
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| 121 | } |