WebSVN - shark - Blame - Rev 1618 - /shark/branches/xen/drivers/fb/radeonfb.c

Rev	Author	Line No.	Line
472	giacomo	1	/*
		2	* drivers/video/radeonfb.c
		3	* framebuffer driver for ATI Radeon chipset video boards
		4	*
		5	* Copyright 2000 Ani Joshi <ajoshi@kernel.crashing.org>
		6	*
		7	*
		8	* ChangeLog:
		9	* 2000-08-03 initial version 0.0.1
		10	* 2000-09-10 more bug fixes, public release 0.0.5
		11	* 2001-02-19 mode bug fixes, 0.0.7
		12	* 2001-07-05 fixed scrolling issues, engine initialization,
		13	* and minor mode tweaking, 0.0.9
		14	* 2001-09-07 Radeon VE support, Nick Kurshev
		15	* blanking, pan_display, and cmap fixes, 0.1.0
		16	* 2001-10-10 Radeon 7500 and 8500 support, and experimental
		17	* flat panel support, 0.1.1
		18	* 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
		19	* 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
		20	* 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
		21	* 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
		22	* 2002-06-02 console switching, mode set fixes, accel fixes
		23	* 2002-06-03 MTRR support, Peter Horton, 0.1.5
		24	* 2002-09-21 rv250, r300, m9 initial support,
		25	* added mirror option, 0.1.6
		26	*
		27	* Special thanks to ATI DevRel team for their hardware donations.
		28	*
		29	*/
		30
		31
		32	#define RADEON_VERSION "0.1.6"
		33
		34	#include <linuxcomp.h>
		35
		36	#include <linux/config.h>
		37	#include <linux/module.h>
		38	#include <linux/kernel.h>
		39	#include <linux/errno.h>
		40	#include <linux/string.h>
		41	#include <linux/mm.h>
		42	#include <linux/tty.h>
		43	#include <linux/slab.h>
		44	#include <linux/delay.h>
		45	#include <linux/fb.h>
		46	#include <linux/ioport.h>
		47	#include <linux/init.h>
		48	#include <linux/pci.h>
		49	#include <linux/vmalloc.h>
		50
		51	#include <asm/io.h>
		52	#include <asm/uaccess.h>
		53	#if defined(__powerpc__)
		54	#include <asm/prom.h>
		55	#include <asm/pci-bridge.h>
		56	#include "macmodes.h"
		57
		58	#ifdef CONFIG_NVRAM
		59	#include <linux/nvram.h>
		60	#endif
		61
		62	#ifdef CONFIG_PMAC_BACKLIGHT
		63	#include <asm/backlight.h>
		64	#endif
		65
		66	#ifdef CONFIG_BOOTX_TEXT
		67	#include <asm/btext.h>
		68	#endif
		69
		70	#ifdef CONFIG_ADB_PMU
		71	#include <linux/adb.h>
		72	#include <linux/pmu.h>
		73	#endif
		74
		75	#endif /* __powerpc__ */
		76
		77	#ifdef CONFIG_MTRR
		78	#include <asm/mtrr.h>
		79	#endif
		80
		81	#include <video/radeon.h>
		82	#include <linux/radeonfb.h>
		83
		84	#define DEBUG 1
		85
		86	#if DEBUG
		87	#define RTRACE printk
		88	#else
		89	#define RTRACE if(0) printk
		90	#endif
		91
		92	// XXX
		93	#undef CONFIG_PMAC_PBOOK
		94
		95
		96	enum radeon_chips {
		97	RADEON_QD,
		98	RADEON_QE,
		99	RADEON_QF,
		100	RADEON_QG,
		101	RADEON_QY,
		102	RADEON_QZ,
		103	RADEON_LW,
		104	RADEON_LX,
		105	RADEON_LY,
		106	RADEON_LZ,
		107	RADEON_QL,
		108	RADEON_QN,
		109	RADEON_QO,
		110	RADEON_Ql,
		111	RADEON_BB,
		112	RADEON_QW,
		113	RADEON_QX,
		114	RADEON_Id,
		115	RADEON_Ie,
		116	RADEON_If,
		117	RADEON_Ig,
		118	RADEON_Ld,
		119	RADEON_Le,
		120	RADEON_Lf,
		121	RADEON_Lg,
		122	RADEON_ND,
		123	RADEON_NE,
		124	RADEON_NF,
		125	RADEON_NG,
		126	RADEON_QM
		127	};
		128
		129	enum radeon_arch {
		130	RADEON_R100,
		131	RADEON_RV100,
		132	RADEON_R200,
		133	RADEON_RV200,
		134	RADEON_RV250,
		135	RADEON_R300,
		136	RADEON_M6,
		137	RADEON_M7,
		138	RADEON_M9
		139	};
		140
		141	static struct radeon_chip_info {
		142	const char *name;
		143	unsigned char arch;
		144	} radeon_chip_info[] __devinitdata = {
		145	{ "QD", RADEON_R100 },
		146	{ "QE", RADEON_R100 },
		147	{ "QF", RADEON_R100 },
		148	{ "QG", RADEON_R100 },
		149	{ "VE QY", RADEON_RV100 },
		150	{ "VE QZ", RADEON_RV100 },
		151	{ "M7 LW", RADEON_M7 },
		152	{ "M7 LX", RADEON_M7 },
		153	{ "M6 LY", RADEON_M6 },
		154	{ "M6 LZ", RADEON_M6 },
		155	{ "8500 QL", RADEON_R200 },
		156	{ "8500 QN", RADEON_R200 },
		157	{ "8500 QO", RADEON_R200 },
		158	{ "8500 Ql", RADEON_R200 },
		159	{ "8500 BB", RADEON_R200 },
		160	{ "7500 QW", RADEON_RV200 },
		161	{ "7500 QX", RADEON_RV200 },
		162	{ "9000 Id", RADEON_RV250 },
		163	{ "9000 Ie", RADEON_RV250 },
		164	{ "9000 If", RADEON_RV250 },
		165	{ "9000 Ig", RADEON_RV250 },
		166	{ "M9 Ld", RADEON_M9 },
		167	{ "M9 Le", RADEON_M9 },
		168	{ "M9 Lf", RADEON_M9 },
		169	{ "M9 Lg", RADEON_M9 },
		170	{ "9700 ND", RADEON_R300 },
		171	{ "9700 NE", RADEON_R300 },
		172	{ "9700 NF", RADEON_R300 },
		173	{ "9700 NG", RADEON_R300 },
		174	{ "9100 QM", RADEON_R200 }
		175	};
		176
		177
		178	enum radeon_montype
		179	{
		180	MT_NONE,
		181	MT_CRT, /* CRT */
		182	MT_LCD, /* LCD */
		183	MT_DFP, /* DVI */
		184	MT_CTV, /* composite TV */
		185	MT_STV /* S-Video out */
		186	};
		187
		188
		189	static struct pci_device_id radeonfb_pci_table[] = {
		190	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
		191	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
		192	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
		193	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
		194	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
		195	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
		196	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
		197	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LX},
		198	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
		199	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
		200	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
		201	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QN, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QN},
		202	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QO, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QO},
		203	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ql, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ql},
		204	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_BB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_BB},
		205	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
		206	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QX, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QX},
		207	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Id},
		208	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ie, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ie},
		209	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_If, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_If},
		210	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ig, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ig},
		211	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Ld, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Ld},
		212	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Le, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Le},
		213	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lf, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lf},
		214	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_Lg, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_Lg},
		215	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_ND, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_ND},
		216	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NE},
		217	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NF},
		218	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_NG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_NG},
		219	{ PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RADEON_QM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QM},
		220	{ 0, }
		221	};
		222	MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
		223
		224
		225	typedef struct {
		226	u16 reg;
		227	u32 val;
		228	} reg_val;
		229
		230
		231	/* these common regs are cleared before mode setting so they do not
		232	* interfere with anything
		233	*/
		234	reg_val common_regs[] = {
		235	{ OVR_CLR, 0 },
		236	{ OVR_WID_LEFT_RIGHT, 0 },
		237	{ OVR_WID_TOP_BOTTOM, 0 },
		238	{ OV0_SCALE_CNTL, 0 },
		239	{ SUBPIC_CNTL, 0 },
		240	{ VIPH_CONTROL, 0 },
		241	{ I2C_CNTL_1, 0 },
		242	{ GEN_INT_CNTL, 0 },
		243	{ CAP0_TRIG_CNTL, 0 },
		244	};
		245
		246	reg_val common_regs_m6[] = {
		247	{ OVR_CLR, 0 },
		248	{ OVR_WID_LEFT_RIGHT, 0 },
		249	{ OVR_WID_TOP_BOTTOM, 0 },
		250	{ OV0_SCALE_CNTL, 0 },
		251	{ SUBPIC_CNTL, 0 },
		252	{ GEN_INT_CNTL, 0 },
		253	{ CAP0_TRIG_CNTL, 0 }
		254	};
		255
		256	typedef struct {
		257	u8 clock_chip_type;
		258	u8 struct_size;
		259	u8 accelerator_entry;
		260	u8 VGA_entry;
		261	u16 VGA_table_offset;
		262	u16 POST_table_offset;
		263	u16 XCLK;
		264	u16 MCLK;
		265	u8 num_PLL_blocks;
		266	u8 size_PLL_blocks;
		267	u16 PCLK_ref_freq;
		268	u16 PCLK_ref_divider;
		269	u32 PCLK_min_freq;
		270	u32 PCLK_max_freq;
		271	u16 MCLK_ref_freq;
		272	u16 MCLK_ref_divider;
		273	u32 MCLK_min_freq;
		274	u32 MCLK_max_freq;
		275	u16 XCLK_ref_freq;
		276	u16 XCLK_ref_divider;
		277	u32 XCLK_min_freq;
		278	u32 XCLK_max_freq;
		279	} __attribute__ ((packed)) PLL_BLOCK;
		280
		281
		282	struct pll_info {
		283	int ppll_max;
		284	int ppll_min;
		285	int xclk;
		286	int ref_div;
		287	int ref_clk;
		288	};
		289
		290
		291	struct ram_info {
		292	int ml;
		293	int mb;
		294	int trcd;
		295	int trp;
		296	int twr;
		297	int cl;
		298	int tr2w;
		299	int loop_latency;
		300	int rloop;
		301	};
		302
		303
		304	struct radeon_regs {
		305	/* CRTC regs */
		306	u32 crtc_h_total_disp;
		307	u32 crtc_h_sync_strt_wid;
		308	u32 crtc_v_total_disp;
		309	u32 crtc_v_sync_strt_wid;
		310	u32 crtc_pitch;
		311	u32 crtc_gen_cntl;
		312	u32 crtc_ext_cntl;
		313	u32 dac_cntl;
		314
		315	u32 flags;
		316	u32 pix_clock;
		317	int xres, yres;
		318
		319	/* DDA regs */
		320	u32 dda_config;
		321	u32 dda_on_off;
		322
		323	/* PLL regs */
		324	u32 ppll_div_3;
		325	u32 ppll_ref_div;
		326	u32 vclk_ecp_cntl;
		327
		328	/* Flat panel regs */
		329	u32 fp_crtc_h_total_disp;
		330	u32 fp_crtc_v_total_disp;
		331	u32 fp_gen_cntl;
		332	u32 fp_h_sync_strt_wid;
		333	u32 fp_horz_stretch;
		334	u32 fp_panel_cntl;
		335	u32 fp_v_sync_strt_wid;
		336	u32 fp_vert_stretch;
		337	u32 lvds_gen_cntl;
		338	u32 lvds_pll_cntl;
		339	u32 tmds_crc;
		340	u32 tmds_transmitter_cntl;
		341
		342	#if defined(__BIG_ENDIAN)
		343	u32 surface_cntl;
		344	#endif
		345	};
		346
		347
		348	struct radeonfb_info {
		349	struct fb_info info;
		350
		351	struct radeon_regs state;
		352	struct radeon_regs init_state;
		353
		354	char name[32];
		355	char ram_type[12];
		356
		357	unsigned long mmio_base_phys;
		358	unsigned long fb_base_phys;
		359
		360	unsigned long mmio_base;
		361	unsigned long fb_base;
		362
		363	struct pci_dev *pdev;
		364
		365	unsigned char *EDID;
		366	unsigned char *bios_seg;
		367
		368	u32 pseudo_palette[17];
		369	struct { u8 red, green, blue, pad; } palette[256];
		370
		371	int chipset;
		372	unsigned char arch;
		373	int video_ram;
		374	u8 rev;
		375	int pitch, bpp, depth;
		376	int xres, yres, pixclock;
		377	int xres_virtual, yres_virtual;
		378	u32 accel_flags;
		379
		380	int use_default_var;
		381	int got_dfpinfo;
		382
		383	int hasCRTC2;
		384	int crtDisp_type;
		385	int dviDisp_type;
		386
		387	int panel_xres, panel_yres;
		388	int clock;
		389	int hOver_plus, hSync_width, hblank;
		390	int vOver_plus, vSync_width, vblank;
		391	int hAct_high, vAct_high, interlaced;
		392	int synct, misc;
		393
		394	u32 dp_gui_master_cntl;
		395
		396	struct pll_info pll;
		397	int pll_output_freq, post_div, fb_div;
		398
		399	struct ram_info ram;
		400
		401	int mtrr_hdl;
		402
		403	#ifdef CONFIG_PMAC_PBOOK
		404	int pm_reg;
		405	u32 save_regs[64];
		406	u32 mdll, mdll2;
		407	#endif /* CONFIG_PMAC_PBOOK */
		408	int asleep;
		409
		410	struct radeonfb_info *next;
		411	};
		412
		413
		414	static struct fb_var_screeninfo radeonfb_default_var = {
		415	640, 480, 640, 480, 0, 0, 8, 0,
		416	{0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
		417	0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
		418	0, FB_VMODE_NONINTERLACED
		419	};
		420
		421	/*
		422	* IO macros
		423	*/
		424
		425	#define INREG8(addr) readb((rinfo->mmio_base)+addr)
		426	#define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
		427	#define INREG(addr) readl((rinfo->mmio_base)+addr)
		428	#define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
		429
		430	#define OUTPLL(addr,val) \
		431	do { \
		432	OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000003f) \| 0x00000080); \
		433	OUTREG(CLOCK_CNTL_DATA, val); \
		434	} while(0)
		435
		436	#define OUTPLLP(addr,val,mask) \
		437	do { \
		438	unsigned int _tmp = INPLL(addr); \
		439	_tmp &= (mask); \
		440	_tmp \|= (val); \
		441	OUTPLL(addr, _tmp); \
		442	} while (0)
		443
		444	#define OUTREGP(addr,val,mask) \
		445	do { \
		446	unsigned int _tmp = INREG(addr); \
		447	_tmp &= (mask); \
		448	_tmp \|= (val); \
		449	OUTREG(addr, _tmp); \
		450	} while (0)
		451
		452
		453	static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, u32 addr)
		454	{
		455	OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000003f);
		456	return (INREG(CLOCK_CNTL_DATA));
		457	}
		458
		459	#define INPLL(addr) _INPLL(rinfo, addr)
		460
		461	#define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
		462	(rinfo->dviDisp_type != MT_STV) && \
		463	(rinfo->dviDisp_type != MT_CTV) ? \
		464	rinfo->dviDisp_type : rinfo->crtDisp_type)
		465
		466	static char *GET_MON_NAME(int type)
		467	{
		468	char *pret = NULL;
		469
		470	switch (type) {
		471	case MT_NONE:
		472	pret = "no";
		473	break;
		474	case MT_CRT:
		475	pret = "CRT";
		476	break;
		477	case MT_DFP:
		478	pret = "DFP";
		479	break;
		480	case MT_LCD:
		481	pret = "LCD";
		482	break;
		483	case MT_CTV:
		484	pret = "CTV";
		485	break;
		486	case MT_STV:
		487	pret = "STV";
		488	break;
		489	}
		490
		491	return pret;
		492	}
		493
		494
		495	/*
		496	* 2D engine routines
		497	*/
		498
		499	static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
		500	{
		501	int i;
		502
		503	/* initiate flush */
		504	OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
		505	~RB2D_DC_FLUSH_ALL);
		506
		507	for (i=0; i < 2000000; i++) {
		508	if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
		509	break;
		510	}
		511	}
		512
		513
		514	static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
		515	{
		516	int i;
		517
		518	for (i=0; i<2000000; i++)
		519	if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
		520	return;
		521	}
		522
		523
		524	static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
		525	{
		526	int i;
		527
		528	/* ensure FIFO is empty before waiting for idle */
		529	_radeon_fifo_wait (rinfo, 64);
		530
		531	for (i=0; i<2000000; i++) {
		532	if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
		533	radeon_engine_flush (rinfo);
		534	return;
		535	}
		536	}
		537	}
		538
		539
		540	#define radeon_engine_idle() _radeon_engine_idle(rinfo)
		541	#define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
		542
		543
		544
		545	/*
		546	* helper routines
		547	*/
		548
		549	static __inline__ u32 radeon_get_dstbpp(u16 depth)
		550	{
		551	switch (depth) {
		552	case 8:
		553	return DST_8BPP;
		554	case 15:
		555	return DST_15BPP;
		556	case 16:
		557	return DST_16BPP;
		558	case 32:
		559	return DST_32BPP;
		560	default:
		561	return 0;
		562	}
		563	}
		564
		565
		566	static inline int var_to_depth(const struct fb_var_screeninfo *var)
		567	{
		568	if (var->bits_per_pixel != 16)
		569	return var->bits_per_pixel;
		570	return (var->green.length == 6) ? 16 : 15;
		571	}
		572
		573
		574	static void _radeon_engine_reset(struct radeonfb_info *rinfo)
		575	{
		576	u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
		577
		578	radeon_engine_flush (rinfo);
		579
		580	clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
		581	mclk_cntl = INPLL(MCLK_CNTL);
		582
		583	OUTPLL(MCLK_CNTL, (mclk_cntl \|
		584	FORCEON_MCLKA \|
		585	FORCEON_MCLKB \|
		586	FORCEON_YCLKA \|
		587	FORCEON_YCLKB \|
		588	FORCEON_MC \|
		589	FORCEON_AIC));
		590	rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
		591
		592	OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset \|
		593	SOFT_RESET_CP \|
		594	SOFT_RESET_HI \|
		595	SOFT_RESET_SE \|
		596	SOFT_RESET_RE \|
		597	SOFT_RESET_PP \|
		598	SOFT_RESET_E2 \|
		599	SOFT_RESET_RB);
		600	INREG(RBBM_SOFT_RESET);
		601	OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
		602	~(SOFT_RESET_CP \|
		603	SOFT_RESET_HI \|
		604	SOFT_RESET_SE \|
		605	SOFT_RESET_RE \|
		606	SOFT_RESET_PP \|
		607	SOFT_RESET_E2 \|
		608	SOFT_RESET_RB));
		609	INREG(RBBM_SOFT_RESET);
		610
		611	OUTPLL(MCLK_CNTL, mclk_cntl);
		612	OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
		613	OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
		614
		615	return;
		616	}
		617
		618	#define radeon_engine_reset() _radeon_engine_reset(rinfo)
		619
		620
		621	static __inline__ u8 radeon_get_post_div_bitval(int post_div)
		622	{
		623	switch (post_div) {
		624	case 1:
		625	return 0x00;
		626	case 2:
		627	return 0x01;
		628	case 3:
		629	return 0x04;
		630	case 4:
		631	return 0x02;
		632	case 6:
		633	return 0x06;
		634	case 8:
		635	return 0x03;
		636	case 12:
		637	return 0x07;
		638	default:
		639	return 0x02;
		640	}
		641	}
		642
		643
		644
		645	static __inline__ int round_div(int num, int den)
		646	{
		647	return (num + (den / 2)) / den;
		648	}
		649
		650
		651
		652	static __inline__ int min_bits_req(int val)
		653	{
		654	int bits_req = 0;
		655
		656	if (val == 0)
		657	bits_req = 1;
		658
		659	while (val) {
		660	val >>= 1;
		661	bits_req++;
		662	}
		663
		664	return (bits_req);
		665	}
		666
		667
		668	static __inline__ int _max(int val1, int val2)
		669	{
		670	if (val1 >= val2)
		671	return val1;
		672	else
		673	return val2;
		674	}
		675
		676
		677
		678	/*
		679	* globals
		680	*/
		681
		682	static char *mode_option __initdata;
		683	static char noaccel = 1;
		684	static char mirror = 0;
		685	static int panel_yres __initdata = 0;
		686	static char force_dfp __initdata = 0;
		687	static struct radeonfb_info *board_list = NULL;
		688	static char nomtrr __initdata = 0;
		689
		690	/*
		691	* prototypes
		692	*/
		693
		694	static void radeon_save_state (struct radeonfb_info *rinfo,
		695	struct radeon_regs *save);
		696	static void radeon_engine_init (struct radeonfb_info *rinfo);
		697	static void radeon_write_mode (struct radeonfb_info *rinfo,
		698	struct radeon_regs *mode);
		699	static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
		700	static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
		701	static int radeon_init_disp_var (struct radeonfb_info rinfo, struct fb_var_screeninfo var);
		702	static char radeon_find_rom(struct radeonfb_info rinfo);
		703	static void radeon_get_pllinfo(struct radeonfb_info rinfo, char bios_seg);
		704	static void radeon_get_moninfo (struct radeonfb_info *rinfo);
		705	static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
		706	static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
		707	static void radeon_get_EDID(struct radeonfb_info *rinfo);
		708	static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
		709	static void radeon_update_default_var(struct radeonfb_info *rinfo);
		710
		711	#ifdef CONFIG_PPC_OF
		712
		713	static int radeon_read_OF (struct radeonfb_info *rinfo);
		714	static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
		715	extern struct device_node pci_device_to_OF_node(struct pci_dev dev);
		716
		717	#ifdef CONFIG_PMAC_PBOOK
		718	int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
		719	static struct pmu_sleep_notifier radeon_sleep_notifier = {
		720	radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
		721	};
		722	#endif /* CONFIG_PMAC_PBOOK */
		723	#ifdef CONFIG_PMAC_BACKLIGHT
		724	static int radeon_set_backlight_enable(int on, int level, void *data);
		725	static int radeon_set_backlight_level(int level, void *data);
		726	static struct backlight_controller radeon_backlight_controller = {
		727	radeon_set_backlight_enable,
		728	radeon_set_backlight_level
		729	};
		730	#endif /* CONFIG_PMAC_BACKLIGHT */
		731
		732	#endif /* CONFIG_PPC_OF */
		733
		734
		735	static char radeon_find_rom(struct radeonfb_info rinfo)
		736	{
		737	#if defined(__i386__)
		738	u32 segstart;
		739	char *rom_base;
		740	char *rom;
		741	int stage;
		742	int i,j;
		743	char aty_rom_sig[] = "761295520";
		744	char *radeon_sig[] = {
		745	"RG6",
		746	"RADEON"
		747	};
		748
		749	for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
		750
		751	stage = 1;
		752
		753	rom_base = (char *)ioremap(segstart, 0x1000);
		754
		755	if ((rom_base == 0x55) && ((((rom_base + 1)) & 0xff) == 0xaa))
		756	stage = 2;
		757
		758
		759	if (stage != 2) {
		760	iounmap(rom_base);
		761	continue;
		762	}
		763
		764	rom = rom_base;
		765
		766	for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
		767	if (aty_rom_sig[0] == *rom)
		768	if (strncmp(aty_rom_sig, rom,
		769	strlen(aty_rom_sig)) == 0)
		770	stage = 3;
		771	rom++;
		772	}
		773	if (stage != 3) {
		774	iounmap(rom_base);
		775	continue;
		776	}
		777	rom = rom_base;
		778
		779	for (i = 0; (i < 512) && (stage != 4); i++) {
		780	for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
		781	if (radeon_sig[j][0] == *rom)
		782	if (strncmp(radeon_sig[j], rom,
		783	strlen(radeon_sig[j])) == 0) {
		784	stage = 4;
		785	break;
		786	}
		787	}
		788	rom++;
		789	}
		790	if (stage != 4) {
		791	iounmap(rom_base);
		792	continue;
		793	}
		794
		795	return rom_base;
		796	}
		797	#endif
		798	return NULL;
		799	}
		800
		801
		802
		803
		804	static void radeon_get_pllinfo(struct radeonfb_info rinfo, char bios_seg)
		805	{
		806	void *bios_header;
		807	void *header_ptr;
		808	u16 bios_header_offset, pll_info_offset;
		809	PLL_BLOCK pll;
		810
		811	if (bios_seg) {
		812	bios_header = bios_seg + 0x48L;
		813	header_ptr = bios_header;
		814
		815	bios_header_offset = readw(header_ptr);
		816	bios_header = bios_seg + bios_header_offset;
		817	bios_header += 0x30;
		818
		819	header_ptr = bios_header;
		820	pll_info_offset = readw(header_ptr);
		821	header_ptr = bios_seg + pll_info_offset;
		822
		823	memcpy_fromio(&pll, header_ptr, 50);
		824
		825	rinfo->pll.xclk = (u32)pll.XCLK;
		826	rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
		827	rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
		828	rinfo->pll.ppll_min = pll.PCLK_min_freq;
		829	rinfo->pll.ppll_max = pll.PCLK_max_freq;
		830
		831	printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
		832	rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
		833	} else {
		834	#ifdef CONFIG_PPC_OF
		835	if (radeon_read_OF(rinfo)) {
		836	unsigned int tmp, Nx, M, ref_div, xclk;
		837
		838	tmp = INPLL(M_SPLL_REF_FB_DIV);
		839	ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
		840
		841	Nx = (tmp & 0xff00) >> 8;
		842	M = (tmp & 0xff);
		843	xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
		844	(2 * M)));
		845
		846	rinfo->pll.xclk = xclk;
		847	rinfo->pll.ref_div = ref_div;
		848	rinfo->pll.ppll_min = 12000;
		849	rinfo->pll.ppll_max = 35000;
		850
		851	printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
		852	rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
		853
		854	return;
		855	}
		856	#endif
		857	/* no BIOS or BIOS not found, use defaults */
		858	switch (rinfo->chipset) {
		859	case PCI_DEVICE_ID_ATI_RADEON_QW:
		860	case PCI_DEVICE_ID_ATI_RADEON_QX:
		861	rinfo->pll.ppll_max = 35000;
		862	rinfo->pll.ppll_min = 12000;
		863	rinfo->pll.xclk = 23000;
		864	rinfo->pll.ref_div = 12;
		865	rinfo->pll.ref_clk = 2700;
		866	break;
		867	case PCI_DEVICE_ID_ATI_RADEON_QL:
		868	case PCI_DEVICE_ID_ATI_RADEON_QN:
		869	case PCI_DEVICE_ID_ATI_RADEON_QO:
		870	case PCI_DEVICE_ID_ATI_RADEON_Ql:
		871	case PCI_DEVICE_ID_ATI_RADEON_BB:
		872	rinfo->pll.ppll_max = 35000;
		873	rinfo->pll.ppll_min = 12000;
		874	rinfo->pll.xclk = 27500;
		875	rinfo->pll.ref_div = 12;
		876	rinfo->pll.ref_clk = 2700;
		877	break;
		878	case PCI_DEVICE_ID_ATI_RADEON_Id:
		879	case PCI_DEVICE_ID_ATI_RADEON_Ie:
		880	case PCI_DEVICE_ID_ATI_RADEON_If:
		881	case PCI_DEVICE_ID_ATI_RADEON_Ig:
		882	rinfo->pll.ppll_max = 35000;
		883	rinfo->pll.ppll_min = 12000;
		884	rinfo->pll.xclk = 25000;
		885	rinfo->pll.ref_div = 12;
		886	rinfo->pll.ref_clk = 2700;
		887	break;
		888	case PCI_DEVICE_ID_ATI_RADEON_ND:
		889	case PCI_DEVICE_ID_ATI_RADEON_NE:
		890	case PCI_DEVICE_ID_ATI_RADEON_NF:
		891	case PCI_DEVICE_ID_ATI_RADEON_NG:
		892	rinfo->pll.ppll_max = 40000;
		893	rinfo->pll.ppll_min = 20000;
		894	rinfo->pll.xclk = 27000;
		895	rinfo->pll.ref_div = 12;
		896	rinfo->pll.ref_clk = 2700;
		897	break;
		898	case PCI_DEVICE_ID_ATI_RADEON_QD:
		899	case PCI_DEVICE_ID_ATI_RADEON_QE:
		900	case PCI_DEVICE_ID_ATI_RADEON_QF:
		901	case PCI_DEVICE_ID_ATI_RADEON_QG:
		902	default:
		903	rinfo->pll.ppll_max = 35000;
		904	rinfo->pll.ppll_min = 12000;
		905	rinfo->pll.xclk = 16600;
		906	rinfo->pll.ref_div = 67;
		907	rinfo->pll.ref_clk = 2700;
		908	break;
		909	}
		910
		911	printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
		912	rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
		913	}
		914	}
		915
		916
		917	static void radeon_get_moninfo (struct radeonfb_info *rinfo)
		918	{
		919	unsigned int tmp;
		920
		921	if (force_dfp) {
		922	rinfo->dviDisp_type = MT_DFP;
		923	return;
		924	}
		925
		926	tmp = INREG(RADEON_BIOS_4_SCRATCH);
		927	printk(KERN_DEBUG "radeon_get_moninfo: bios 4 scratch = %x\n", tmp);
		928
		929	if (rinfo->hasCRTC2) {
		930	/* primary DVI port */
		931	if (tmp & 0x08)
		932	rinfo->dviDisp_type = MT_DFP;
		933	else if (tmp & 0x4)
		934	rinfo->dviDisp_type = MT_LCD;
		935	else if (tmp & 0x200)
		936	rinfo->dviDisp_type = MT_CRT;
		937	else if (tmp & 0x10)
		938	rinfo->dviDisp_type = MT_CTV;
		939	else if (tmp & 0x20)
		940	rinfo->dviDisp_type = MT_STV;
		941
		942	/* secondary CRT port */
		943	if (tmp & 0x2)
		944	rinfo->crtDisp_type = MT_CRT;
		945	else if (tmp & 0x800)
		946	rinfo->crtDisp_type = MT_DFP;
		947	else if (tmp & 0x400)
		948	rinfo->crtDisp_type = MT_LCD;
		949	else if (tmp & 0x1000)
		950	rinfo->crtDisp_type = MT_CTV;
		951	else if (tmp & 0x2000)
		952	rinfo->crtDisp_type = MT_STV;
		953	} else {
		954	rinfo->dviDisp_type = MT_NONE;
		955
		956	tmp = INREG(FP_GEN_CNTL);
		957
		958	if (tmp & FP_EN_TMDS)
		959	rinfo->crtDisp_type = MT_DFP;
		960	else
		961	rinfo->crtDisp_type = MT_CRT;
		962	}
		963	}
		964
		965
		966
		967	static void radeon_get_EDID(struct radeonfb_info *rinfo)
		968	{
		969	#ifdef CONFIG_PPC_OF
		970	if (!radeon_get_EDID_OF(rinfo))
		971	RTRACE("radeonfb: could not retrieve EDID from OF\n");
		972	#else
		973	/* XXX use other methods later */
		974	#endif
		975	}
		976
		977
		978	#ifdef CONFIG_PPC_OF
		979	static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
		980	{
		981	struct device_node *dp;
		982	unsigned char *pedid = NULL;
		983	static char *propnames[] = { "DFP,EDID", "LCD,EDID", "EDID", "EDID1", NULL };
		984	int i;
		985
		986	dp = pci_device_to_OF_node(rinfo->pdev);
		987	while (dp != NULL) {
		988	for (i = 0; propnames[i] != NULL; ++i) {
		989	pedid = (unsigned char *)
		990	get_property(dp, propnames[i], NULL);
		991	if (pedid != NULL) {
		992	rinfo->EDID = pedid;
		993	return 1;
		994	}
		995	}
		996	dp = dp->child;
		997	}
		998	return 0;
		999	}
		1000	#endif /* CONFIG_PPC_OF */
		1001
		1002
		1003	static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
		1004	{
		1005	unsigned char *block = rinfo->EDID;
		1006
		1007	if (!block)
		1008	return 0;
		1009
		1010	/* jump to the detailed timing block section */
		1011	block += 54;
		1012
		1013	rinfo->clock = (block[0] + (block[1] << 8));
		1014	rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
		1015	rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
		1016	rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
		1017	rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
		1018	rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
		1019	rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
		1020	rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
		1021	rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
		1022	rinfo->interlaced = ((block[17] & 0x80) >> 7);
		1023	rinfo->synct = ((block[17] & 0x18) >> 3);
		1024	rinfo->misc = ((block[17] & 0x06) >> 1);
		1025	rinfo->hAct_high = rinfo->vAct_high = 0;
		1026	if (rinfo->synct == 3) {
		1027	if (rinfo->misc & 2)
		1028	rinfo->hAct_high = 1;
		1029	if (rinfo->misc & 1)
		1030	rinfo->vAct_high = 1;
		1031	}
		1032
		1033	printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
		1034	rinfo->panel_xres, rinfo->panel_yres);
		1035
		1036	rinfo->got_dfpinfo = 1;
		1037
		1038	return 1;
		1039	}
		1040
		1041
		1042	static void radeon_update_default_var(struct radeonfb_info *rinfo)
		1043	{
		1044	struct fb_var_screeninfo *var = &radeonfb_default_var;
		1045
		1046	var->xres = rinfo->panel_xres;
		1047	var->yres = rinfo->panel_yres;
		1048	var->xres_virtual = rinfo->panel_xres;
		1049	var->yres_virtual = rinfo->panel_yres;
		1050	var->xoffset = var->yoffset = 0;
		1051	var->bits_per_pixel = 8;
		1052	var->pixclock = 100000000 / rinfo->clock;
		1053	var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
		1054	var->right_margin = rinfo->hOver_plus;
		1055	var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
		1056	var->lower_margin = rinfo->vOver_plus;
		1057	var->hsync_len = rinfo->hSync_width;
		1058	var->vsync_len = rinfo->vSync_width;
		1059	var->sync = 0;
		1060	if (rinfo->synct == 3) {
		1061	if (rinfo->hAct_high)
		1062	var->sync \|= FB_SYNC_HOR_HIGH_ACT;
		1063	if (rinfo->vAct_high)
		1064	var->sync \|= FB_SYNC_VERT_HIGH_ACT;
		1065	}
		1066
		1067	var->vmode = 0;
		1068	if (rinfo->interlaced)
		1069	var->vmode \|= FB_VMODE_INTERLACED;
		1070
		1071	rinfo->use_default_var = 1;
		1072	}
		1073
		1074
		1075	static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
		1076	{
		1077	char fpbiosstart, tmp, *tmp0;
		1078	char stmp[30];
		1079	int i;
		1080
		1081	if (!rinfo->bios_seg)
		1082	return 0;
		1083
		1084	if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
		1085	printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
		1086	return 0;
		1087	}
		1088
		1089	if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
		1090	printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
		1091	return 0;
		1092	}
		1093
		1094	for(i=0; i<24; i++)
		1095	stmp[i] = readb(tmp+i+1);
		1096	stmp[24] = 0;
		1097	printk("radeonfb: panel ID string: %s\n", stmp);
		1098	rinfo->panel_xres = readw(tmp + 25);
		1099	rinfo->panel_yres = readw(tmp + 27);
		1100	printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
		1101	rinfo->panel_xres, rinfo->panel_yres);
		1102
		1103	for(i=0; i<20; i++) {
		1104	tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
		1105	if (tmp0 == 0)
		1106	break;
		1107	if ((readw(tmp0) == rinfo->panel_xres) &&
		1108	(readw(tmp0+2) == rinfo->panel_yres)) {
		1109	rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
		1110	rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
		1111	rinfo->hSync_width = readb(tmp0+23) * 8;
		1112	rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
		1113	rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
		1114	rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
		1115	rinfo->clock = readw(tmp0+9);
		1116
		1117	rinfo->got_dfpinfo = 1;
		1118	return 1;
		1119	}
		1120	}
		1121
		1122	return 0;
		1123	}
		1124
		1125
		1126
		1127	static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
		1128	{
		1129	unsigned int tmp;
		1130	unsigned short a, b;
		1131
		1132	if (radeon_get_dfpinfo_BIOS(rinfo))
		1133	radeon_update_default_var(rinfo);
		1134
		1135	if (radeon_dfp_parse_EDID(rinfo))
		1136	radeon_update_default_var(rinfo);
		1137
		1138	if (!rinfo->got_dfpinfo) {
		1139	/*
		1140	* it seems all else has failed now and we
		1141	* resort to probing registers for our DFP info
		1142	*/
		1143	if (panel_yres) {
		1144	rinfo->panel_yres = panel_yres;
		1145	} else {
		1146	tmp = INREG(FP_VERT_STRETCH);
		1147	tmp &= 0x00fff000;
		1148	rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
		1149	}
		1150
		1151	switch (rinfo->panel_yres) {
		1152	case 480:
		1153	rinfo->panel_xres = 640;
		1154	break;
		1155	case 600:
		1156	rinfo->panel_xres = 800;
		1157	break;
		1158	case 768:
		1159	#if defined(__powerpc__)
		1160	if (rinfo->dviDisp_type == MT_LCD)
		1161	rinfo->panel_xres = 1152;
		1162	else
		1163	#endif
		1164	rinfo->panel_xres = 1024;
		1165	break;
		1166	case 1024:
		1167	rinfo->panel_xres = 1280;
		1168	break;
		1169	case 1050:
		1170	rinfo->panel_xres = 1400;
		1171	break;
		1172	case 1200:
		1173	rinfo->panel_xres = 1600;
		1174	break;
		1175	default:
		1176	printk("radeonfb: Failed to detect DFP panel size\n");
		1177	return 0;
		1178	}
		1179
		1180	printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
		1181	rinfo->panel_xres, rinfo->panel_yres);
		1182
		1183	tmp = INREG(FP_CRTC_H_TOTAL_DISP);
		1184	a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
		1185	b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
		1186	rinfo->hblank = (a - b + 1) * 8;
		1187
		1188	tmp = INREG(FP_H_SYNC_STRT_WID);
		1189	rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
		1190	FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
		1191	rinfo->hOver_plus *= 8;
		1192	rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
		1193	FP_H_SYNC_WID_SHIFT);
		1194	rinfo->hSync_width *= 8;
		1195	tmp = INREG(FP_CRTC_V_TOTAL_DISP);
		1196	a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
		1197	b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
		1198	rinfo->vblank = a - b /* + 24 */ ;
		1199
		1200	tmp = INREG(FP_V_SYNC_STRT_WID);
		1201	rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
		1202	- b + 1;
		1203	rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
		1204	FP_V_SYNC_WID_SHIFT);
		1205
		1206	return 1;
		1207	}
		1208
		1209	return 1;
		1210	}
		1211
		1212
		1213	#ifdef CONFIG_PPC_OF
		1214	static int radeon_read_OF (struct radeonfb_info *rinfo)
		1215	{
		1216	struct device_node *dp;
		1217	unsigned int *xtal;
		1218
		1219	dp = pci_device_to_OF_node(rinfo->pdev);
		1220
		1221	xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
		1222
		1223	rinfo->pll.ref_clk = *xtal / 10;
		1224
		1225	if (*xtal)
		1226	return 1;
		1227	else
		1228	return 0;
		1229	}
		1230	#endif
		1231
		1232
		1233	static void radeon_engine_init (struct radeonfb_info *rinfo)
		1234	{
		1235	u32 temp;
		1236
		1237	/* disable 3D engine */
		1238	OUTREG(RB3D_CNTL, 0);
		1239
		1240	radeon_engine_reset ();
		1241
		1242	radeon_fifo_wait (1);
		1243	OUTREG(RB2D_DSTCACHE_MODE, 0);
		1244
		1245	/* XXX */
		1246	rinfo->pitch = ((rinfo->xres_virtual * (rinfo->bpp / 8) + 0x3f)) >> 6;
		1247
		1248	radeon_fifo_wait (1);
		1249	temp = INREG(DEFAULT_PITCH_OFFSET);
		1250	OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) \|
		1251	(rinfo->pitch << 0x16)));
		1252
		1253	radeon_fifo_wait (1);
		1254	OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
		1255
		1256	radeon_fifo_wait (1);
		1257	OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX \|
		1258	DEFAULT_SC_BOTTOM_MAX));
		1259
		1260	temp = radeon_get_dstbpp(rinfo->depth);
		1261	rinfo->dp_gui_master_cntl = ((temp << 8) \| GMC_CLR_CMP_CNTL_DIS);
		1262	radeon_fifo_wait (1);
		1263	OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl \|
		1264	GMC_BRUSH_SOLID_COLOR \|
		1265	GMC_SRC_DATATYPE_COLOR));
		1266
		1267	radeon_fifo_wait (7);
		1268
		1269	/* clear line drawing regs */
		1270	OUTREG(DST_LINE_START, 0);
		1271	OUTREG(DST_LINE_END, 0);
		1272
		1273	/* set brush color regs */
		1274	OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
		1275	OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
		1276
		1277	/* set source color regs */
		1278	OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
		1279	OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
		1280
		1281	/* default write mask */
		1282	OUTREG(DP_WRITE_MSK, 0xffffffff);
		1283
		1284	radeon_engine_idle ();
		1285	}
		1286
		1287
		1288	static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
		1289	{
		1290	struct fb_info *info = &rinfo->info;
		1291	struct fb_var_screeninfo var;
		1292
		1293	var = radeonfb_default_var;
		1294	if ((radeon_init_disp_var(rinfo, &var)) < 0)
		1295	return -1;
		1296
		1297	rinfo->depth = var_to_depth(&var);
		1298	rinfo->bpp = var.bits_per_pixel;
		1299
		1300	info->var = var;
		1301	fb_alloc_cmap(&info->cmap, 256, 0);
		1302
		1303	var.activate = FB_ACTIVATE_NOW;
		1304	return 0;
		1305	}
		1306
		1307
		1308	static int radeon_init_disp_var (struct radeonfb_info *rinfo,
		1309	struct fb_var_screeninfo *var)
		1310	{
		1311	#ifndef MODULE
		1312	if (mode_option)
		1313	fb_find_mode (var, &rinfo->info, mode_option,
		1314	NULL, 0, NULL, 8);
		1315	else
		1316	#endif
		1317	if (rinfo->use_default_var)
		1318	/* We will use the modified default far */
		1319	*var = radeonfb_default_var;
		1320	else
		1321
		1322	fb_find_mode (var, &rinfo->info, "640x480-8@60",
		1323	NULL, 0, NULL, 0);
		1324
		1325	if (noaccel)
		1326	var->accel_flags &= ~FB_ACCELF_TEXT;
		1327	else
		1328	var->accel_flags \|= FB_ACCELF_TEXT;
		1329
		1330	return 0;
		1331	}
		1332
		1333
		1334	static int radeon_do_maximize(struct radeonfb_info *rinfo,
		1335	struct fb_var_screeninfo *var,
		1336	struct fb_var_screeninfo *v,
		1337	int nom, int den)
		1338	{
		1339	static struct {
		1340	int xres, yres;
		1341	} modes[] = {
		1342	{1600, 1280},
		1343	{1280, 1024},
		1344	{1024, 768},
		1345	{800, 600},
		1346	{640, 480},
		1347	{-1, -1}
		1348	};
		1349	int i;
		1350
		1351	/* use highest possible virtual resolution */
		1352	if (v->xres_virtual == -1 && v->yres_virtual == -1) {
		1353	printk("radeonfb: using max available virtual resolution\n");
		1354	for (i=0; modes[i].xres != -1; i++) {
		1355	if (modes[i].xres * nom / den * modes[i].yres <
		1356	rinfo->video_ram / 2)
		1357	break;
		1358	}
		1359	if (modes[i].xres == -1) {
		1360	printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
		1361	return -EINVAL;
		1362	}
		1363	v->xres_virtual = modes[i].xres;
		1364	v->yres_virtual = modes[i].yres;
		1365
		1366	printk("radeonfb: virtual resolution set to max of %dx%d\n",
		1367	v->xres_virtual, v->yres_virtual);
		1368	} else if (v->xres_virtual == -1) {
		1369	v->xres_virtual = (rinfo->video_ram * den /
		1370	(nom * v->yres_virtual * 2)) & ~15;
		1371	} else if (v->yres_virtual == -1) {
		1372	v->xres_virtual = (v->xres_virtual + 15) & ~15;
		1373	v->yres_virtual = rinfo->video_ram * den /
		1374	(nom * v->xres_virtual *2);
		1375	} else {
		1376	if (v->xres_virtual * nom / den * v->yres_virtual >
		1377	rinfo->video_ram) {
		1378	return -EINVAL;
		1379	}
		1380	}
		1381
		1382	if (v->xres_virtual * nom / den >= 8192) {
		1383	v->xres_virtual = 8192 * den / nom - 16;
		1384	}
		1385
		1386	if (v->xres_virtual < v->xres)
		1387	return -EINVAL;
		1388
		1389	if (v->yres_virtual < v->yres)
		1390	return -EINVAL;
		1391
		1392	return 0;
		1393	}
		1394
		1395
		1396	static int radeonfb_check_var (struct fb_var_screeninfo var, struct fb_info info)
		1397	{
		1398	struct radeonfb_info rinfo = (struct radeonfb_info ) info->par;
		1399	struct fb_var_screeninfo v;
		1400	int nom, den;
		1401
		1402	memcpy (&v, var, sizeof (v));
		1403
		1404	switch (v.bits_per_pixel) {
		1405	case 0 ... 8:
		1406	v.bits_per_pixel = 8;
		1407	break;
		1408	case 9 ... 16:
		1409	v.bits_per_pixel = 16;
		1410	break;
		1411	case 17 ... 24:
		1412	#if 0 /* Doesn't seem to work */
		1413	v.bits_per_pixel = 24;
		1414	break;
		1415	#endif
		1416	return -EINVAL;
		1417	case 25 ... 32:
		1418	v.bits_per_pixel = 32;
		1419	break;
		1420	default:
		1421	return -EINVAL;
		1422	}
		1423
		1424	switch (var_to_depth(&v)) {
		1425	case 8:
		1426	nom = den = 1;
		1427	v.red.offset = v.green.offset = v.blue.offset = 0;
		1428	v.red.length = v.green.length = v.blue.length = 8;
		1429	v.transp.offset = v.transp.length = 0;
		1430	break;
		1431	case 15:
		1432	nom = 2;
		1433	den = 1;
		1434	v.red.offset = 10;
		1435	v.green.offset = 5;
		1436	v.blue.offset = 0;
		1437	v.red.length = v.green.length = v.blue.length = 5;
		1438	v.transp.offset = v.transp.length = 0;
		1439	break;
		1440	case 16:
		1441	nom = 2;
		1442	den = 1;
		1443	v.red.offset = 11;
		1444	v.green.offset = 5;
		1445	v.blue.offset = 0;
		1446	v.red.length = 5;
		1447	v.green.length = 6;
		1448	v.blue.length = 5;
		1449	v.transp.offset = v.transp.length = 0;
		1450	break;
		1451	case 24:
		1452	nom = 4;
		1453	den = 1;
		1454	v.red.offset = 16;
		1455	v.green.offset = 8;
		1456	v.blue.offset = 0;
		1457	v.red.length = v.blue.length = v.green.length = 8;
		1458	v.transp.offset = v.transp.length = 0;
		1459	break;
		1460	case 32:
		1461	nom = 4;
		1462	den = 1;
		1463	v.red.offset = 16;
		1464	v.green.offset = 8;
		1465	v.blue.offset = 0;
		1466	v.red.length = v.blue.length = v.green.length = 8;
		1467	v.transp.offset = 24;
		1468	v.transp.length = 8;
		1469	break;
		1470	default:
		1471	printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
		1472	var->xres, var->yres, var->bits_per_pixel);
		1473	return -EINVAL;
		1474	}
		1475
		1476	if (radeon_do_maximize(rinfo, var, &v, nom, den) < 0)
		1477	return -EINVAL;
		1478
		1479	if (v.xoffset < 0)
		1480	v.xoffset = 0;
		1481	if (v.yoffset < 0)
		1482	v.yoffset = 0;
		1483
		1484	if (v.xoffset > v.xres_virtual - v.xres)
		1485	v.xoffset = v.xres_virtual - v.xres - 1;
		1486
		1487	if (v.yoffset > v.yres_virtual - v.yres)
		1488	v.yoffset = v.yres_virtual - v.yres - 1;
		1489
		1490	v.red.msb_right = v.green.msb_right = v.blue.msb_right =
		1491	v.transp.offset = v.transp.length =
		1492	v.transp.msb_right = 0;
		1493
		1494	if (noaccel)
		1495	v.accel_flags = 0;
		1496
		1497	memcpy(var, &v, sizeof(v));
		1498
		1499	return 0;
		1500	}
		1501
		1502
		1503	static int radeonfb_pan_display (struct fb_var_screeninfo *var,
		1504	struct fb_info *info)
		1505	{
		1506	struct radeonfb_info rinfo = (struct radeonfb_info ) info;
		1507
		1508	if ((var->xoffset + var->xres > var->xres_virtual)
		1509	\|\| (var->yoffset + var->yres > var->yres_virtual))
		1510	return -EINVAL;
		1511
		1512	if (rinfo->asleep)
		1513	return 0;
		1514
		1515	OUTREG(CRTC_OFFSET, ((var->yoffset * var->xres_virtual + var->xoffset)
		1516	* var->bits_per_pixel / 8) & ~7);
		1517	return 0;
		1518	}
		1519
		1520
		1521	static int radeonfb_ioctl (struct inode inode, struct file file, unsigned int cmd,
		1522	unsigned long arg, struct fb_info *info)
		1523	{
		1524	struct radeonfb_info rinfo = (struct radeonfb_info ) info;
		1525	unsigned int tmp;
		1526	u32 value = 0;
		1527	int rc;
		1528
		1529	switch (cmd) {
		1530	/*
		1531	* TODO: set mirror accordingly for non-Mobility chipsets with 2 CRTC's
		1532	*/
		1533	case FBIO_RADEON_SET_MIRROR:
		1534	switch (rinfo->arch) {
		1535	case RADEON_R100:
		1536	case RADEON_RV100:
		1537	case RADEON_R200:
		1538	case RADEON_RV200:
		1539	case RADEON_RV250:
		1540	case RADEON_R300:
		1541	return -EINVAL;
		1542	default:
		1543	/* RADEON M6, RADEON_M7, RADEON_M9 */
		1544	break;
		1545	}
		1546
		1547	rc = 0;
475	giacomo	1548	value = (__u32)arg; //get_user(value, (__u32*)arg);
472	giacomo	1549
		1550	if (rc)
		1551	return rc;
		1552
		1553	if (value & 0x01) {
		1554	tmp = INREG(LVDS_GEN_CNTL);
		1555
		1556	tmp \|= (LVDS_ON \| LVDS_BLON);
		1557	} else {
		1558	tmp = INREG(LVDS_GEN_CNTL);
		1559
		1560	tmp &= ~(LVDS_ON \| LVDS_BLON);
		1561	}
		1562
		1563	OUTREG(LVDS_GEN_CNTL, tmp);
		1564
		1565	if (value & 0x02) {
		1566	tmp = INREG(CRTC_EXT_CNTL);
		1567	tmp \|= CRTC_CRT_ON;
		1568
		1569	mirror = 1;
		1570	} else {
		1571	tmp = INREG(CRTC_EXT_CNTL);
		1572	tmp &= ~CRTC_CRT_ON;
		1573
		1574	mirror = 0;
		1575	}
		1576
		1577	OUTREG(CRTC_EXT_CNTL, tmp);
		1578
		1579	break;
		1580	case FBIO_RADEON_GET_MIRROR:
		1581	switch (rinfo->arch) {
		1582	case RADEON_R100:
		1583	case RADEON_RV100:
		1584	case RADEON_R200:
		1585	case RADEON_RV200:
		1586	case RADEON_RV250:
		1587	case RADEON_R300:
		1588	return -EINVAL;
		1589	default:
		1590	/* RADEON M6, RADEON_M7, RADEON_M9 */
		1591	break;
		1592	}
		1593
		1594	tmp = INREG(LVDS_GEN_CNTL);
		1595	if ((LVDS_ON \| LVDS_BLON) & tmp)
		1596	value \|= 0x01;
		1597
		1598	tmp = INREG(CRTC_EXT_CNTL);
		1599	if (CRTC_CRT_ON & tmp)
		1600	value \|= 0x02;
		1601
1056	tullio	1602	// changed for gcc4 compatibility
		1603	//(__u32*)arg = value;
		1604	arg = (__u32*)(value);
475	giacomo	1605	return 0;
472	giacomo	1606	default:
		1607	return -EINVAL;
		1608	}
		1609
		1610	return -EINVAL;
		1611	}
		1612
		1613
		1614	static int radeonfb_blank (int blank, struct fb_info *info)
		1615	{
		1616	struct radeonfb_info rinfo = (struct radeonfb_info ) info;
		1617	u32 val = INREG(CRTC_EXT_CNTL);
		1618	u32 val2 = INREG(LVDS_GEN_CNTL);
		1619
		1620	if (rinfo->asleep)
		1621	return 0;
		1622
		1623	#ifdef CONFIG_PMAC_BACKLIGHT
		1624	if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
		1625	set_backlight_enable(!blank);
		1626	return 0;
		1627	}
		1628	#endif
		1629
		1630	/* reset it */
		1631	val &= ~(CRTC_DISPLAY_DIS \| CRTC_HSYNC_DIS \|
		1632	CRTC_VSYNC_DIS);
		1633	val2 &= ~(LVDS_DISPLAY_DIS);
		1634
		1635	switch (blank) {
		1636	case VESA_NO_BLANKING:
		1637	break;
		1638	case VESA_VSYNC_SUSPEND:
		1639	val \|= (CRTC_DISPLAY_DIS \| CRTC_VSYNC_DIS);
		1640	break;
		1641	case VESA_HSYNC_SUSPEND:
		1642	val \|= (CRTC_DISPLAY_DIS \| CRTC_HSYNC_DIS);
		1643	break;
		1644	case VESA_POWERDOWN:
		1645	val \|= (CRTC_DISPLAY_DIS \| CRTC_VSYNC_DIS \|
		1646	CRTC_HSYNC_DIS);
		1647	val2 \|= (LVDS_DISPLAY_DIS);
		1648	break;
		1649	}
		1650
		1651	switch (rinfo->dviDisp_type) {
		1652	case MT_LCD:
		1653	OUTREG(LVDS_GEN_CNTL, val2);
		1654	break;
		1655	case MT_CRT:
		1656	default:
		1657	OUTREG(CRTC_EXT_CNTL, val);
		1658	break;
		1659	}
		1660
		1661	return 0;
		1662	}
		1663
		1664
		1665	static int radeonfb_setcolreg (unsigned regno, unsigned red, unsigned green,
		1666	unsigned blue, unsigned transp, struct fb_info *info)
		1667	{
		1668	struct radeonfb_info rinfo = (struct radeonfb_info ) info;
		1669	u32 pindex, vclk_cntl;
		1670	unsigned int i;
		1671
		1672	if (regno > 255)
		1673	return 1;
		1674
		1675	red >>= 8;
		1676	green >>= 8;
		1677	blue >>= 8;
		1678	rinfo->palette[regno].red = red;
		1679	rinfo->palette[regno].green = green;
		1680	rinfo->palette[regno].blue = blue;
		1681
		1682	/* default */
		1683	pindex = regno;
		1684
		1685	if (!rinfo->asleep) {
		1686	vclk_cntl = INPLL(VCLK_ECP_CNTL);
		1687	OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
		1688
		1689	if (rinfo->bpp == 16) {
		1690	pindex = regno * 8;
		1691
		1692	if (rinfo->depth == 16 && regno > 63)
		1693	return 1;
		1694	if (rinfo->depth == 15 && regno > 31)
		1695	return 1;
		1696
		1697	/* For 565, the green component is mixed one order below */
		1698	if (rinfo->depth == 16) {
		1699	OUTREG(PALETTE_INDEX, pindex>>1);
		1700	OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) \|
		1701	(green << 8) \| (rinfo->palette[regno>>1].blue));
		1702	green = rinfo->palette[regno<<1].green;
		1703	}
		1704	}
		1705
		1706	if (rinfo->depth != 16 \|\| regno < 32) {
		1707	OUTREG(PALETTE_INDEX, pindex);
		1708	OUTREG(PALETTE_DATA, (red << 16) \| (green << 8) \| blue);
		1709	}
		1710
		1711	OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
		1712	}
		1713	if (regno < 16) {
		1714	switch (rinfo->depth) {
		1715	case 15:
		1716	((u16 *) (info->pseudo_palette))[regno] =
		1717	(regno << 10) \| (regno << 5) \| regno;
		1718	break;
		1719	case 16:
		1720	((u16 *) (info->pseudo_palette))[regno] =
		1721	(regno << 11) \| (regno << 6) \| regno;
		1722	break;
		1723	case 24:
		1724	((u32 *) (info->pseudo_palette))[regno] =
		1725	(regno << 16) \| (regno << 8) \| regno;
		1726	break;
		1727	case 32:
		1728	i = (regno << 8) \| regno;
		1729	((u32 *) (info->pseudo_palette))[regno] =
		1730	(i << 16) \| i;
		1731	break;
		1732	}
		1733	}
		1734	return 0;
		1735	}
		1736
		1737
		1738
		1739	static void radeon_save_state (struct radeonfb_info *rinfo,
		1740	struct radeon_regs *save)
		1741	{
		1742	/* CRTC regs */
		1743	save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
		1744	save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
		1745	save->dac_cntl = INREG(DAC_CNTL);
		1746	save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
		1747	save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
		1748	save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
		1749	save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
		1750	save->crtc_pitch = INREG(CRTC_PITCH);
		1751	#if defined(__BIG_ENDIAN)
		1752	save->surface_cntl = INREG(SURFACE_CNTL);
		1753	#endif
		1754
		1755	/* FP regs */
		1756	save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
		1757	save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
		1758	save->fp_gen_cntl = INREG(FP_GEN_CNTL);
		1759	save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
		1760	save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
		1761	save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
		1762	save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
		1763	save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
		1764	save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
		1765	save->tmds_crc = INREG(TMDS_CRC);
		1766	save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
		1767	save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
		1768	}
		1769
		1770
		1771
		1772	static int radeonfb_set_par (struct fb_info *info)
		1773	{
		1774	struct radeonfb_info rinfo = (struct radeonfb_info )info->par;
		1775	struct fb_var_screeninfo *mode = &info->var;
		1776	struct radeon_regs newmode;
		1777	int hTotal, vTotal, hSyncStart, hSyncEnd,
		1778	hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
		1779	u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
		1780	u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
		1781	u32 dotClock = 1000000000 / mode->pixclock,
		1782	sync, h_sync_pol, v_sync_pol;
		1783	int freq = dotClock / 10; /* x 100 */
		1784	int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
		1785	int useable_precision, roff, ron;
		1786	int min_bits, format = 0;
		1787	int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
		1788	int primary_mon = PRIMARY_MONITOR(rinfo);
		1789	int depth = var_to_depth(mode);
		1790
		1791	rinfo->xres = mode->xres;
		1792	rinfo->yres = mode->yres;
		1793	rinfo->xres_virtual = mode->xres_virtual;
		1794	rinfo->yres_virtual = mode->yres_virtual;
		1795	rinfo->pixclock = mode->pixclock;
		1796
		1797	hSyncStart = mode->xres + mode->right_margin;
		1798	hSyncEnd = hSyncStart + mode->hsync_len;
		1799	hTotal = hSyncEnd + mode->left_margin;
		1800
		1801	vSyncStart = mode->yres + mode->lower_margin;
		1802	vSyncEnd = vSyncStart + mode->vsync_len;
		1803	vTotal = vSyncEnd + mode->upper_margin;
		1804
		1805	if ((primary_mon == MT_DFP) \|\| (primary_mon == MT_LCD)) {
		1806	if (rinfo->panel_xres < mode->xres)
		1807	rinfo->xres = mode->xres = rinfo->panel_xres;
		1808	if (rinfo->panel_yres < mode->yres)
		1809	rinfo->yres = mode->yres = rinfo->panel_yres;
		1810
		1811	hTotal = mode->xres + rinfo->hblank;
		1812	hSyncStart = mode->xres + rinfo->hOver_plus;
		1813	hSyncEnd = hSyncStart + rinfo->hSync_width;
		1814
		1815	vTotal = mode->yres + rinfo->vblank;
		1816	vSyncStart = mode->yres + rinfo->vOver_plus;
		1817	vSyncEnd = vSyncStart + rinfo->vSync_width;
		1818	}
		1819
		1820	sync = mode->sync;
		1821	h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
		1822	v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
		1823
		1824	RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
		1825	hSyncStart, hSyncEnd, hTotal);
		1826	RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
		1827	vSyncStart, vSyncEnd, vTotal);
		1828
		1829	hsync_wid = (hSyncEnd - hSyncStart) / 8;
		1830	vsync_wid = vSyncEnd - vSyncStart;
		1831	if (hsync_wid == 0)
		1832	hsync_wid = 1;
		1833	else if (hsync_wid > 0x3f) /* max */
		1834	hsync_wid = 0x3f;
		1835
		1836	if (vsync_wid == 0)
		1837	vsync_wid = 1;
		1838	else if (vsync_wid > 0x1f) /* max */
		1839	vsync_wid = 0x1f;
		1840
		1841	hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
		1842	vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
		1843
		1844	cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
		1845
		1846	format = radeon_get_dstbpp(depth);
		1847	bytpp = mode->bits_per_pixel >> 3;
		1848
		1849	if ((primary_mon == MT_DFP) \|\| (primary_mon == MT_LCD))
		1850	hsync_fudge = hsync_fudge_fp[format-1];
		1851	else
		1852	hsync_fudge = hsync_adj_tab[format-1];
		1853
		1854	hsync_start = hSyncStart - 8 + hsync_fudge;
		1855
		1856	newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN \| CRTC_EN \|
		1857	(format << 8);
		1858
		1859	if ((primary_mon == MT_DFP) \|\| (primary_mon == MT_LCD)) {
		1860	newmode.crtc_ext_cntl = VGA_ATI_LINEAR \| XCRT_CNT_EN;
		1861	if (mirror)
		1862	newmode.crtc_ext_cntl \|= CRTC_CRT_ON;
		1863
		1864	newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN \|
		1865	CRTC_INTERLACE_EN);
		1866	} else {
		1867	newmode.crtc_ext_cntl = VGA_ATI_LINEAR \| XCRT_CNT_EN \|
		1868	CRTC_CRT_ON;
		1869	}
		1870
		1871	newmode.dac_cntl = /* INREG(DAC_CNTL) \| */ DAC_MASK_ALL \| DAC_VGA_ADR_EN \|
		1872	DAC_8BIT_EN;
		1873
		1874	newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) \|
		1875	(((mode->xres / 8) - 1) << 16));
		1876
		1877	newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) \|
		1878	(hsync_wid << 16) \| (h_sync_pol << 23));
		1879
		1880	newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) \|
		1881	((mode->yres - 1) << 16);
		1882
		1883	newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) \|
		1884	(vsync_wid << 16) \| (v_sync_pol << 23));
		1885
		1886	newmode.crtc_pitch = (mode->xres_virtual >> 3);
		1887	newmode.crtc_pitch \|= (newmode.crtc_pitch << 16);
		1888
		1889	#if defined(__BIG_ENDIAN)
		1890	/*
		1891	* It looks like recent chips have a problem with SURFACE_CNTL,
		1892	* setting SURF_TRANSLATION_DIS completely disables the
		1893	* swapper as well, so we leave it unset now.
		1894	*/
		1895	newmode.surface_cntl = 0;
		1896
		1897	/* Setup swapping on both apertures, though we currently
		1898	* only use aperture 0, enabling swapper on aperture 1
		1899	* won't harm
		1900	*/
		1901	switch (mode->bits_per_pixel) {
		1902	case 16:
		1903	newmode.surface_cntl \|= NONSURF_AP0_SWP_16BPP;
		1904	newmode.surface_cntl \|= NONSURF_AP1_SWP_16BPP;
		1905	break;
		1906	case 24:
		1907	case 32:
		1908	newmode.surface_cntl \|= NONSURF_AP0_SWP_32BPP;
		1909	newmode.surface_cntl \|= NONSURF_AP1_SWP_32BPP;
		1910	break;
		1911	}
		1912	#endif
		1913
		1914	rinfo->pitch = ((mode->xres_virtual * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
		1915	& ~(0x3f)) / 64;
		1916
		1917	RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
		1918	newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
		1919	RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
		1920	newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
		1921
		1922	newmode.xres = mode->xres;
		1923	newmode.yres = mode->yres;
		1924
		1925	rinfo->bpp = mode->bits_per_pixel;
		1926	rinfo->depth = depth;
		1927
		1928	if (freq > rinfo->pll.ppll_max)
		1929	freq = rinfo->pll.ppll_max;
		1930	if (freq*12 < rinfo->pll.ppll_min)
		1931	freq = rinfo->pll.ppll_min / 12;
		1932
		1933	{
		1934	struct {
		1935	int divider;
		1936	int bitvalue;
		1937	} *post_div,
		1938	post_divs[] = {
		1939	{ 1, 0 },
		1940	{ 2, 1 },
		1941	{ 4, 2 },
		1942	{ 8, 3 },
		1943	{ 3, 4 },
		1944	{ 16, 5 },
		1945	{ 6, 6 },
		1946	{ 12, 7 },
		1947	{ 0, 0 },
		1948	};
		1949
		1950	for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
		1951	rinfo->pll_output_freq = post_div->divider * freq;
		1952	if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
		1953	rinfo->pll_output_freq <= rinfo->pll.ppll_max)
		1954	break;
		1955	}
		1956
		1957	rinfo->post_div = post_div->divider;
		1958	rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
		1959	rinfo->pll.ref_clk);
		1960	newmode.ppll_ref_div = rinfo->pll.ref_div;
		1961	newmode.ppll_div_3 = rinfo->fb_div \| (post_div->bitvalue << 16);
		1962	}
		1963	newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
		1964
		1965	#ifdef CONFIG_PPC_OF
		1966	/* Gross hack for iBook with M7 until I find out a proper fix */
		1967	if (machine_is_compatible("PowerBook4,3") && rinfo->arch == RADEON_M7)
		1968	newmode.ppll_div_3 = 0x000600ad;
		1969	#endif /* CONFIG_PPC_OF */
		1970
		1971	RTRACE("post div = 0x%x\n", rinfo->post_div);
		1972	RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
		1973	RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
		1974
		1975	/* DDA */
		1976	vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
		1977	rinfo->pll.ref_div * rinfo->post_div);
		1978	xclk_freq = rinfo->pll.xclk;
		1979
		1980	xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
		1981
		1982	min_bits = min_bits_req(xclk_per_trans);
		1983	useable_precision = min_bits + 1;
		1984
		1985	xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
		1986	vclk_freq * mode->bits_per_pixel);
		1987
		1988	ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
		1989	2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
		1990	xclk_per_trans) << (11 - useable_precision);
		1991	roff = xclk_per_trans_precise * (32 - 4);
		1992
		1993	RTRACE("ron = %d, roff = %d\n", ron, roff);
		1994	RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
		1995
		1996	if ((ron + rinfo->ram.rloop) >= roff) {
		1997	printk("radeonfb: error ron out of range\n");
		1998	return -EINVAL;
		1999	}
		2000
		2001	newmode.dda_config = (xclk_per_trans_precise \|
		2002	(useable_precision << 16) \|
		2003	(rinfo->ram.rloop << 20));
		2004	newmode.dda_on_off = (ron << 16) \| roff;
		2005
		2006	if ((primary_mon == MT_DFP) \|\| (primary_mon == MT_LCD)) {
		2007	unsigned int hRatio, vRatio;
		2008
		2009	/* We force the pixel clock to be always enabled. Allowing it
		2010	* to be power managed during blanking would save power, but has
		2011	* nasty interactions with the 2D engine & sleep code that haven't
		2012	* been solved yet. --BenH
		2013	*/
		2014	newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
		2015
		2016	if (mode->xres > rinfo->panel_xres)
		2017	mode->xres = rinfo->panel_xres;
		2018	if (mode->yres > rinfo->panel_yres)
		2019	mode->yres = rinfo->panel_yres;
		2020
		2021	newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
		2022	<< HORZ_PANEL_SHIFT);
		2023	newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
		2024	<< VERT_PANEL_SHIFT);
		2025
		2026	if (mode->xres != rinfo->panel_xres) {
		2027	hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
		2028	rinfo->panel_xres);
		2029	newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) \|
		2030	(newmode.fp_horz_stretch &
		2031	(HORZ_PANEL_SIZE \| HORZ_FP_LOOP_STRETCH \|
		2032	HORZ_AUTO_RATIO_INC)));
		2033	newmode.fp_horz_stretch \|= (HORZ_STRETCH_BLEND \|
		2034	HORZ_STRETCH_ENABLE);
		2035	}
		2036	newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
		2037
		2038	if (mode->yres != rinfo->panel_yres) {
		2039	vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
		2040	rinfo->panel_yres);
		2041	newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) \|
		2042	(newmode.fp_vert_stretch &
		2043	(VERT_PANEL_SIZE \| VERT_STRETCH_RESERVED)));
		2044	newmode.fp_vert_stretch \|= (VERT_STRETCH_BLEND \|
		2045	VERT_STRETCH_ENABLE);
		2046	}
		2047	newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
		2048
		2049	newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
		2050	~(FP_SEL_CRTC2 \|
		2051	FP_RMX_HVSYNC_CONTROL_EN \|
		2052	FP_DFP_SYNC_SEL \|
		2053	FP_CRT_SYNC_SEL \|
		2054	FP_CRTC_LOCK_8DOT \|
		2055	FP_USE_SHADOW_EN \|
		2056	FP_CRTC_USE_SHADOW_VEND \|
		2057	FP_CRT_SYNC_ALT));
		2058
		2059	newmode.fp_gen_cntl \|= (FP_CRTC_DONT_SHADOW_VPAR \|
		2060	FP_CRTC_DONT_SHADOW_HEND);
		2061
		2062	newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
		2063	newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
		2064	newmode.tmds_crc = rinfo->init_state.tmds_crc;
		2065	newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
		2066
		2067	if (primary_mon == MT_LCD) {
		2068	newmode.lvds_gen_cntl \|= (LVDS_ON \| LVDS_BLON);
		2069	newmode.fp_gen_cntl &= ~(FP_FPON \| FP_TMDS_EN);
		2070	} else {
		2071	/* DFP */
		2072	newmode.fp_gen_cntl \|= (FP_FPON \| FP_TMDS_EN);
		2073	newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST \|
		2074	ICHCSEL \| TMDS_PLL_EN) &
		2075	~(TMDS_PLLRST);
		2076	newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
		2077	}
		2078
		2079	newmode.fp_crtc_h_total_disp = (((rinfo->hblank / 8) & 0x3ff) \|
		2080	(((mode->xres / 8) - 1) << 16));
		2081	newmode.fp_crtc_v_total_disp = (rinfo->vblank & 0xffff) \|
		2082	((mode->yres - 1) << 16);
		2083	newmode.fp_h_sync_strt_wid = ((rinfo->hOver_plus & 0x1fff) \|
		2084	(hsync_wid << 16) \| (h_sync_pol << 23));
		2085	newmode.fp_v_sync_strt_wid = ((rinfo->vOver_plus & 0xfff) \|
		2086	(vsync_wid << 16) \| (v_sync_pol << 23));
		2087	}
		2088
		2089	/* do it! */
		2090	if (!rinfo->asleep) {
		2091	radeon_write_mode (rinfo, &newmode);
		2092	/* (re)initialize the engine */
		2093	if (!noaccel)
		2094	radeon_engine_init (rinfo);
		2095
		2096	}
		2097	/* Update fix */
		2098	info->fix.line_length = rinfo->pitch*64;
		2099	info->fix.visual = rinfo->depth == 8 ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
		2100
		2101	#ifdef CONFIG_BOOTX_TEXT
		2102	/* Update debug text engine */
		2103	btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
		2104	rinfo->depth, rinfo->pitch*64);
		2105	#endif
		2106
		2107	return 0;
		2108	}
		2109
		2110
		2111	static void radeon_write_mode (struct radeonfb_info *rinfo,
		2112	struct radeon_regs *mode)
		2113	{
		2114	int i;
		2115	int primary_mon = PRIMARY_MONITOR(rinfo);
		2116
		2117	radeonfb_blank(VESA_POWERDOWN, (struct fb_info *)rinfo);
		2118
		2119
		2120	if (rinfo->arch == RADEON_M6) {
		2121	for (i=0; i<8; i++)
		2122	OUTREG(common_regs_m6[i].reg, common_regs_m6[i].val);
		2123	} else {
		2124	for (i=0; i<9; i++)
		2125	OUTREG(common_regs[i].reg, common_regs[i].val);
		2126	}
		2127
		2128	OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
		2129	OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
		2130	CRTC_HSYNC_DIS \| CRTC_VSYNC_DIS \| CRTC_DISPLAY_DIS);
		2131	OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL \| DAC_BLANKING);
		2132	OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
		2133	OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
		2134	OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
		2135	OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
		2136	OUTREG(CRTC_OFFSET, 0);
		2137	OUTREG(CRTC_OFFSET_CNTL, 0);
		2138	OUTREG(CRTC_PITCH, mode->crtc_pitch);
		2139
		2140	#if defined(__BIG_ENDIAN)
		2141	OUTREG(SURFACE_CNTL, mode->surface_cntl);
		2142	#endif
		2143
		2144	while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
		2145	PPLL_DIV_SEL_MASK) {
		2146	OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
		2147	}
		2148
		2149	OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
		2150
		2151	while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
		2152	(mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
		2153	OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
		2154	}
		2155
		2156	while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
		2157	(mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
		2158	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
		2159	}
		2160
		2161	while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
		2162	(mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
		2163	OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
		2164	}
		2165
		2166	OUTPLL(HTOTAL_CNTL, 0);
		2167
		2168	OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
		2169
		2170	// OUTREG(DDA_CONFIG, mode->dda_config);
		2171	// OUTREG(DDA_ON_OFF, mode->dda_on_off);
		2172
		2173	if ((primary_mon == MT_DFP) \|\| (primary_mon == MT_LCD)) {
		2174	OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
		2175	OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
		2176	OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
		2177	OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
		2178	OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
		2179	OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
		2180	OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
		2181	OUTREG(TMDS_CRC, mode->tmds_crc);
		2182	OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
		2183
		2184	if (primary_mon == MT_LCD) {
		2185	unsigned int tmp = INREG(LVDS_GEN_CNTL);
		2186
		2187	mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
		2188	mode->lvds_gen_cntl \|= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
		2189
		2190	if ((tmp & (LVDS_ON \| LVDS_BLON)) ==
		2191	(mode->lvds_gen_cntl & (LVDS_ON \| LVDS_BLON))) {
		2192	OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
		2193	} else {
		2194	if (mode->lvds_gen_cntl & (LVDS_ON \| LVDS_BLON)) {
		2195	udelay(1000);
		2196	OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
		2197	} else {
		2198	OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl \|
		2199	LVDS_BLON);
		2200	udelay(1000);
		2201	OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
		2202	}
		2203	}
		2204	}
		2205	}
		2206
		2207	radeonfb_blank(VESA_NO_BLANKING, (struct fb_info *)rinfo);
		2208
		2209	OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
		2210
		2211	return;
		2212	}
		2213
		2214	static struct fb_ops radeonfb_ops = {
		2215	.owner = THIS_MODULE,
		2216	.fb_check_var = radeonfb_check_var,
		2217	.fb_set_par = radeonfb_set_par,
		2218	.fb_setcolreg = radeonfb_setcolreg,
		2219	.fb_pan_display = radeonfb_pan_display,
		2220	.fb_blank = radeonfb_blank,
		2221	.fb_ioctl = radeonfb_ioctl,
		2222	#if 0
		2223	.fb_fillrect = radeonfb_fillrect,
		2224	.fb_copyarea = radeonfb_copyarea,
		2225	.fb_imageblit = radeonfb_imageblit,
		2226	.fb_rasterimg = radeonfb_rasterimg,
		2227	#else
		2228	.fb_fillrect = cfb_fillrect,
		2229	.fb_copyarea = cfb_copyarea,
		2230	.fb_imageblit = cfb_imageblit,
		2231	#endif
		2232	.fb_cursor = soft_cursor,
		2233	};
		2234
		2235
		2236	static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
		2237	{
		2238	struct fb_info *info;
		2239
		2240	info = &rinfo->info;
		2241
		2242	info->currcon = -1;
		2243	info->par = rinfo;
		2244	info->pseudo_palette = rinfo->pseudo_palette;
		2245	info->flags = FBINFO_FLAG_DEFAULT;
		2246	info->fbops = &radeonfb_ops;
		2247	info->display_fg = NULL;
		2248	info->screen_base = (char *)rinfo->fb_base;
		2249
		2250	/* Fill fix common fields */
		2251	strncpy(info->fix.id, rinfo->name, sizeof(info->fix.id));
		2252	info->fix.smem_start = rinfo->fb_base_phys;
		2253	info->fix.smem_len = rinfo->video_ram;
		2254	info->fix.type = FB_TYPE_PACKED_PIXELS;
		2255	info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
		2256	info->fix.xpanstep = 8;
		2257	info->fix.ypanstep = 1;
		2258	info->fix.ywrapstep = 0;
		2259	info->fix.type_aux = 0;
		2260	info->fix.mmio_start = rinfo->mmio_base_phys;
		2261	info->fix.mmio_len = RADEON_REGSIZE;
		2262	if (noaccel)
		2263	info->fix.accel = FB_ACCEL_NONE;
		2264	else
		2265	info->fix.accel = FB_ACCEL_ATI_RADEON;
		2266
		2267	if (radeon_init_disp (rinfo) < 0)
		2268	return -1;
		2269
		2270	return 0;
		2271	}
		2272
		2273
		2274	#ifdef CONFIG_PMAC_BACKLIGHT
		2275
		2276	/* TODO: Dbl check these tables, we don't go up to full ON backlight
		2277	* in these, possibly because we noticed MacOS doesn't, but I'd prefer
		2278	* having some more official numbers from ATI
		2279	*/
		2280	static int backlight_conv_m6[] = {
		2281	0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
		2282	0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
		2283	};
		2284	static int backlight_conv_m7[] = {
		2285	0x00, 0x3f, 0x4a, 0x55, 0x60, 0x6b, 0x76, 0x81,
		2286	0x8c, 0x97, 0xa2, 0xad, 0xb8, 0xc3, 0xce, 0xd9
		2287	};
		2288
		2289	#define BACKLIGHT_LVDS_OFF
		2290	#undef BACKLIGHT_DAC_OFF
		2291
		2292	/* We turn off the LCD completely instead of just dimming the backlight.
		2293	* This provides some greater power saving and the display is useless
		2294	* without backlight anyway.
		2295	*/
		2296
		2297	static int radeon_set_backlight_enable(int on, int level, void *data)
		2298	{
		2299	struct radeonfb_info rinfo = (struct radeonfb_info )data;
		2300	unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
		2301	int* conv_table;
		2302
		2303	/* Pardon me for that hack... maybe some day we can figure
		2304	* out in what direction backlight should work on a given
		2305	* panel ?
		2306	*/
		2307	if ((rinfo->arch == RADEON_M7 \|\| rinfo->arch == RADEON_M9)
		2308	&& !machine_is_compatible("PowerBook4,3"))
		2309	conv_table = backlight_conv_m7;
		2310	else
		2311	conv_table = backlight_conv_m6;
		2312
		2313	lvds_gen_cntl \|= (LVDS_BL_MOD_EN \| LVDS_BLON);
		2314	if (on && (level > BACKLIGHT_OFF)) {
		2315	lvds_gen_cntl \|= LVDS_DIGON;
		2316	if (!lvds_gen_cntl & LVDS_ON) {
		2317	lvds_gen_cntl &= ~LVDS_BLON;
		2318	OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		2319	(void)INREG(LVDS_GEN_CNTL);
		2320	mdelay(10);
		2321	lvds_gen_cntl \|= LVDS_BLON;
		2322	OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		2323	}
		2324	lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
		2325	lvds_gen_cntl \|= (conv_table[level] <<
		2326	LVDS_BL_MOD_LEVEL_SHIFT);
		2327	lvds_gen_cntl \|= (LVDS_ON \| LVDS_EN);
		2328	lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
		2329	} else {
		2330	lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
		2331	lvds_gen_cntl \|= (conv_table[0] <<
		2332	LVDS_BL_MOD_LEVEL_SHIFT);
		2333	lvds_gen_cntl \|= LVDS_DISPLAY_DIS;
		2334	OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		2335	udelay(10);
		2336	lvds_gen_cntl &= ~(LVDS_ON \| LVDS_EN \| LVDS_BLON \| LVDS_DIGON);
		2337	}
		2338
		2339	OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
		2340	rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
		2341	rinfo->init_state.lvds_gen_cntl \|= (lvds_gen_cntl & LVDS_STATE_MASK);
		2342
		2343	return 0;
		2344	}
		2345
		2346	static int radeon_set_backlight_level(int level, void *data)
		2347	{
		2348	return radeon_set_backlight_enable(1, level, data);
		2349	}
		2350	#endif /* CONFIG_PMAC_BACKLIGHT */
		2351
		2352
		2353	#ifdef CONFIG_PMAC_PBOOK
		2354
		2355	static u32 dbg_clk;
		2356
		2357	/*
		2358	* Radeon M6 Power Management code. This code currently only supports
		2359	* the mobile chips, it's based from some informations provided by ATI
		2360	* along with hours of tracing of MacOS drivers
		2361	*/
		2362
		2363	static void radeon_pm_save_regs(struct radeonfb_info *rinfo)
		2364	{
		2365	rinfo->save_regs[0] = INPLL(PLL_PWRMGT_CNTL);
		2366	rinfo->save_regs[1] = INPLL(CLK_PWRMGT_CNTL);
		2367	rinfo->save_regs[2] = INPLL(MCLK_CNTL);
		2368	rinfo->save_regs[3] = INPLL(SCLK_CNTL);
		2369	rinfo->save_regs[4] = INPLL(CLK_PIN_CNTL);
		2370	rinfo->save_regs[5] = INPLL(VCLK_ECP_CNTL);
		2371	rinfo->save_regs[6] = INPLL(PIXCLKS_CNTL);
		2372	rinfo->save_regs[7] = INPLL(MCLK_MISC);
		2373	rinfo->save_regs[8] = INPLL(P2PLL_CNTL);
		2374
		2375	rinfo->save_regs[9] = INREG(DISP_MISC_CNTL);
		2376	rinfo->save_regs[10] = INREG(DISP_PWR_MAN);
		2377	rinfo->save_regs[11] = INREG(LVDS_GEN_CNTL);
		2378	rinfo->save_regs[12] = INREG(LVDS_PLL_CNTL);
		2379	rinfo->save_regs[13] = INREG(TV_DAC_CNTL);
		2380	rinfo->save_regs[14] = INREG(BUS_CNTL1);
		2381	rinfo->save_regs[15] = INREG(CRTC_OFFSET_CNTL);
		2382	rinfo->save_regs[16] = INREG(AGP_CNTL);
		2383	rinfo->save_regs[17] = (INREG(CRTC_GEN_CNTL) & 0xfdffffff) \| 0x04000000;
		2384	rinfo->save_regs[18] = (INREG(CRTC2_GEN_CNTL) & 0xfdffffff) \| 0x04000000;
		2385	rinfo->save_regs[19] = INREG(GPIOPAD_A);
		2386	rinfo->save_regs[20] = INREG(GPIOPAD_EN);
		2387	rinfo->save_regs[21] = INREG(GPIOPAD_MASK);
		2388	rinfo->save_regs[22] = INREG(ZV_LCDPAD_A);
		2389	rinfo->save_regs[23] = INREG(ZV_LCDPAD_EN);
		2390	rinfo->save_regs[24] = INREG(ZV_LCDPAD_MASK);
		2391	rinfo->save_regs[25] = INREG(GPIO_VGA_DDC);
		2392	rinfo->save_regs[26] = INREG(GPIO_DVI_DDC);
		2393	rinfo->save_regs[27] = INREG(GPIO_MONID);
		2394	rinfo->save_regs[28] = INREG(GPIO_CRT2_DDC);
		2395
		2396	rinfo->save_regs[29] = INREG(SURFACE_CNTL);
		2397	rinfo->save_regs[30] = INREG(MC_FB_LOCATION);
		2398	rinfo->save_regs[31] = INREG(DISPLAY_BASE_ADDR);
		2399	rinfo->save_regs[32] = INREG(MC_AGP_LOCATION);
		2400	rinfo->save_regs[33] = INREG(CRTC2_DISPLAY_BASE_ADDR);
		2401	}
		2402
		2403	static void radeon_pm_restore_regs(struct radeonfb_info *rinfo)
		2404	{
		2405	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8] & 0xFFFFFFFE); /* First */
		2406
		2407	OUTPLL(PLL_PWRMGT_CNTL, rinfo->save_regs[0]);
		2408	OUTPLL(CLK_PWRMGT_CNTL, rinfo->save_regs[1]);
		2409	OUTPLL(MCLK_CNTL, rinfo->save_regs[2]);
		2410	OUTPLL(SCLK_CNTL, rinfo->save_regs[3]);
		2411	OUTPLL(CLK_PIN_CNTL, rinfo->save_regs[4]);
		2412	OUTPLL(VCLK_ECP_CNTL, rinfo->save_regs[5]);
		2413	OUTPLL(PIXCLKS_CNTL, rinfo->save_regs[6]);
		2414	OUTPLL(MCLK_MISC, rinfo->save_regs[7]);
		2415
		2416	OUTREG(DISP_MISC_CNTL, rinfo->save_regs[9]);
		2417	OUTREG(DISP_PWR_MAN, rinfo->save_regs[10]);
		2418	OUTREG(LVDS_GEN_CNTL, rinfo->save_regs[11]);
		2419	OUTREG(LVDS_PLL_CNTL,rinfo->save_regs[12]);
		2420	OUTREG(TV_DAC_CNTL, rinfo->save_regs[13]);
		2421	OUTREG(BUS_CNTL1, rinfo->save_regs[14]);
		2422	OUTREG(CRTC_OFFSET_CNTL, rinfo->save_regs[15]);
		2423	OUTREG(AGP_CNTL, rinfo->save_regs[16]);
		2424	OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[17]);
		2425	OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[18]);
		2426
		2427	// wait VBL before that one ?
		2428	OUTPLL(P2PLL_CNTL, rinfo->save_regs[8]);
		2429
		2430	OUTREG(GPIOPAD_A, rinfo->save_regs[19]);
		2431	OUTREG(GPIOPAD_EN, rinfo->save_regs[20]);
		2432	OUTREG(GPIOPAD_MASK, rinfo->save_regs[21]);
		2433	OUTREG(ZV_LCDPAD_A, rinfo->save_regs[22]);
		2434	OUTREG(ZV_LCDPAD_EN, rinfo->save_regs[23]);
		2435	OUTREG(ZV_LCDPAD_MASK, rinfo->save_regs[24]);
		2436	OUTREG(GPIO_VGA_DDC, rinfo->save_regs[25]);
		2437	OUTREG(GPIO_DVI_DDC, rinfo->save_regs[26]);
		2438	OUTREG(GPIO_MONID, rinfo->save_regs[27]);
		2439	OUTREG(GPIO_CRT2_DDC, rinfo->save_regs[28]);
		2440	}
		2441
		2442	static void radeon_pm_disable_iopad(struct radeonfb_info *rinfo)
		2443	{
		2444	OUTREG(GPIOPAD_MASK, 0x0001ffff);
		2445	OUTREG(GPIOPAD_EN, 0x00000400);
		2446	OUTREG(GPIOPAD_A, 0x00000000);
		2447	OUTREG(ZV_LCDPAD_MASK, 0x00000000);
		2448	OUTREG(ZV_LCDPAD_EN, 0x00000000);
		2449	OUTREG(ZV_LCDPAD_A, 0x00000000);
		2450	OUTREG(GPIO_VGA_DDC, 0x00030000);
		2451	OUTREG(GPIO_DVI_DDC, 0x00000000);
		2452	OUTREG(GPIO_MONID, 0x00030000);
		2453	OUTREG(GPIO_CRT2_DDC, 0x00000000);
		2454	}
		2455
		2456	static void radeon_pm_program_v2clk(struct radeonfb_info *rinfo)
		2457	{
		2458	//
		2459	// u32 reg;
		2460	//
		2461	// OUTPLL(P2PLL_REF_DIV, 0x0c);
		2462	//
		2463	// .../... figure out what macos does here
		2464	}
		2465
		2466	static void radeon_pm_low_current(struct radeonfb_info *rinfo)
		2467	{
		2468	u32 reg;
		2469
		2470	reg = INREG(BUS_CNTL1);
		2471	reg &= ~BUS_CNTL1_MOBILE_PLATFORM_SEL_MASK;
		2472	reg \|= BUS_CNTL1_AGPCLK_VALID \| (1<<BUS_CNTL1_MOBILE_PLATFORM_SEL_SHIFT);
		2473	OUTREG(BUS_CNTL1, reg);
		2474
		2475	reg = INPLL(PLL_PWRMGT_CNTL);
		2476	reg \|= PLL_PWRMGT_CNTL_SPLL_TURNOFF \| PLL_PWRMGT_CNTL_PPLL_TURNOFF \|
		2477	PLL_PWRMGT_CNTL_P2PLL_TURNOFF \| PLL_PWRMGT_CNTL_TVPLL_TURNOFF;
		2478	reg &= ~PLL_PWRMGT_CNTL_SU_MCLK_USE_BCLK;
		2479	reg &= ~PLL_PWRMGT_CNTL_MOBILE_SU;
		2480	OUTPLL(PLL_PWRMGT_CNTL, reg);
		2481
		2482	// reg = INPLL(TV_PLL_CNTL1);
		2483	// reg \|= TV_PLL_CNTL1__TVPLL_RESET \| TV_PLL_CNTL1__TVPLL_SLEEP;
		2484	// OUTPLL(TV_PLL_CNTL1, reg);
		2485
		2486	reg = INREG(TV_DAC_CNTL);
		2487	reg &= ~(TV_DAC_CNTL_BGADJ_MASK \|TV_DAC_CNTL_DACADJ_MASK);
		2488	reg \|=TV_DAC_CNTL_BGSLEEP \| TV_DAC_CNTL_RDACPD \| TV_DAC_CNTL_GDACPD \|
		2489	TV_DAC_CNTL_BDACPD \|
		2490	(8<<TV_DAC_CNTL_BGADJ__SHIFT) \| (8<<TV_DAC_CNTL_DACADJ__SHIFT);
		2491	OUTREG(TV_DAC_CNTL, reg);
		2492
		2493	reg = INREG(TMDS_TRANSMITTER_CNTL);
		2494	reg &= ~(TMDS_PLL_EN \|TMDS_PLLRST);
		2495	OUTREG(TMDS_TRANSMITTER_CNTL, reg);
		2496
		2497	// lvds_pll_cntl = regr32(g, LVDS_PLL_CNTL);
		2498	// lvds_pll_cntl &= ~LVDS_PLL_CNTL__LVDS_PLL_EN;
		2499	// lvds_pll_cntl \|= LVDS_PLL_CNTL__LVDS_PLL_RESET;
		2500	// regw32(g, LVDS_PLL_CNTL, lvds_pll_cntl);
		2501
		2502	reg = INREG(DAC_CNTL);
		2503	reg &= ~DAC_CMP_EN;
		2504	OUTREG(DAC_CNTL, reg);
		2505
		2506	reg = INREG(DAC_CNTL2);
		2507	reg &= ~DAC2_CMP_EN;
		2508	OUTREG(DAC_CNTL2, reg);
		2509
		2510	reg = INREG(TV_DAC_CNTL);
		2511	reg &= ~TV_DAC_CNTL_DETECT;
		2512	OUTREG(TV_DAC_CNTL, reg);
		2513	}
		2514
		2515	static void radeon_pm_setup_for_suspend(struct radeonfb_info *rinfo)
		2516	{
		2517	/* This code is disabled. It does what is in the pm_init
		2518	* function of the MacOS driver code ATI sent me. However,
		2519	* it doesn't fix my sleep problem, and is causing other issues
		2520	* on wakeup (bascially the machine dying when switching consoles
		2521	* I haven't had time to investigate this yet
		2522	*/
		2523	#if 0
		2524	u32 disp_misc_cntl;
		2525	u32 disp_pwr_man;
		2526	u32 temp;
		2527
		2528	// set SPLL, MPLL, PPLL, P2PLL, TVPLL, SCLK, MCLK, PCLK, P2CLK,
		2529	// TCLK and TEST_MODE to 0
		2530	temp = INPLL(CLK_PWRMGT_CNTL);
		2531	OUTPLL(CLK_PWRMGT_CNTL , temp & ~0xc00002ff);
		2532
		2533	// Turn on Power Management
		2534	temp = INPLL(CLK_PWRMGT_CNTL);
		2535	OUTPLL(CLK_PWRMGT_CNTL , temp \| 0x00000400);
		2536
		2537	// Turn off display clock if using mobile chips
		2538	temp = INPLL(CLK_PWRMGT_CNTL);
		2539	OUTREG(CLK_PWRMGT_CNTL , temp \| 0x00100000);
		2540
		2541	// Force PIXCLK_ALWAYS_ON and PIXCLK_DAC_ALWAYS_ON
		2542	temp = INPLL(VCLK_ECP_CNTL);
		2543	OUTPLL(VCLK_ECP_CNTL, temp & ~0x000000c0);
		2544
		2545	// Force ECP_FORCE_ON to 1
		2546	temp = INPLL(VCLK_ECP_CNTL);
		2547	OUTPLL(VCLK_ECP_CNTL, temp \| 0x00040000);
		2548
		2549	// Force PIXCLK_BLEND_ALWAYS_ON and PIXCLK_GV_ALWAYS_ON
		2550	temp = INPLL(PIXCLKS_CNTL);
		2551	OUTPLL(PIXCLKS_CNTL, temp & ~0x00001800);
		2552
		2553	// Forcing SCLK_CNTL to ON
		2554	OUTPLL(SCLK_CNTL, (INPLL(SCLK_CNTL)& 0x00000007) \| 0xffff8000 );
		2555
		2556	// Set PM control over XTALIN pad
		2557	temp = INPLL(CLK_PIN_CNTL);
		2558	OUTPLL(CLK_PIN_CNTL, temp \| 0x00080000);
		2559
		2560	// Force MCLK and YCLK and MC as dynamic
		2561	temp = INPLL(MCLK_CNTL);
		2562	OUTPLL(MCLK_CNTL, temp & 0xffeaffff);
		2563
		2564	// PLL_TURNOFF
		2565	temp = INPLL(PLL_PWRMGT_CNTL);
		2566	OUTPLL(PLL_PWRMGT_CNTL, temp \| 0x0000001f);
		2567
		2568	// set MOBILE_SU to 1 if M6 or DDR64 is detected
		2569	temp = INPLL(PLL_PWRMGT_CNTL);
		2570	OUTPLL(PLL_PWRMGT_CNTL, temp \| 0x00010000);
		2571
		2572	// select PM access mode (PM_MODE_SEL) (use ACPI mode)
		2573	// temp = INPLL(PLL_PWRMGT_CNTL);
		2574	// OUTPLL(PLL_PWRMGT_CNTL, temp \| 0x00002000);
		2575	temp = INPLL(PLL_PWRMGT_CNTL);
		2576	OUTPLL(PLL_PWRMGT_CNTL, temp & ~0x00002000);
		2577
		2578	// set DISP_MISC_CNTL register
		2579	disp_misc_cntl = INREG(DISP_MISC_CNTL);
		2580	disp_misc_cntl &= ~( DISP_MISC_CNTL_SOFT_RESET_GRPH_PP \|
		2581	DISP_MISC_CNTL_SOFT_RESET_SUBPIC_PP \|
		2582	DISP_MISC_CNTL_SOFT_RESET_OV0_PP \|
		2583	DISP_MISC_CNTL_SOFT_RESET_GRPH_SCLK \|
		2584	DISP_MISC_CNTL_SOFT_RESET_SUBPIC_SCLK \|
		2585	DISP_MISC_CNTL_SOFT_RESET_OV0_SCLK \|
		2586	DISP_MISC_CNTL_SOFT_RESET_GRPH2_PP \|
		2587	DISP_MISC_CNTL_SOFT_RESET_GRPH2_SCLK \|
		2588	DISP_MISC_CNTL_SOFT_RESET_LVDS \|
		2589	DISP_MISC_CNTL_SOFT_RESET_TMDS \|
		2590	DISP_MISC_CNTL_SOFT_RESET_DIG_TMDS \|
		2591	DISP_MISC_CNTL_SOFT_RESET_TV);
		2592	OUTREG(DISP_MISC_CNTL, disp_misc_cntl);
		2593
		2594	// set DISP_PWR_MAN register
		2595	disp_pwr_man = INREG(DISP_PWR_MAN);
		2596	// clau - 9.29.2000 - changes made to bit23:18 to set to 1 as requested by George
		2597	disp_pwr_man \|= (DISP_PWR_MAN_DIG_TMDS_ENABLE_RST \|
		2598	DISP_PWR_MAN_TV_ENABLE_RST \|
		2599	// DISP_PWR_MAN_AUTO_PWRUP_EN \|
		2600	DISP_PWR_MAN_DISP_D3_GRPH_RST \|
		2601	DISP_PWR_MAN_DISP_D3_SUBPIC_RST \|
		2602	DISP_PWR_MAN_DISP_D3_OV0_RST \|
		2603	DISP_PWR_MAN_DISP_D1D2_GRPH_RST \|
		2604	DISP_PWR_MAN_DISP_D1D2_SUBPIC_RST \|
		2605	DISP_PWR_MAN_DISP_D1D2_OV0_RST);
		2606	disp_pwr_man &= ~(DISP_PWR_MAN_DISP_PWR_MAN_D3_CRTC_EN \|
		2607	DISP_PWR_MAN_DISP2_PWR_MAN_D3_CRTC2_EN\|
		2608	DISP_PWR_MAN_DISP_D3_RST \|
		2609	DISP_PWR_MAN_DISP_D3_REG_RST);
		2610	OUTREG(DISP_PWR_MAN, disp_pwr_man);
		2611
		2612	// clau - 10.24.2000
		2613	// - add in setting for BUS_CNTL1 b27:26 = 0x01 and b31 = 0x1
		2614	// - add in setting for AGP_CNTL b7:0 = 0x20
		2615	// - add in setting for DVI_DDC_DATA_OUT_EN b17:16 = 0x0
		2616
		2617	// the following settings (two lines) are applied at a later part of this function, only on mobile platform
		2618	// requres -mobile flag
		2619	OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1) & 0xf3ffffff) \| 0x04000000);
		2620	OUTREG(BUS_CNTL1, INREG(BUS_CNTL1) \| 0x80000000);
		2621	OUTREG(AGP_CNTL, (INREG(AGP_CNTL) & 0xffffff00) \| 0x20);
		2622	OUTREG(GPIO_DVI_DDC, INREG(GPIO_DVI_DDC) & 0xfffcffff);
		2623
		2624	// yulee - 12.12.2000
		2625	// A12 only
		2626	// EN_MCLK_TRISTATE_IN_SUSPEND@MCLK_MISC = 1
		2627	// ACCESS_REGS_IN_SUSPEND@CLK_PIN_CNTL = 0
		2628	// only on mobile platform
		2629	OUTPLL(MCLK_MISC, INPLL(MCLK_MISC) \| 0x00040000 );
		2630
		2631	// yulee -12.12.2000
		2632	// AGPCLK_VALID@BUS_CNTL1 = 1
		2633	// MOBILE_PLATFORM_SEL@BUS_CNTL1 = 01
		2634	// CRTC_STEREO_SYNC_OUT_EN@CRTC_OFFSET_CNTL = 0
		2635	// CG_CLK_TO_OUTPIN@CLK_PIN_CNTL = 0
		2636	// only on mobile platform
		2637	OUTPLL(CLK_PIN_CNTL, INPLL(CLK_PIN_CNTL ) & 0xFFFFF7FF );
		2638	OUTREG(BUS_CNTL1, (INREG(BUS_CNTL1 ) & 0xF3FFFFFF) \| 0x84000000 );
		2639	OUTREG(CRTC_OFFSET_CNTL, INREG(CRTC_OFFSET_CNTL ) & 0xFFEFFFFF );
		2640
		2641	mdelay(100);
		2642	#endif
		2643
		2644	/* Disable CRTCs */
		2645	OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) \| CRTC_DISP_REQ_EN_B);
		2646	OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) \| CRTC2_DISP_REQ_EN_B);
		2647	(void)INREG(CRTC2_GEN_CNTL);
		2648	mdelay(17);
		2649	}
		2650
		2651	static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
		2652	{
		2653	u16 pwr_cmd;
		2654
		2655	if (!rinfo->pm_reg)
		2656	return;
		2657
		2658	/* Set the chip into appropriate suspend mode (we use D2,
		2659	* D3 would require a compete re-initialization of the chip,
		2660	* including PCI config registers, clocks, AGP conf, ...)
		2661	*/
		2662	if (suspend) {
		2663	/* According to ATI, we should program V2CLK here, I have
		2664	* to verify what's up exactly
		2665	*/
		2666	/* Save some registers */
		2667	radeon_pm_save_regs(rinfo);
		2668
		2669	/* Check that on M7 too, might work might not. M7 may also
		2670	* need explicit enabling of PM
		2671	*/
		2672	if (rinfo->arch == RADEON_M6) {
		2673	/* Program V2CLK */
		2674	radeon_pm_program_v2clk(rinfo);
		2675
		2676	/* Disable IO PADs */
		2677	radeon_pm_disable_iopad(rinfo);
		2678
		2679	/* Set low current */
		2680	radeon_pm_low_current(rinfo);
		2681
		2682	/* Prepare chip for power management */
		2683	radeon_pm_setup_for_suspend(rinfo);
		2684
		2685	/* Reset the MDLL */
		2686	OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) \| MCKOA_RESET);
		2687	(void)INPLL(MDLL_RDCKA);
		2688	OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
		2689	(void)INPLL(MDLL_RDCKA);
		2690	}
		2691
		2692	/* Switch PCI power managment to D2. */
		2693	for (;;) {
		2694	pci_read_config_word(
		2695	rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
		2696	&pwr_cmd);
		2697	if (pwr_cmd & 2)
		2698	break;
		2699	pci_write_config_word(
		2700	rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
		2701	(pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) \| 2);
		2702	mdelay(500);
		2703	}
		2704	} else {
		2705	/* Switch back PCI powermanagment to D0 */
		2706	mdelay(200);
		2707	pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
		2708	mdelay(500);
		2709
		2710	dbg_clk = INPLL(1);
		2711
		2712	/* Do we need that on M7 ? */
		2713	if (rinfo->arch == RADEON_M6) {
		2714	/* Restore the MDLL */
		2715	OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
		2716	(void)INPLL(MDLL_CKO);
		2717	}
		2718
		2719	/* Restore some registers */
		2720	radeon_pm_restore_regs(rinfo);
		2721	}
		2722	}
		2723
		2724	/*
		2725	* Save the contents of the framebuffer when we go to sleep,
		2726	* and restore it when we wake up again.
		2727	*/
		2728
		2729	int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
		2730	{
		2731	struct radeonfb_info *rinfo;
		2732
		2733	for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
		2734	struct fb_fix_screeninfo fix;
		2735	int nb;
		2736	struct display *disp;
		2737
		2738	disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
		2739
		2740	switch (rinfo->arch) {
		2741	case RADEON_M6:
		2742	case RADEON_M7:
		2743	case RADEON_M9:
		2744	break;
		2745	default:
		2746	return PBOOK_SLEEP_REFUSE;
		2747	}
		2748
		2749	radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
		2750	nb = fb_display[fg_console].var.yres * fix.line_length;
		2751
		2752	switch (when) {
		2753	case PBOOK_SLEEP_NOW:
		2754	acquire_console_sem();
		2755	disp->dispsw = &fbcon_dummy;
		2756
		2757	if (!noaccel) {
		2758	/* Make sure engine is reset */
		2759	radeon_engine_reset();
		2760	radeon_engine_idle();
		2761	}
		2762
		2763	/* Blank display and LCD */
		2764	radeonfb_blank(VESA_POWERDOWN+1,
		2765	(struct fb_info *)rinfo);
		2766
		2767	/* Sleep */
		2768	rinfo->asleep = 1;
		2769	radeon_set_suspend(rinfo, 1);
		2770	release_console_sem();
		2771
		2772	break;
		2773	case PBOOK_WAKE:
		2774	acquire_console_sem();
		2775	/* Wakeup */
		2776	radeon_set_suspend(rinfo, 0);
		2777
		2778	if (!noaccel)
		2779	radeon_engine_init(rinfo);
		2780	rinfo->asleep = 0;
		2781	radeon_set_dispsw(rinfo, disp);
		2782	radeon_load_video_mode(rinfo, &disp->var);
		2783	do_install_cmap(rinfo->currcon < 0 ? 0 : rinfo->currcon,
		2784	(struct fb_info *)rinfo);
		2785
		2786	radeonfb_blank(0, (struct fb_info *)rinfo);
		2787	release_console_sem();
		2788	printk("CLK_PIN_CNTL on wakeup was: %08x\n", dbg_clk);
		2789	break;
		2790	}
		2791	}
		2792
		2793	return PBOOK_SLEEP_OK;
		2794	}
		2795
		2796	#endif /* CONFIG_PMAC_PBOOK */
		2797
		2798	static int radeonfb_pci_register (struct pci_dev *pdev,
		2799	const struct pci_device_id *ent)
		2800	{
		2801	struct radeonfb_info *rinfo;
		2802	struct radeon_chip_info *rci = &radeon_chip_info[ent->driver_data];
		2803	u32 tmp;
		2804
		2805	RTRACE("radeonfb_pci_register BEGIN\n");
		2806
		2807	/* Enable device in PCI config */
		2808	if (pci_enable_device(pdev) != 0) {
		2809	printk(KERN_ERR "radeonfb: Cannot enable PCI device\n");
		2810	return -ENODEV;
		2811	}
		2812
		2813	rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
		2814	if (!rinfo) {
		2815	printk ("radeonfb: could not allocate memory\n");
		2816	return -ENODEV;
		2817	}
		2818
		2819	memset (rinfo, 0, sizeof (struct radeonfb_info));
		2820	//info = &rinfo->info;
		2821	rinfo->pdev = pdev;
		2822	strcpy(rinfo->name, rci->name);
		2823	rinfo->arch = rci->arch;
		2824
		2825	/* Set base addrs */
		2826	rinfo->fb_base_phys = pci_resource_start (pdev, 0);
		2827	rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
		2828
		2829	/* request the mem regions */
		2830	if (!request_mem_region (rinfo->fb_base_phys,
		2831	pci_resource_len(pdev, 0), "radeonfb")) {
		2832	printk ("radeonfb: cannot reserve FB region\n");
		2833	kfree (rinfo);
		2834	return -ENODEV;
		2835	}
		2836
		2837	if (!request_mem_region (rinfo->mmio_base_phys,
		2838	pci_resource_len(pdev, 2), "radeonfb")) {
		2839	printk ("radeonfb: cannot reserve MMIO region\n");
		2840	release_mem_region (rinfo->fb_base_phys,
		2841	pci_resource_len(pdev, 0));
		2842	kfree (rinfo);
		2843	return -ENODEV;
		2844	}
		2845
		2846	/* map the regions */
		2847	rinfo->mmio_base = (unsigned long) ioremap (rinfo->mmio_base_phys, RADEON_REGSIZE);
		2848	if (!rinfo->mmio_base) {
		2849	printk ("radeonfb: cannot map MMIO\n");
		2850	release_mem_region (rinfo->mmio_base_phys,
		2851	pci_resource_len(pdev, 2));
		2852	release_mem_region (rinfo->fb_base_phys,
		2853	pci_resource_len(pdev, 0));
		2854	kfree (rinfo);
		2855	return -ENODEV;
		2856	}
		2857
		2858	rinfo->chipset = pdev->device;
		2859
		2860	switch (rinfo->arch) {
		2861	case RADEON_R100:
		2862	rinfo->hasCRTC2 = 0;
		2863	break;
		2864	default:
		2865	/* all the rest have it */
		2866	rinfo->hasCRTC2 = 1;
		2867	break;
		2868	}
		2869	#if 0
		2870	if (rinfo->arch == RADEON_M7) {
		2871	/*
		2872	* Noticed some errors in accel with M7, will have to work these out...
		2873	*/
		2874	noaccel = 1;
		2875	}
		2876	#endif
		2877	if (mirror)
		2878	printk("radeonfb: mirroring display to CRT\n");
		2879
		2880	/* framebuffer size */
		2881	tmp = INREG(CONFIG_MEMSIZE);
		2882
		2883	/* mem size is bits [28:0], mask off the rest */
		2884	rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
		2885
		2886	/* ram type */
		2887	tmp = INREG(MEM_SDRAM_MODE_REG);
		2888	switch ((MEM_CFG_TYPE & tmp) >> 30) {
		2889	case 0:
		2890	/* SDR SGRAM (2:1) */
		2891	strcpy(rinfo->ram_type, "SDR SGRAM");
		2892	rinfo->ram.ml = 4;
		2893	rinfo->ram.mb = 4;
		2894	rinfo->ram.trcd = 1;
		2895	rinfo->ram.trp = 2;
		2896	rinfo->ram.twr = 1;
		2897	rinfo->ram.cl = 2;
		2898	rinfo->ram.loop_latency = 16;
		2899	rinfo->ram.rloop = 16;
		2900
		2901	break;
		2902	case 1:
		2903	/* DDR SGRAM */
		2904	strcpy(rinfo->ram_type, "DDR SGRAM");
		2905	rinfo->ram.ml = 4;
		2906	rinfo->ram.mb = 4;
		2907	rinfo->ram.trcd = 3;
		2908	rinfo->ram.trp = 3;
		2909	rinfo->ram.twr = 2;
		2910	rinfo->ram.cl = 3;
		2911	rinfo->ram.tr2w = 1;
		2912	rinfo->ram.loop_latency = 16;
		2913	rinfo->ram.rloop = 16;
		2914
		2915	break;
		2916	default:
		2917	/* 64-bit SDR SGRAM */
		2918	strcpy(rinfo->ram_type, "SDR SGRAM 64");
		2919	rinfo->ram.ml = 4;
		2920	rinfo->ram.mb = 8;
		2921	rinfo->ram.trcd = 3;
		2922	rinfo->ram.trp = 3;
		2923	rinfo->ram.twr = 1;
		2924	rinfo->ram.cl = 3;
		2925	rinfo->ram.tr2w = 1;
		2926	rinfo->ram.loop_latency = 17;
		2927	rinfo->ram.rloop = 17;
		2928
		2929	break;
		2930	}
		2931
		2932	rinfo->bios_seg = radeon_find_rom(rinfo);
		2933	radeon_get_pllinfo(rinfo, rinfo->bios_seg);
		2934
		2935	/*
		2936	* Hack to get around some busted production M6's
		2937	* reporting no ram
		2938	*/
		2939	if (rinfo->video_ram == 0) {
		2940	switch (pdev->device) {
		2941	case PCI_DEVICE_ID_ATI_RADEON_LY:
		2942	case PCI_DEVICE_ID_ATI_RADEON_LZ:
		2943	rinfo->video_ram = 8192 * 1024;
		2944	break;
		2945	default:
		2946	break;
		2947	}
		2948	}
		2949
		2950
		2951	RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
		2952
		2953	#if !defined(__powerpc__)
		2954	radeon_get_moninfo(rinfo);
		2955	#else
		2956	switch (pdev->device) {
		2957	case PCI_DEVICE_ID_ATI_RADEON_LW:
		2958	case PCI_DEVICE_ID_ATI_RADEON_LX:
		2959	case PCI_DEVICE_ID_ATI_RADEON_LY:
		2960	case PCI_DEVICE_ID_ATI_RADEON_LZ:
		2961	rinfo->dviDisp_type = MT_LCD;
		2962	break;
		2963	default:
		2964	radeon_get_moninfo(rinfo);
		2965	break;
		2966	}
		2967	#endif
		2968
		2969	radeon_get_EDID(rinfo);
		2970
		2971	if ((rinfo->dviDisp_type == MT_DFP) \|\| (rinfo->dviDisp_type == MT_LCD) \|\|
		2972	(rinfo->crtDisp_type == MT_DFP)) {
		2973	if (!radeon_get_dfpinfo(rinfo)) {
		2974	iounmap ((void*)rinfo->mmio_base);
		2975	release_mem_region (rinfo->mmio_base_phys,
		2976	pci_resource_len(pdev, 2));
		2977	release_mem_region (rinfo->fb_base_phys,
		2978	pci_resource_len(pdev, 0));
		2979	kfree (rinfo);
		2980	return -ENODEV;
		2981	}
		2982	}
		2983
		2984	rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys, rinfo->video_ram);
		2985	if (!rinfo->fb_base) {
		2986	printk ("radeonfb: cannot map FB\n");
		2987	iounmap ((void*)rinfo->mmio_base);
		2988	release_mem_region (rinfo->mmio_base_phys,
		2989	pci_resource_len(pdev, 2));
		2990	release_mem_region (rinfo->fb_base_phys,
		2991	pci_resource_len(pdev, 0));
		2992	kfree (rinfo);
		2993	return -ENODEV;
		2994	}
		2995
		2996	/* I SHOULD FIX THAT CRAP ! I should probably mimmic XFree DRI
		2997	* driver setup here.
		2998	*
		2999	* On PPC, OF based cards setup the internal memory
		3000	* mapping in strange ways. We change it so that the
		3001	* framebuffer is mapped at 0 and given half of the card's
		3002	* address space (2Gb). AGP is mapped high (0xe0000000) and
		3003	* can use up to 512Mb. Once DRI is fully implemented, we
		3004	* will have to setup the PCI remapper to remap the agp_special_page
		3005	* memory page somewhere between those regions so that the card
		3006	* use a normal PCI bus master cycle to access the ring read ptr.
		3007	* --BenH.
		3008	*/
		3009	#ifdef CONFIG_ALL_PPC
		3010	if (rinfo->hasCRTC2)
		3011	OUTREG(CRTC2_GEN_CNTL,
		3012	(INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) \| CRTC2_DISP_REQ_EN_B);
		3013	OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) \| CRTC_DISPLAY_DIS);
		3014	OUTREG(MC_FB_LOCATION, 0x7fff0000);
		3015	OUTREG(MC_AGP_LOCATION, 0xffffe000);
		3016	OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
		3017	if (rinfo->hasCRTC2)
		3018	OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
		3019	OUTREG(SRC_OFFSET, 0x00000000);
		3020	OUTREG(DST_OFFSET, 0x00000000);
		3021	mdelay(10);
		3022	OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
		3023	#endif /* CONFIG_ALL_PPC */
		3024
		3025	/* save current mode regs before we switch into the new one
		3026	* so we can restore this upon __exit
		3027	*/
		3028	radeon_save_state (rinfo, &rinfo->init_state);
		3029
		3030	if (!noaccel) {
		3031	/* initialize the engine */
		3032	radeon_engine_init (rinfo);
		3033	}
		3034
		3035	/* set all the vital stuff */
		3036	radeon_set_fbinfo (rinfo);
		3037
		3038	pci_set_drvdata(pdev, rinfo);
		3039	rinfo->next = board_list;
		3040	board_list = rinfo;
		3041
		3042	if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
		3043	printk ("radeonfb: could not register framebuffer\n");
		3044	iounmap ((void*)rinfo->fb_base);
		3045	iounmap ((void*)rinfo->mmio_base);
		3046	release_mem_region (rinfo->mmio_base_phys,
		3047	pci_resource_len(pdev, 2));
		3048	release_mem_region (rinfo->fb_base_phys,
		3049	pci_resource_len(pdev, 0));
		3050	kfree (rinfo);
		3051	return -ENODEV;
		3052	}
		3053
		3054	#ifdef CONFIG_MTRR
		3055	rinfo->mtrr_hdl = nomtrr ? -1 : mtrr_add(rinfo->fb_base_phys,
		3056	rinfo->video_ram,
		3057	MTRR_TYPE_WRCOMB, 1);
		3058	#endif
		3059
		3060	#ifdef CONFIG_PMAC_BACKLIGHT
		3061	if (rinfo->dviDisp_type == MT_LCD)
		3062	register_backlight_controller(&radeon_backlight_controller,
		3063	rinfo, "ati");
		3064	#endif
		3065
		3066	#ifdef CONFIG_PMAC_PBOOK
		3067	if (rinfo->dviDisp_type == MT_LCD) {
		3068	rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
		3069	pmu_register_sleep_notifier(&radeon_sleep_notifier);
		3070	}
		3071	#endif
		3072
		3073	printk ("radeonfb: ATI Radeon %s %s %d MB\n", rinfo->name, rinfo->ram_type,
		3074	(rinfo->video_ram/(1024*1024)));
		3075
		3076	if (rinfo->hasCRTC2) {
		3077	printk("radeonfb: DVI port %s monitor connected\n",
		3078	GET_MON_NAME(rinfo->dviDisp_type));
		3079	printk("radeonfb: CRT port %s monitor connected\n",
		3080	GET_MON_NAME(rinfo->crtDisp_type));
		3081	} else {
		3082	printk("radeonfb: CRT port %s monitor connected\n",
		3083	GET_MON_NAME(rinfo->crtDisp_type));
		3084	}
		3085
		3086	RTRACE("radeonfb_pci_register END\n");
		3087
		3088	return 0;
		3089	}
		3090
		3091
		3092
		3093	static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
		3094	{
		3095	struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
		3096
		3097	if (!rinfo)
		3098	return;
		3099
		3100	/* restore original state
		3101	*
		3102	* Doesn't quite work yet, possibly because of the PPC hacking
		3103	* I do on startup, disable for now. --BenH
		3104	*/
		3105	radeon_write_mode (rinfo, &rinfo->init_state);
		3106
		3107	#ifdef CONFIG_MTRR
		3108	if (rinfo->mtrr_hdl >= 0)
		3109	mtrr_del(rinfo->mtrr_hdl, 0, 0);
		3110	#endif
		3111
		3112	unregister_framebuffer ((struct fb_info *) rinfo);
		3113
		3114	iounmap ((void*)rinfo->mmio_base);
		3115	iounmap ((void*)rinfo->fb_base);
		3116
		3117	release_mem_region (rinfo->mmio_base_phys,
		3118	pci_resource_len(pdev, 2));
		3119	release_mem_region (rinfo->fb_base_phys,
		3120	pci_resource_len(pdev, 0));
		3121
		3122	kfree (rinfo);
		3123	}
		3124
		3125
		3126	static struct pci_driver radeonfb_driver = {
		3127	.name = "radeonfb",
		3128	.id_table = radeonfb_pci_table,
		3129	.probe = radeonfb_pci_register,
		3130	.remove = __devexit_p(radeonfb_pci_unregister),
		3131	};
		3132
		3133
		3134	int __init radeonfb_init (void)
		3135	{
		3136	return pci_module_init (&radeonfb_driver);
		3137	}
		3138
		3139
		3140	void __exit radeonfb_exit (void)
		3141	{
		3142	pci_unregister_driver (&radeonfb_driver);
		3143	}
		3144
		3145
		3146	int __init radeonfb_setup (char *options)
		3147	{
		3148	char *this_opt;
		3149
		3150	if (!options \|\| !*options)
		3151	return 0;
		3152
		3153	while ((this_opt = strsep (&options, ",")) != NULL) {
		3154	if (!*this_opt)
		3155	continue;
		3156	if (!strncmp(this_opt, "noaccel", 7)) {
		3157	noaccel = 1;
		3158	} else if (!strncmp(this_opt, "mirror", 6)) {
		3159	mirror = 1;
		3160	} else if (!strncmp(this_opt, "dfp", 3)) {
		3161	force_dfp = 1;
		3162	} else if (!strncmp(this_opt, "panel_yres:", 11)) {
		3163	panel_yres = simple_strtoul((this_opt+11), NULL, 0);
		3164	} else if (!strncmp(this_opt, "nomtrr", 6)) {
		3165	nomtrr = 1;
		3166	} else
		3167	mode_option = this_opt;
		3168	}
		3169
		3170	return 0;
		3171	}
		3172
		3173	#ifdef MODULE
		3174	module_init(radeonfb_init);
		3175	module_exit(radeonfb_exit);
		3176	#endif
		3177
		3178
		3179	MODULE_AUTHOR("Ani Joshi");
		3180	MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
		3181	MODULE_LICENSE("GPL");

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(root)/shark/branches/xen/drivers/fb/radeonfb.c - Rev 1618