WebSVN - shark - Blame - Rev 1618 - /shark/branches/xen/drivers/fb/riva/fbdev.c

Rev	Author	Line No.	Line
472	giacomo	1	/*
		2	* linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
		3	*
		4	* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
		5	*
		6	* Copyright 1999-2000 Jeff Garzik
		7	*
		8	* Contributors:
		9	*
		10	* Ani Joshi: Lots of debugging and cleanup work, really helped
		11	* get the driver going
		12	*
		13	* Ferenc Bakonyi: Bug fixes, cleanup, modularization
		14	*
		15	* Jindrich Makovicka: Accel code help, hw cursor, mtrr
		16	*
		17	* Paul Richards: Bug fixes, updates
		18	*
		19	* Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
		20	* Includes riva_hw.c from nVidia, see copyright below.
		21	* KGI code provided the basis for state storage, init, and mode switching.
		22	*
		23	* This file is subject to the terms and conditions of the GNU General Public
		24	* License. See the file COPYING in the main directory of this archive
		25	* for more details.
		26	*
		27	* Known bugs and issues:
		28	* restoring text mode fails
		29	* doublescan modes are broken
		30	*/
		31
		32	#include <linuxcomp.h>
		33
		34	#include <linux/config.h>
		35	#include <linux/module.h>
		36	#include <linux/kernel.h>
		37	#include <linux/errno.h>
		38	#include <linux/string.h>
		39	#include <linux/mm.h>
		40	#include <linux/tty.h>
		41	#include <linux/slab.h>
		42	#include <linux/delay.h>
		43	#include <linux/fb.h>
		44	#include <linux/init.h>
		45	#include <linux/pci.h>
		46	#ifdef CONFIG_MTRR
		47	#include <asm/mtrr.h>
		48	#endif
		49
		50	#include "rivafb.h"
		51	#include "nvreg.h"
		52
		53	#ifndef CONFIG_PCI /* sanity check */
		54	#error This driver requires PCI support.
		55	#endif
		56
		57	/* version number of this driver */
		58	#define RIVAFB_VERSION "0.9.5b"
		59
		60	/* ------------------------------------------------------------------------- *
		61	*
		62	* various helpful macros and constants
		63	*
		64	* ------------------------------------------------------------------------- */
		65
477	giacomo	66	#undef RIVAFBDEBUG
472	giacomo	67	#ifdef RIVAFBDEBUG
		68	#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
		69	#else
		70	#define DPRINTK(fmt, args...)
		71	#endif
		72
		73	#ifndef RIVA_NDEBUG
		74	#define assert(expr) \
		75	if(!(expr)) { \
		76	printk( "Assertion failed! %s,%s,%s,line=%d\n",\
		77	#expr,__FILE__,__FUNCTION__,__LINE__); \
		78	BUG(); \
		79	}
		80	#else
		81	#define assert(expr)
		82	#endif
		83
		84	#define PFX "rivafb: "
		85
		86	/* macro that allows you to set overflow bits */
		87	#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
		88	#define SetBit(n) (1<<(n))
		89	#define Set8Bits(value) ((value)&0xff)
		90
		91	/* HW cursor parameters */
		92	#define MAX_CURS 32
		93
		94	/* ------------------------------------------------------------------------- *
		95	*
		96	* prototypes
		97	*
		98	* ------------------------------------------------------------------------- */
		99
		100	static int rivafb_blank(int blank, struct fb_info *info);
		101
		102	/* ------------------------------------------------------------------------- *
		103	*
		104	* card identification
		105	*
		106	* ------------------------------------------------------------------------- */
		107
		108	enum riva_chips {
		109	CH_RIVA_128 = 0,
		110	CH_RIVA_TNT,
		111	CH_RIVA_TNT2,
		112	CH_RIVA_UTNT2,
		113	CH_RIVA_VTNT2,
		114	CH_RIVA_UVTNT2,
		115	CH_RIVA_ITNT2,
		116	CH_GEFORCE_SDR,
		117	CH_GEFORCE_DDR,
		118	CH_QUADRO,
		119	CH_GEFORCE2_MX,
		120	CH_GEFORCE2_MX2,
		121	CH_GEFORCE2_GO,
		122	CH_QUADRO2_MXR,
		123	CH_GEFORCE2_GTS,
		124	CH_GEFORCE2_GTS2,
		125	CH_GEFORCE2_ULTRA,
		126	CH_QUADRO2_PRO,
473	giacomo	127	CH_TEST,
472	giacomo	128	CH_GEFORCE4_MX_460,
		129	CH_GEFORCE4_MX_440,
		130	CH_GEFORCE4_MX_420,
		131	CH_GEFORCE4_440_GO,
		132	CH_GEFORCE4_420_GO,
		133	CH_GEFORCE4_420_GO_M32,
		134	CH_QUADRO4_500XGL,
		135	CH_GEFORCE4_440_GO_M64,
		136	CH_QUADRO4_200,
		137	CH_QUADRO4_550XGL,
		138	CH_QUADRO4_500_GOGL,
		139	CH_IGEFORCE2,
		140	CH_GEFORCE3,
		141	CH_GEFORCE3_1,
		142	CH_GEFORCE3_2,
		143	CH_QUADRO_DDC,
		144	CH_GEFORCE4_TI_4600,
		145	CH_GEFORCE4_TI_4400,
		146	CH_GEFORCE4_TI_4200,
		147	CH_QUADRO4_900XGL,
		148	CH_QUADRO4_750XGL,
		149	CH_QUADRO4_700XGL
		150	};
		151
		152	/* directly indexed by riva_chips enum, above */
		153	static struct riva_chip_info {
		154	const char *name;
		155	unsigned arch_rev;
		156	} riva_chip_info[] __initdata = {
		157	{ "RIVA-128", NV_ARCH_03 },
		158	{ "RIVA-TNT", NV_ARCH_04 },
		159	{ "RIVA-TNT2", NV_ARCH_04 },
		160	{ "RIVA-UTNT2", NV_ARCH_04 },
		161	{ "RIVA-VTNT2", NV_ARCH_04 },
		162	{ "RIVA-UVTNT2", NV_ARCH_04 },
		163	{ "RIVA-ITNT2", NV_ARCH_04 },
		164	{ "GeForce-SDR", NV_ARCH_10 },
		165	{ "GeForce-DDR", NV_ARCH_10 },
		166	{ "Quadro", NV_ARCH_10 },
		167	{ "GeForce2-MX", NV_ARCH_10 },
		168	{ "GeForce2-MX", NV_ARCH_10 },
		169	{ "GeForce2-GO", NV_ARCH_10 },
		170	{ "Quadro2-MXR", NV_ARCH_10 },
		171	{ "GeForce2-GTS", NV_ARCH_10 },
		172	{ "GeForce2-GTS", NV_ARCH_10 },
		173	{ "GeForce2-ULTRA", NV_ARCH_10 },
		174	{ "Quadro2-PRO", NV_ARCH_10 },
473	giacomo	175	{ "TEST",NV_ARCH_20 },
472	giacomo	176	{ "GeForce4-MX-460", NV_ARCH_20 },
		177	{ "GeForce4-MX-440", NV_ARCH_20 },
		178	{ "GeForce4-MX-420", NV_ARCH_20 },
		179	{ "GeForce4-440-GO", NV_ARCH_20 },
		180	{ "GeForce4-420-GO", NV_ARCH_20 },
		181	{ "GeForce4-420-GO-M32", NV_ARCH_20 },
		182	{ "Quadro4-500-XGL", NV_ARCH_20 },
		183	{ "GeForce4-440-GO-M64", NV_ARCH_20 },
		184	{ "Quadro4-200", NV_ARCH_20 },
		185	{ "Quadro4-550-XGL", NV_ARCH_20 },
		186	{ "Quadro4-500-GOGL", NV_ARCH_20 },
		187	{ "GeForce2", NV_ARCH_20 },
		188	{ "GeForce3", NV_ARCH_20 },
		189	{ "GeForce3 Ti 200", NV_ARCH_20 },
		190	{ "GeForce3 Ti 500", NV_ARCH_20 },
		191	{ "Quadro DDC", NV_ARCH_20 },
		192	{ "GeForce4 Ti 4600", NV_ARCH_20 },
		193	{ "GeForce4 Ti 4400", NV_ARCH_20 },
		194	{ "GeForce4 Ti 4200", NV_ARCH_20 },
		195	{ "Quadro4-900-XGL", NV_ARCH_20 },
		196	{ "Quadro4-750-XGL", NV_ARCH_20 },
		197	{ "Quadro4-700-XGL", NV_ARCH_20 }
		198	};
		199
		200	static struct pci_device_id rivafb_pci_tbl[] = {
		201	{ PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
		202	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
		203	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
		204	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
		205	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
		206	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
		207	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
		208	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
		209	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
		210	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
		211	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
		212	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
		213	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
		214	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
		215	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
		216	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR },
		217	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
		218	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR },
		219	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
		220	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO },
		221	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
		222	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
		223	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
		224	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
		225	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
		226	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
		227	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
		228	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
		229	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
		230	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
		231	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
		232	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
		233	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
		234	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
		235	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
		236	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
		237	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
		238	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
		239	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
		240	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
		241	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
		242	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
473	giacomo	243	{ PCI_VENDOR_ID_NVIDIA, 0x0182,
		244	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_TEST },
472	giacomo	245	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
		246	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
		247	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
		248	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
		249	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
		250	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
		251	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
		252	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
		253	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
		254	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
		255	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
		256	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
		257	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
		258	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
		259	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
		260	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
		261	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
		262	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
		263	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
		264	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
		265	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
		266	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
		267	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
		268	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
		269	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
		270	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
		271	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
		272	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
		273	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
		274	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
		275	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
		276	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
		277	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
		278	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
		279	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
		280	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
		281	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
		282	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
		283	{ 0, } /* terminate list */
		284	};
		285	MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
		286
		287	/* ------------------------------------------------------------------------- *
		288	*
		289	* global variables
		290	*
		291	* ------------------------------------------------------------------------- */
		292
		293	/* command line data, set in rivafb_setup() */
		294	static u32 pseudo_palette[17];
		295	static int flatpanel __initdata = -1; /* Autodetect later */
		296	static int forceCRTC __initdata = -1;
		297	#ifdef CONFIG_MTRR
		298	static int nomtrr __initdata = 0;
		299	#endif
		300
		301	#ifndef MODULE
		302	static char *mode_option __initdata = NULL;
		303	#endif
		304
		305	static struct fb_fix_screeninfo rivafb_fix = {
		306	.id = "nVidia",
		307	.type = FB_TYPE_PACKED_PIXELS,
		308	.xpanstep = 1,
		309	.ypanstep = 1,
		310	};
		311
		312	static struct fb_var_screeninfo rivafb_default_var = {
		313	.xres = 640,
		314	.yres = 480,
		315	.xres_virtual = 640,
		316	.yres_virtual = 480,
		317	.bits_per_pixel = 8,
		318	.red = {0, 8, 0},
		319	.green = {0, 8, 0},
		320	.blue = {0, 8, 0},
		321	.transp = {0, 0, 0},
		322	.activate = FB_ACTIVATE_NOW,
		323	.height = -1,
		324	.width = -1,
		325	.accel_flags = FB_ACCELF_TEXT,
		326	.pixclock = 39721,
		327	.left_margin = 40,
		328	.right_margin = 24,
		329	.upper_margin = 32,
		330	.lower_margin = 11,
		331	.hsync_len = 96,
		332	.vsync_len = 2,
		333	.vmode = FB_VMODE_NONINTERLACED
		334	};
		335
		336	/* from GGI */
		337	static const struct riva_regs reg_template = {
		338	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
		339	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
		340	0x41, 0x01, 0x0F, 0x00, 0x00},
		341	{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
		342	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
		343	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
		344	0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		345	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
		346	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		347	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
		348	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		349	0x00, /* 0x40 */
		350	},
		351	{0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
		352	0xFF},
		353	{0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
		354	0xEB /* MISC */
		355	};
		356
		357	/* ------------------------------------------------------------------------- *
		358	*
		359	* MMIO access macros
		360	*
		361	* ------------------------------------------------------------------------- */
		362
		363	static inline void CRTCout(struct riva_par *par, unsigned char index,
		364	unsigned char val)
		365	{
		366	VGA_WR08(par->riva.PCIO, 0x3d4, index);
		367	VGA_WR08(par->riva.PCIO, 0x3d5, val);
		368	}
		369
		370	static inline unsigned char CRTCin(struct riva_par *par,
		371	unsigned char index)
		372	{
		373	VGA_WR08(par->riva.PCIO, 0x3d4, index);
		374	return (VGA_RD08(par->riva.PCIO, 0x3d5));
		375	}
		376
		377	static inline void GRAout(struct riva_par *par, unsigned char index,
		378	unsigned char val)
		379	{
		380	VGA_WR08(par->riva.PVIO, 0x3ce, index);
		381	VGA_WR08(par->riva.PVIO, 0x3cf, val);
		382	}
		383
		384	static inline unsigned char GRAin(struct riva_par *par,
		385	unsigned char index)
		386	{
		387	VGA_WR08(par->riva.PVIO, 0x3ce, index);
		388	return (VGA_RD08(par->riva.PVIO, 0x3cf));
		389	}
		390
		391	static inline void SEQout(struct riva_par *par, unsigned char index,
		392	unsigned char val)
		393	{
		394	VGA_WR08(par->riva.PVIO, 0x3c4, index);
		395	VGA_WR08(par->riva.PVIO, 0x3c5, val);
		396	}
		397
		398	static inline unsigned char SEQin(struct riva_par *par,
		399	unsigned char index)
		400	{
		401	VGA_WR08(par->riva.PVIO, 0x3c4, index);
		402	return (VGA_RD08(par->riva.PVIO, 0x3c5));
		403	}
		404
		405	static inline void ATTRout(struct riva_par *par, unsigned char index,
		406	unsigned char val)
		407	{
		408	VGA_WR08(par->riva.PCIO, 0x3c0, index);
		409	VGA_WR08(par->riva.PCIO, 0x3c0, val);
		410	}
		411
		412	static inline unsigned char ATTRin(struct riva_par *par,
		413	unsigned char index)
		414	{
		415	VGA_WR08(par->riva.PCIO, 0x3c0, index);
		416	return (VGA_RD08(par->riva.PCIO, 0x3c1));
		417	}
		418
		419	static inline void MISCout(struct riva_par *par, unsigned char val)
		420	{
		421	VGA_WR08(par->riva.PVIO, 0x3c2, val);
		422	}
		423
		424	static inline unsigned char MISCin(struct riva_par *par)
		425	{
		426	return (VGA_RD08(par->riva.PVIO, 0x3cc));
		427	}
		428
		429	static u8 byte_rev[256] = {
		430	0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
		431	0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
		432	0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
		433	0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
		434	0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
		435	0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
		436	0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
		437	0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
		438	0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
		439	0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
		440	0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
		441	0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
		442	0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
		443	0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
		444	0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
		445	0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
		446	0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
		447	0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
		448	0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
		449	0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
		450	0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
		451	0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
		452	0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
		453	0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
		454	0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
		455	0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
		456	0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
		457	0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
		458	0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
		459	0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
		460	0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
		461	0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
		462	};
		463
		464	static inline void reverse_order(u32 *l)
		465	{
		466	u8 a = (u8 )l;
		467	a = byte_rev[a], a++;
		468	a = byte_rev[a], a++;
		469	a = byte_rev[a], a++;
		470	a = byte_rev[a];
		471	}
		472
		473	/* ------------------------------------------------------------------------- *
		474	*
		475	* cursor stuff
		476	*
		477	* ------------------------------------------------------------------------- */
		478
		479	/**
		480	* rivafb_load_cursor_image - load cursor image to hardware
		481	* @data: address to monochrome bitmap (1 = foreground color, 0 = background)
		482	* @par: pointer to private data
		483	* @w: width of cursor image in pixels
		484	* @h: height of cursor image in scanlines
		485	* @bg: background color (ARGB1555) - alpha bit determines opacity
		486	* @fg: foreground color (ARGB1555)
		487	*
		488	* DESCRIPTiON:
		489	* Loads cursor image based on a monochrome source and mask bitmap. The
		490	* image bits determines the color of the pixel, 0 for background, 1 for
		491	* foreground. Only the affected region (as determined by @w and @h
		492	* parameters) will be updated.
		493	*
		494	* CALLED FROM:
		495	* rivafb_cursor()
		496	*/
		497	static void rivafb_load_cursor_image(struct riva_par par, u8 data,
		498	u8 *mask, u16 bg, u16 fg, u32 w, u32 h)
		499	{
		500	int i, j, k = 0;
		501	u32 b, m, tmp;
		502
		503	for (i = 0; i < h; i++) {
1056	tullio	504
		505	// changed for gcc4 compatibility
		506	//b = ((u32 )data)++;
		507	b = ((u32 )data);
		508	data += sizeof(u32);
		509	//m = ((u32 )mask)++;
		510	m = ((u32 )mask);
		511	mask += sizeof(u32);
		512
472	giacomo	513	reverse_order(&b);
		514
		515	for (j = 0; j < w/2; j++) {
		516	tmp = 0;
		517	#if defined (__BIG_ENDIAN)
		518	if (m & (1 << 31)) {
		519	fg \|= 1 << 15;
		520	bg \|= 1 << 15;
		521	}
		522	tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
		523	b <<= 1;
		524	m <<= 1;
		525
		526	if (m & (1 << 31)) {
		527	fg \|= 1 << 15;
		528	bg \|= 1 << 15;
		529	}
		530	tmp \|= (b & (1 << 31)) ? fg : bg;
		531	b <<= 1;
		532	m <<= 1;
		533	#else
		534	if (m & 1) {
		535	fg \|= 1 << 15;
		536	bg \|= 1 << 15;
		537	}
		538	tmp = (b & 1) ? fg : bg;
		539	b >>= 1;
		540	m >>= 1;
		541
		542	if (m & 1) {
		543	fg \|= 1 << 15;
		544	bg \|= 1 << 15;
		545	}
		546	tmp \|= (b & 1) ? fg << 16 : bg << 16;
		547	b >>= 1;
		548	m >>= 1;
		549	#endif
		550	writel(tmp, par->riva.CURSOR + k++);
		551	}
		552	k += (MAX_CURS - w)/2;
		553	}
		554	}
		555
		556	/* ------------------------------------------------------------------------- *
		557	*
		558	* general utility functions
		559	*
		560	* ------------------------------------------------------------------------- */
		561
		562	/**
		563	* riva_wclut - set CLUT entry
		564	* @chip: pointer to RIVA_HW_INST object
		565	* @regnum: register number
		566	* @red: red component
		567	* @green: green component
		568	* @blue: blue component
		569	*
		570	* DESCRIPTION:
		571	* Sets color register @regnum.
		572	*
		573	* CALLED FROM:
		574	* rivafb_setcolreg()
		575	*/
		576	static void riva_wclut(RIVA_HW_INST *chip,
		577	unsigned char regnum, unsigned char red,
		578	unsigned char green, unsigned char blue)
		579	{
		580	VGA_WR08(chip->PDIO, 0x3c8, regnum);
		581	VGA_WR08(chip->PDIO, 0x3c9, red);
		582	VGA_WR08(chip->PDIO, 0x3c9, green);
		583	VGA_WR08(chip->PDIO, 0x3c9, blue);
		584	}
		585
		586	/**
		587	* riva_rclut - read fromCLUT register
		588	* @chip: pointer to RIVA_HW_INST object
		589	* @regnum: register number
		590	* @red: red component
		591	* @green: green component
		592	* @blue: blue component
		593	*
		594	* DESCRIPTION:
		595	* Reads red, green, and blue from color register @regnum.
		596	*
		597	* CALLED FROM:
		598	* rivafb_setcolreg()
		599	*/
		600	static void riva_rclut(RIVA_HW_INST *chip,
		601	unsigned char regnum, unsigned char *red,
		602	unsigned char green, unsigned char blue)
		603	{
		604
		605	VGA_WR08(chip->PDIO, 0x3c8, regnum);
		606	*red = VGA_RD08(chip->PDIO, 0x3c9);
		607	*green = VGA_RD08(chip->PDIO, 0x3c9);
		608	*blue = VGA_RD08(chip->PDIO, 0x3c9);
		609	}
		610
		611	/**
		612	* riva_save_state - saves current chip state
		613	* @par: pointer to riva_par object containing info for current riva board
		614	* @regs: pointer to riva_regs object
		615	*
		616	* DESCRIPTION:
		617	* Saves current chip state to @regs.
		618	*
		619	* CALLED FROM:
		620	* rivafb_probe()
		621	*/
		622	/* from GGI */
		623	static void riva_save_state(struct riva_par par, struct riva_regs regs)
		624	{
		625	int i;
		626
		627	par->riva.LockUnlock(&par->riva, 0);
		628
		629	par->riva.UnloadStateExt(&par->riva, &regs->ext);
		630
		631	regs->misc_output = MISCin(par);
		632
		633	for (i = 0; i < NUM_CRT_REGS; i++)
		634	regs->crtc[i] = CRTCin(par, i);
		635
		636	for (i = 0; i < NUM_ATC_REGS; i++)
		637	regs->attr[i] = ATTRin(par, i);
		638
		639	for (i = 0; i < NUM_GRC_REGS; i++)
		640	regs->gra[i] = GRAin(par, i);
		641
		642	for (i = 0; i < NUM_SEQ_REGS; i++)
		643	regs->seq[i] = SEQin(par, i);
		644	}
		645
		646	/**
		647	* riva_load_state - loads current chip state
		648	* @par: pointer to riva_par object containing info for current riva board
		649	* @regs: pointer to riva_regs object
		650	*
		651	* DESCRIPTION:
		652	* Loads chip state from @regs.
		653	*
		654	* CALLED FROM:
		655	* riva_load_video_mode()
		656	* rivafb_probe()
		657	* rivafb_remove()
		658	*/
		659	/* from GGI */
		660	static void riva_load_state(struct riva_par par, struct riva_regs regs)
		661	{
		662	RIVA_HW_STATE *state = &regs->ext;
		663	int i;
		664
		665	CRTCout(par, 0x11, 0x00);
		666
		667	par->riva.LockUnlock(&par->riva, 0);
		668
		669	par->riva.LoadStateExt(&par->riva, state);
		670
		671	MISCout(par, regs->misc_output);
		672
		673	for (i = 0; i < NUM_CRT_REGS; i++) {
		674	switch (i) {
		675	case 0x19:
		676	case 0x20 ... 0x40:
		677	break;
		678	default:
		679	CRTCout(par, i, regs->crtc[i]);
		680	}
		681	}
		682
		683	for (i = 0; i < NUM_ATC_REGS; i++)
		684	ATTRout(par, i, regs->attr[i]);
		685
		686	for (i = 0; i < NUM_GRC_REGS; i++)
		687	GRAout(par, i, regs->gra[i]);
		688
		689	for (i = 0; i < NUM_SEQ_REGS; i++)
		690	SEQout(par, i, regs->seq[i]);
		691	}
		692
		693	/**
		694	* riva_load_video_mode - calculate timings
		695	* @info: pointer to fb_info object containing info for current riva board
		696	*
		697	* DESCRIPTION:
		698	* Calculate some timings and then send em off to riva_load_state().
		699	*
		700	* CALLED FROM:
		701	* rivafb_set_par()
		702	*/
		703	static void riva_load_video_mode(struct fb_info *info)
		704	{
		705	int bpp, width, hDisplaySize, hDisplay, hStart,
		706	hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
		707	int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
		708	struct riva_par par = (struct riva_par ) info->par;
		709	struct riva_regs newmode;
		710
		711	/* time to calculate */
		712	rivafb_blank(1, info);
		713
		714	bpp = info->var.bits_per_pixel;
		715	if (bpp == 16 && info->var.green.length == 5)
		716	bpp = 15;
		717	width = info->var.xres_virtual;
		718	hDisplaySize = info->var.xres;
		719	hDisplay = (hDisplaySize / 8) - 1;
		720	hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
		721	hEnd = (hDisplaySize + info->var.right_margin +
		722	info->var.hsync_len) / 8 - 1;
		723	hTotal = (hDisplaySize + info->var.right_margin +
		724	info->var.hsync_len + info->var.left_margin) / 8 - 5;
		725	hBlankStart = hDisplay;
		726	hBlankEnd = hTotal + 4;
		727
		728	height = info->var.yres_virtual;
		729	vDisplay = info->var.yres - 1;
		730	vStart = info->var.yres + info->var.lower_margin - 1;
		731	vEnd = info->var.yres + info->var.lower_margin +
		732	info->var.vsync_len - 1;
		733	vTotal = info->var.yres + info->var.lower_margin +
		734	info->var.vsync_len + info->var.upper_margin + 2;
		735	vBlankStart = vDisplay;
		736	vBlankEnd = vTotal + 1;
		737	dotClock = 1000000000 / info->var.pixclock;
		738
		739	memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
		740
		741	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
		742	vTotal \|= 1;
		743
		744	if (par->FlatPanel) {
		745	vStart = vTotal - 3;
		746	vEnd = vTotal - 2;
		747	vBlankStart = vStart;
		748	hStart = hTotal - 3;
		749	hEnd = hTotal - 2;
		750	hBlankEnd = hTotal + 4;
		751	}
		752
		753	newmode.crtc[0x0] = Set8Bits (hTotal);
		754	newmode.crtc[0x1] = Set8Bits (hDisplay);
		755	newmode.crtc[0x2] = Set8Bits (hBlankStart);
		756	newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) \| SetBit (7);
		757	newmode.crtc[0x4] = Set8Bits (hStart);
		758	newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
		759	\| SetBitField (hEnd, 4: 0, 4:0);
		760	newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
		761	newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
		762	\| SetBitField (vDisplay, 8: 8, 1:1)
		763	\| SetBitField (vStart, 8: 8, 2:2)
		764	\| SetBitField (vBlankStart, 8: 8, 3:3)
		765	\| SetBit (4)
		766	\| SetBitField (vTotal, 9: 9, 5:5)
		767	\| SetBitField (vDisplay, 9: 9, 6:6)
		768	\| SetBitField (vStart, 9: 9, 7:7);
		769	newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
		770	\| SetBit (6);
		771	newmode.crtc[0x10] = Set8Bits (vStart);
		772	newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
		773	\| SetBit (5);
		774	newmode.crtc[0x12] = Set8Bits (vDisplay);
		775	newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
		776	newmode.crtc[0x15] = Set8Bits (vBlankStart);
		777	newmode.crtc[0x16] = Set8Bits (vBlankEnd);
		778
		779	newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
		780	\| SetBitField(vBlankStart,10:10,3:3)
		781	\| SetBitField(vStart,10:10,2:2)
		782	\| SetBitField(vDisplay,10:10,1:1)
		783	\| SetBitField(vTotal,10:10,0:0);
		784	newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
		785	\| SetBitField(hDisplay,8:8,1:1)
		786	\| SetBitField(hBlankStart,8:8,2:2)
		787	\| SetBitField(hStart,8:8,3:3);
		788	newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
		789	\| SetBitField(vDisplay,11:11,2:2)
		790	\| SetBitField(vStart,11:11,4:4)
		791	\| SetBitField(vBlankStart,11:11,6:6);
		792
		793	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
		794	int tmp = (hTotal >> 1) & ~1;
		795	newmode.ext.interlace = Set8Bits(tmp);
		796	newmode.ext.horiz \|= SetBitField(tmp, 8:8,4:4);
		797	} else
		798	newmode.ext.interlace = 0xff; /* interlace off */
		799
		800	if (par->riva.Architecture >= NV_ARCH_10)
		801	par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
		802
		803	if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
		804	newmode.misc_output &= ~0x40;
		805	else
		806	newmode.misc_output \|= 0x40;
		807	if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
		808	newmode.misc_output &= ~0x80;
		809	else
		810	newmode.misc_output \|= 0x80;
		811
		812	par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
		813	hDisplaySize, height, dotClock);
		814
		815	newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
		816	if (par->FlatPanel == 1) {
		817	newmode.ext.pixel \|= (1 << 7);
		818	newmode.ext.scale \|= (1 << 8);
		819	}
		820	if (par->SecondCRTC) {
		821	newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
		822	newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] \| 0x00001000;
		823	newmode.ext.crtcOwner = 3;
		824	newmode.ext.pllsel \|= 0x20000800;
		825	newmode.ext.vpll2 = newmode.ext.vpll;
		826	} else if (par->riva.twoHeads) {
		827	newmode.ext.head = par->riva.PCRTC0[0x00000860/4] \| 0x00001000;
		828	newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
		829	newmode.ext.crtcOwner = 0;
		830	newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
		831	}
		832	if (par->FlatPanel == 1) {
		833	newmode.ext.pixel \|= (1 << 7);
		834	newmode.ext.scale \|= (1 << 8);
		835	}
		836	newmode.ext.cursorConfig = 0x02000100;
		837	par->current_state = newmode;
		838	riva_load_state(par, &par->current_state);
		839	par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
		840	rivafb_blank(0, info);
		841	}
		842
		843	/**
		844	* rivafb_do_maximize -
		845	* @info: pointer to fb_info object containing info for current riva board
		846	* @var:
		847	* @nom:
		848	* @den:
		849	*
		850	* DESCRIPTION:
		851	* .
		852	*
		853	* RETURNS:
		854	* -EINVAL on failure, 0 on success
		855	*
		856	*
		857	* CALLED FROM:
		858	* rivafb_check_var()
		859	*/
		860	static int rivafb_do_maximize(struct fb_info *info,
		861	struct fb_var_screeninfo *var,
		862	int nom, int den)
		863	{
		864	static struct {
		865	int xres, yres;
		866	} modes[] = {
		867	{1600, 1280},
		868	{1280, 1024},
		869	{1024, 768},
		870	{800, 600},
		871	{640, 480},
		872	{-1, -1}
		873	};
		874	int i;
		875
		876	/* use highest possible virtual resolution */
		877	if (var->xres_virtual == -1 && var->yres_virtual == -1) {
		878	printk(KERN_WARNING PFX
		879	"using maximum available virtual resolution\n");
		880	for (i = 0; modes[i].xres != -1; i++) {
		881	if (modes[i].xres * nom / den * modes[i].yres <
		882	info->fix.smem_len / 2)
		883	break;
		884	}
		885	if (modes[i].xres == -1) {
		886	printk(KERN_ERR PFX
		887	"could not find a virtual resolution that fits into video memory!!\n");
		888	DPRINTK("EXIT - EINVAL error\n");
		889	return -EINVAL;
		890	}
		891	var->xres_virtual = modes[i].xres;
		892	var->yres_virtual = modes[i].yres;
		893
		894	printk(KERN_INFO PFX
		895	"virtual resolution set to maximum of %dx%d\n",
		896	var->xres_virtual, var->yres_virtual);
		897	} else if (var->xres_virtual == -1) {
		898	var->xres_virtual = (info->fix.smem_len * den /
		899	(nom * var->yres_virtual * 2)) & ~15;
		900	printk(KERN_WARNING PFX
		901	"setting virtual X resolution to %d\n", var->xres_virtual);
		902	} else if (var->yres_virtual == -1) {
		903	var->xres_virtual = (var->xres_virtual + 15) & ~15;
		904	var->yres_virtual = info->fix.smem_len * den /
		905	(nom * var->xres_virtual * 2);
		906	printk(KERN_WARNING PFX
		907	"setting virtual Y resolution to %d\n", var->yres_virtual);
		908	} else {
		909	var->xres_virtual = (var->xres_virtual + 15) & ~15;
		910	if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
		911	printk(KERN_ERR PFX
		912	"mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
		913	var->xres, var->yres, var->bits_per_pixel);
		914	DPRINTK("EXIT - EINVAL error\n");
		915	return -EINVAL;
		916	}
		917	}
		918
		919	if (var->xres_virtual * nom / den >= 8192) {
		920	printk(KERN_WARNING PFX
		921	"virtual X resolution (%d) is too high, lowering to %d\n",
		922	var->xres_virtual, 8192 * den / nom - 16);
		923	var->xres_virtual = 8192 * den / nom - 16;
		924	}
		925
		926	if (var->xres_virtual < var->xres) {
		927	printk(KERN_ERR PFX
		928	"virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
		929	return -EINVAL;
		930	}
		931
		932	if (var->yres_virtual < var->yres) {
		933	printk(KERN_ERR PFX
		934	"virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
		935	return -EINVAL;
		936	}
		937	return 0;
		938	}
		939
		940	/* acceleration routines */
		941	inline void wait_for_idle(struct riva_par *par)
		942	{
		943	while (par->riva.Busy(&par->riva));
		944	}
		945
		946	/* set copy ROP, no mask */
		947	static void riva_setup_ROP(struct riva_par *par)
		948	{
		949	RIVA_FIFO_FREE(par->riva, Patt, 5);
		950	par->riva.Patt->Shape = 0;
		951	par->riva.Patt->Color0 = 0xffffffff;
		952	par->riva.Patt->Color1 = 0xffffffff;
		953	par->riva.Patt->Monochrome[0] = 0xffffffff;
		954	par->riva.Patt->Monochrome[1] = 0xffffffff;
		955
		956	RIVA_FIFO_FREE(par->riva, Rop, 1);
		957	par->riva.Rop->Rop3 = 0xCC;
		958	}
		959
		960	void riva_setup_accel(struct riva_par *par)
		961	{
		962	RIVA_FIFO_FREE(par->riva, Clip, 2);
		963	par->riva.Clip->TopLeft = 0x0;
		964	par->riva.Clip->WidthHeight = 0x80008000;
		965	riva_setup_ROP(par);
		966	wait_for_idle(par);
		967	}
		968
		969	/**
		970	* riva_get_cmap_len - query current color map length
		971	* @var: standard kernel fb changeable data
		972	*
		973	* DESCRIPTION:
		974	* Get current color map length.
		975	*
		976	* RETURNS:
		977	* Length of color map
		978	*
		979	* CALLED FROM:
		980	* rivafb_setcolreg()
		981	*/
		982	static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
		983	{
		984	int rc = 256; /* reasonable default */
		985
		986	switch (var->green.length) {
		987	case 8:
		988	rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
		989	break;
		990	case 5:
		991	rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
		992	break;
		993	case 6:
		994	rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
		995	break;
		996	default:
		997	/* should not occur */
		998	break;
		999	}
		1000	return rc;
		1001	}
		1002
		1003	/* ------------------------------------------------------------------------- *
		1004	*
		1005	* framebuffer operations
		1006	*
		1007	* ------------------------------------------------------------------------- */
		1008
		1009	static int rivafb_open(struct fb_info *info, int user)
		1010	{
		1011	struct riva_par par = (struct riva_par ) info->par;
		1012	int cnt = atomic_read(&par->ref_count);
		1013
		1014	if (!cnt) {
		1015	memset(&par->state, 0, sizeof(struct vgastate));
		1016	par->state.flags = VGA_SAVE_MODE \| VGA_SAVE_FONTS;
		1017	/* save the DAC for Riva128 */
		1018	if (par->riva.Architecture == NV_ARCH_03)
		1019	par->state.flags \|= VGA_SAVE_CMAP;
		1020	save_vga(&par->state);
		1021
		1022	RivaGetConfig(&par->riva, par->Chipset);
		1023	/* vgaHWunlock() + riva unlock (0x7F) */
		1024	CRTCout(par, 0x11, 0xFF);
		1025	par->riva.LockUnlock(&par->riva, 0);
		1026
		1027	riva_save_state(par, &par->initial_state);
		1028	}
		1029	atomic_inc(&par->ref_count);
		1030	return 0;
		1031	}
		1032
		1033	static int rivafb_release(struct fb_info *info, int user)
		1034	{
		1035	struct riva_par par = (struct riva_par ) info->par;
		1036	int cnt = atomic_read(&par->ref_count);
		1037
		1038	if (!cnt)
		1039	return -EINVAL;
		1040	if (cnt == 1) {
		1041	par->riva.LockUnlock(&par->riva, 0);
		1042	par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
		1043	riva_load_state(par, &par->initial_state);
		1044	restore_vga(&par->state);
		1045	par->riva.LockUnlock(&par->riva, 1);
		1046	}
		1047	atomic_dec(&par->ref_count);
		1048	return 0;
		1049	}
		1050
		1051	static int rivafb_check_var(struct fb_var_screeninfo var, struct fb_info info)
		1052	{
		1053	int nom, den; /* translating from pixels->bytes */
		1054
		1055	switch (var->bits_per_pixel) {
		1056	case 1 ... 8:
		1057	var->red.offset = var->green.offset = var->blue.offset = 0;
		1058	var->red.length = var->green.length = var->blue.length = 8;
		1059	var->bits_per_pixel = 8;
		1060	nom = den = 1;
		1061	break;
		1062	case 9 ... 15:
		1063	var->green.length = 5;
		1064	/* fall through */
		1065	case 16:
		1066	var->bits_per_pixel = 16;
		1067	if (var->green.length == 5) {
		1068	/* 0rrrrrgg gggbbbbb */
		1069	var->red.offset = 10;
		1070	var->green.offset = 5;
		1071	var->blue.offset = 0;
		1072	var->red.length = 5;
		1073	var->green.length = 5;
		1074	var->blue.length = 5;
		1075	} else {
		1076	/* rrrrrggg gggbbbbb */
		1077	var->red.offset = 11;
		1078	var->green.offset = 5;
		1079	var->blue.offset = 0;
		1080	var->red.length = 5;
		1081	var->green.length = 6;
		1082	var->blue.length = 5;
		1083	}
		1084	nom = 2;
		1085	den = 1;
		1086	break;
		1087	case 17 ... 32:
		1088	var->red.length = var->green.length = var->blue.length = 8;
		1089	var->bits_per_pixel = 32;
		1090	var->red.offset = 16;
		1091	var->green.offset = 8;
		1092	var->blue.offset = 0;
		1093	nom = 4;
		1094	den = 1;
		1095	break;
		1096	default:
		1097	printk(KERN_ERR PFX
		1098	"mode %dx%dx%d rejected...color depth not supported.\n",
		1099	var->xres, var->yres, var->bits_per_pixel);
		1100	DPRINTK("EXIT, returning -EINVAL\n");
		1101	return -EINVAL;
		1102	}
		1103
		1104	if (rivafb_do_maximize(info, var, nom, den) < 0)
		1105	return -EINVAL;
		1106
		1107	if (var->xoffset < 0)
		1108	var->xoffset = 0;
		1109	if (var->yoffset < 0)
		1110	var->yoffset = 0;
		1111
		1112	/* truncate xoffset and yoffset to maximum if too high */
		1113	if (var->xoffset > var->xres_virtual - var->xres)
		1114	var->xoffset = var->xres_virtual - var->xres - 1;
		1115
		1116	if (var->yoffset > var->yres_virtual - var->yres)
		1117	var->yoffset = var->yres_virtual - var->yres - 1;
		1118
		1119	var->red.msb_right =
		1120	var->green.msb_right =
		1121	var->blue.msb_right =
		1122	var->transp.offset = var->transp.length = var->transp.msb_right = 0;
		1123	return 0;
		1124	}
		1125
		1126	static int rivafb_set_par(struct fb_info *info)
		1127	{
		1128	struct riva_par par = (struct riva_par ) info->par;
		1129
		1130	riva_load_video_mode(info);
		1131	riva_setup_accel(par);
		1132
		1133	info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
		1134	info->fix.visual = (info->var.bits_per_pixel == 8) ?
		1135	FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
		1136	return 0;
		1137	}
		1138
		1139	/**
		1140	* rivafb_pan_display
		1141	* @var: standard kernel fb changeable data
		1142	* @con: TODO
		1143	* @info: pointer to fb_info object containing info for current riva board
		1144	*
		1145	* DESCRIPTION:
		1146	* Pan (or wrap, depending on the `vmode' field) the display using the
		1147	* `xoffset' and `yoffset' fields of the `var' structure.
		1148	* If the values don't fit, return -EINVAL.
		1149	*
		1150	* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
		1151	*/
		1152	static int rivafb_pan_display(struct fb_var_screeninfo *var,
		1153	struct fb_info *info)
		1154	{
		1155	struct riva_par par = (struct riva_par )info->par;
		1156	unsigned int base;
		1157
		1158	if (var->xoffset > (var->xres_virtual - var->xres))
		1159	return -EINVAL;
		1160	if (var->yoffset > (var->yres_virtual - var->yres))
		1161	return -EINVAL;
		1162
		1163	if (var->vmode & FB_VMODE_YWRAP) {
		1164	if (var->yoffset < 0
		1165	\|\| var->yoffset >= info->var.yres_virtual
		1166	\|\| var->xoffset) return -EINVAL;
		1167	} else {
		1168	if (var->xoffset + info->var.xres > info->var.xres_virtual \|\|
		1169	var->yoffset + info->var.yres > info->var.yres_virtual)
		1170	return -EINVAL;
		1171	}
		1172
		1173	base = var->yoffset * info->fix.line_length + var->xoffset;
		1174
		1175	par->riva.SetStartAddress(&par->riva, base);
		1176
		1177	info->var.xoffset = var->xoffset;
		1178	info->var.yoffset = var->yoffset;
		1179
		1180	if (var->vmode & FB_VMODE_YWRAP)
		1181	info->var.vmode \|= FB_VMODE_YWRAP;
		1182	else
		1183	info->var.vmode &= ~FB_VMODE_YWRAP;
		1184	return 0;
		1185	}
		1186
		1187	static int rivafb_blank(int blank, struct fb_info *info)
		1188	{
		1189	struct riva_par par= (struct riva_par )info->par;
		1190	unsigned char tmp, vesa;
		1191
		1192	tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
		1193	vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
		1194
		1195	if (blank) {
		1196	tmp \|= 0x20;
		1197	switch (blank - 1) {
		1198	case VESA_NO_BLANKING:
		1199	break;
		1200	case VESA_VSYNC_SUSPEND:
		1201	vesa \|= 0x80;
		1202	break;
		1203	case VESA_HSYNC_SUSPEND:
		1204	vesa \|= 0x40;
		1205	break;
		1206	case VESA_POWERDOWN:
		1207	vesa \|= 0xc0;
		1208	break;
		1209	}
		1210	}
		1211	SEQout(par, 0x01, tmp);
		1212	CRTCout(par, 0x1a, vesa);
		1213	return 0;
		1214	}
		1215
		1216	/**
		1217	* rivafb_setcolreg
		1218	* @regno: register index
		1219	* @red: red component
		1220	* @green: green component
		1221	* @blue: blue component
		1222	* @transp: transparency
		1223	* @info: pointer to fb_info object containing info for current riva board
		1224	*
		1225	* DESCRIPTION:
		1226	* Set a single color register. The values supplied have a 16 bit
		1227	* magnitude.
		1228	*
		1229	* RETURNS:
		1230	* Return != 0 for invalid regno.
		1231	*
		1232	* CALLED FROM:
		1233	* fbcmap.c:fb_set_cmap()
		1234	*/
		1235	static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
		1236	unsigned blue, unsigned transp,
		1237	struct fb_info *info)
		1238	{
		1239	struct riva_par par = (struct riva_par )info->par;
		1240	RIVA_HW_INST *chip = &par->riva;
		1241	int i;
		1242
		1243	if (regno >= riva_get_cmap_len(&info->var))
		1244	return -EINVAL;
		1245
		1246	if (info->var.grayscale) {
		1247	/* gray = 0.30R + 0.59G + 0.11B /
		1248	red = green = blue =
		1249	(red * 77 + green * 151 + blue * 28) >> 8;
		1250	}
		1251
		1252	switch (info->var.bits_per_pixel) {
		1253	case 8:
		1254	/* "transparent" stuff is completely ignored. */
		1255	riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
		1256	break;
		1257	case 16:
		1258	if (info->var.green.length == 5) {
		1259	if (regno < 16) {
		1260	/* 0rrrrrgg gggbbbbb */
		1261	((u32 *)info->pseudo_palette)[regno] =
		1262	((red & 0xf800) >> 1) \|
		1263	((green & 0xf800) >> 6) \|
		1264	((blue & 0xf800) >> 11);
		1265	}
		1266	for (i = 0; i < 8; i++)
		1267	riva_wclut(chip, regno*8+i, red >> 8,
		1268	green >> 8, blue >> 8);
		1269	} else {
		1270	u8 r, g, b;
		1271
		1272	if (regno < 16) {
		1273	/* rrrrrggg gggbbbbb */
		1274	((u32 *)info->pseudo_palette)[regno] =
		1275	((red & 0xf800) >> 0) \|
		1276	((green & 0xf800) >> 5) \|
		1277	((blue & 0xf800) >> 11);
		1278	}
		1279	if (regno < 32) {
		1280	for (i = 0; i < 8; i++) {
		1281	riva_wclut(chip, regno*8+i, red >> 8,
		1282	green >> 8, blue >> 8);
		1283	}
		1284	}
		1285	for (i = 0; i < 4; i++) {
		1286	riva_rclut(chip, regno*2+i, &r, &g, &b);
		1287	riva_wclut(chip, regno*4+i, r, green >> 8, b);
		1288	}
		1289	}
		1290	break;
		1291	case 32:
		1292	if (regno < 16) {
		1293	((u32 *)info->pseudo_palette)[regno] =
		1294	((red & 0xff00) << 8) \|
		1295	((green & 0xff00)) \| ((blue & 0xff00) >> 8);
		1296
		1297	}
		1298	riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
		1299	break;
		1300	default:
		1301	/* do nothing */
		1302	break;
		1303	}
		1304	return 0;
		1305	}
		1306
		1307	/**
		1308	* rivafb_fillrect - hardware accelerated color fill function
		1309	* @info: pointer to fb_info structure
		1310	* @rect: pointer to fb_fillrect structure
		1311	*
		1312	* DESCRIPTION:
		1313	* This function fills up a region of framebuffer memory with a solid
		1314	* color with a choice of two different ROP's, copy or invert.
		1315	*
		1316	* CALLED FROM:
		1317	* framebuffer hook
		1318	*/
		1319	static void rivafb_fillrect(struct fb_info info, const struct fb_fillrect rect)
		1320	{
		1321	struct riva_par par = (struct riva_par ) info->par;
		1322	u_int color, rop = 0;
		1323
		1324	if (info->var.bits_per_pixel == 8)
		1325	color = rect->color;
		1326	else
		1327	color = ((u32 *)info->pseudo_palette)[rect->color];
		1328
		1329	switch (rect->rop) {
		1330	case ROP_XOR:
		1331	rop = 0x66;
		1332	break;
		1333	case ROP_COPY:
		1334	default:
		1335	rop = 0xCC;
		1336	break;
		1337	}
		1338
		1339	RIVA_FIFO_FREE(par->riva, Rop, 1);
		1340	par->riva.Rop->Rop3 = rop;
		1341
		1342	RIVA_FIFO_FREE(par->riva, Bitmap, 1);
		1343	par->riva.Bitmap->Color1A = color;
		1344
		1345	RIVA_FIFO_FREE(par->riva, Bitmap, 2);
		1346	par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
		1347	(rect->dx << 16) \| rect->dy;
		1348	par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
		1349	(rect->width << 16) \| rect->height;
		1350	RIVA_FIFO_FREE(par->riva, Rop, 1);
		1351	par->riva.Rop->Rop3 = 0xCC; // back to COPY
		1352	}
		1353
		1354	/**
		1355	* rivafb_copyarea - hardware accelerated blit function
		1356	* @info: pointer to fb_info structure
		1357	* @region: pointer to fb_copyarea structure
		1358	*
		1359	* DESCRIPTION:
		1360	* This copies an area of pixels from one location to another
		1361	*
		1362	* CALLED FROM:
		1363	* framebuffer hook
		1364	*/
		1365	static void rivafb_copyarea(struct fb_info info, const struct fb_copyarea region)
		1366	{
		1367	struct riva_par par = (struct riva_par ) info->par;
		1368
		1369	RIVA_FIFO_FREE(par->riva, Blt, 3);
		1370	par->riva.Blt->TopLeftSrc = (region->sy << 16) \| region->sx;
		1371	par->riva.Blt->TopLeftDst = (region->dy << 16) \| region->dx;
		1372	par->riva.Blt->WidthHeight = (region->height << 16) \| region->width;
		1373	wait_for_idle(par);
		1374	}
		1375
		1376	static inline void convert_bgcolor_16(u32 *col)
		1377	{
		1378	col = ((col & 0x00007C00) << 9)
		1379	\| ((*col & 0x000003E0) << 6)
		1380	\| ((*col & 0x0000001F) << 3)
		1381	\| 0xFF000000;
		1382	}
		1383
		1384	/**
		1385	* rivafb_imageblit: hardware accelerated color expand function
		1386	* @info: pointer to fb_info structure
		1387	* @image: pointer to fb_image structure
		1388	*
		1389	* DESCRIPTION:
		1390	* If the source is a monochrome bitmap, the function fills up a a region
		1391	* of framebuffer memory with pixels whose color is determined by the bit
		1392	* setting of the bitmap, 1 - foreground, 0 - background.
		1393	*
		1394	* If the source is not a monochrome bitmap, color expansion is not done.
		1395	* In this case, it is channeled to a software function.
		1396	*
		1397	* CALLED FROM:
		1398	* framebuffer hook
		1399	*/
		1400	static void rivafb_imageblit(struct fb_info *info,
		1401	const struct fb_image *image)
		1402	{
		1403	struct riva_par par = (struct riva_par ) info->par;
		1404	u32 fgx = 0, bgx = 0, width, tmp;
		1405	u8 cdat = (u8 ) image->data;
		1406	volatile u32 *d;
		1407	int i, size;
		1408
		1409	if (image->depth != 1) {
		1410	cfb_imageblit(info, image);
		1411	return;
		1412	}
		1413
		1414	switch (info->var.bits_per_pixel) {
		1415	case 8:
		1416	fgx = image->fg_color;
		1417	bgx = image->bg_color;
		1418	break;
		1419	case 16:
		1420	fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
		1421	bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
		1422	if (info->var.green.length == 6)
		1423	convert_bgcolor_16(&bgx);
		1424	break;
		1425	case 32:
		1426	fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
		1427	bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
		1428	break;
		1429	}
		1430
		1431	RIVA_FIFO_FREE(par->riva, Bitmap, 7);
		1432	par->riva.Bitmap->ClipE.TopLeft =
		1433	(image->dy << 16) \| (image->dx & 0xFFFF);
		1434	par->riva.Bitmap->ClipE.BottomRight =
		1435	(((image->dy + image->height) << 16) \|
		1436	((image->dx + image->width) & 0xffff));
		1437	par->riva.Bitmap->Color0E = bgx;
		1438	par->riva.Bitmap->Color1E = fgx;
		1439	par->riva.Bitmap->WidthHeightInE =
		1440	(image->height << 16) \| ((image->width + 31) & ~31);
		1441	par->riva.Bitmap->WidthHeightOutE =
		1442	(image->height << 16) \| ((image->width + 31) & ~31);
		1443	par->riva.Bitmap->PointE =
		1444	(image->dy << 16) \| (image->dx & 0xFFFF);
		1445
		1446	d = &par->riva.Bitmap->MonochromeData01E;
		1447
		1448	width = (image->width + 31)/32;
		1449	size = width * image->height;
		1450	while (size >= 16) {
		1451	RIVA_FIFO_FREE(par->riva, Bitmap, 16);
		1452	for (i = 0; i < 16; i++) {
1056	tullio	1453
		1454	// changed for gcc4 compatibility
		1455	//tmp = ((u32 )cdat)++;
		1456	tmp = ((u32 )(cdat));
		1457	tmp += sizeof(u32);
		1458
472	giacomo	1459	reverse_order(&tmp);
		1460	d[i] = tmp;
		1461	}
		1462	size -= 16;
		1463	}
		1464	if (size) {
		1465	RIVA_FIFO_FREE(par->riva, Bitmap, size);
		1466	for (i = 0; i < size; i++) {
1056	tullio	1467
		1468	// changed for gcc4 compatibility
		1469	//tmp = ((u32 ) cdat)++;
		1470	tmp = ((u32 )(cdat));
		1471	tmp += sizeof(u32);
		1472
472	giacomo	1473	reverse_order(&tmp);
		1474	d[i] = tmp;
		1475	}
		1476	}
		1477	}
		1478
		1479	/**
		1480	* rivafb_cursor - hardware cursor function
		1481	* @info: pointer to info structure
		1482	* @cursor: pointer to fbcursor structure
		1483	*
		1484	* DESCRIPTION:
		1485	* A cursor function that supports displaying a cursor image via hardware.
		1486	* Within the kernel, copy and invert rops are supported. If exported
		1487	* to user space, only the copy rop will be supported.
		1488	*
		1489	* CALLED FROM
		1490	* framebuffer hook
		1491	*/
		1492	static int rivafb_cursor(struct fb_info info, struct fb_cursor cursor)
		1493	{
		1494	struct riva_par par = (struct riva_par ) info->par;
		1495	u8 data[MAX_CURS * MAX_CURS/8];
		1496	u8 mask[MAX_CURS * MAX_CURS/8];
		1497	u16 fg, bg;
		1498	int i;
		1499
		1500	par->riva.ShowHideCursor(&par->riva, 0);
		1501
		1502	if (cursor->set & FB_CUR_SETPOS) {
		1503	u32 xx, yy, temp;
		1504
		1505	info->cursor.image.dx = cursor->image.dx;
		1506	info->cursor.image.dy = cursor->image.dy;
		1507	yy = cursor->image.dy - info->var.yoffset;
		1508	xx = cursor->image.dx - info->var.xoffset;
		1509	temp = xx & 0xFFFF;
		1510	temp \|= yy << 16;
		1511
		1512	par->riva.PRAMDAC[0x0000300/4] = temp;
		1513	}
		1514
		1515	if (cursor->set & FB_CUR_SETSIZE) {
		1516	info->cursor.image.height = cursor->image.height;
		1517	info->cursor.image.width = cursor->image.width;
		1518	memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
		1519	}
		1520
		1521	if (cursor->set & FB_CUR_SETCMAP) {
		1522	info->cursor.image.bg_color = cursor->image.bg_color;
		1523	info->cursor.image.fg_color = cursor->image.fg_color;
		1524	}
		1525
		1526	if (cursor->set & (FB_CUR_SETSHAPE \| FB_CUR_SETCMAP)) {
		1527	u32 bg_idx = info->cursor.image.bg_color;
		1528	u32 fg_idx = info->cursor.image.fg_color;
		1529	u32 s_pitch = (info->cursor.image.width+7) >> 3;
		1530	u32 d_pitch = MAX_CURS/8;
		1531	u8 dat = (u8 ) cursor->image.data;
		1532	u8 msk = (u8 ) info->cursor.mask;
		1533	u8 src[64];
		1534
		1535	switch (info->cursor.rop) {
		1536	case ROP_XOR:
		1537	for (i = 0; i < s_pitch * info->cursor.image.height; i++)
		1538	src[i] = dat[i] ^ msk[i];
		1539	break;
		1540	case ROP_COPY:
		1541	default:
		1542	for (i = 0; i < s_pitch * info->cursor.image.height; i++)
		1543
		1544	src[i] = dat[i] & msk[i];
		1545	break;
		1546	}
		1547
		1548	move_buf_aligned(info, data, src, d_pitch, s_pitch, info->cursor.image.height);
		1549
		1550	move_buf_aligned(info, mask, msk, d_pitch, s_pitch, info->cursor.image.height);
		1551
		1552	bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) \|
		1553	((info->cmap.green[bg_idx] & 0xf8) << 2) \|
		1554	((info->cmap.blue[bg_idx] & 0xf8) >> 3);
		1555
		1556	fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) \|
		1557	((info->cmap.green[fg_idx] & 0xf8) << 2) \|
		1558	((info->cmap.blue[fg_idx] & 0xf8) >> 3);
		1559
		1560	par->riva.LockUnlock(&par->riva, 0);
		1561
		1562	rivafb_load_cursor_image(par, data, mask, bg, fg,
		1563	info->cursor.image.width,
		1564	info->cursor.image.height);
		1565	}
		1566	if (info->cursor.enable)
		1567	par->riva.ShowHideCursor(&par->riva, 1);
		1568	return 0;
		1569	}
		1570
		1571	static int rivafb_sync(struct fb_info *info)
		1572	{
		1573	struct riva_par par = (struct riva_par )info->par;
		1574
		1575	wait_for_idle(par);
		1576	return 0;
		1577	}
		1578
		1579	/* ------------------------------------------------------------------------- *
		1580	*
		1581	* initialization helper functions
		1582	*
		1583	* ------------------------------------------------------------------------- */
		1584
		1585	/* kernel interface */
		1586	static struct fb_ops riva_fb_ops = {
		1587	.owner = THIS_MODULE,
		1588	.fb_open = rivafb_open,
		1589	.fb_release = rivafb_release,
		1590	.fb_check_var = rivafb_check_var,
		1591	.fb_set_par = rivafb_set_par,
		1592	.fb_setcolreg = rivafb_setcolreg,
		1593	.fb_pan_display = rivafb_pan_display,
		1594	.fb_blank = rivafb_blank,
		1595	.fb_fillrect = rivafb_fillrect,
		1596	.fb_copyarea = rivafb_copyarea,
		1597	.fb_imageblit = rivafb_imageblit,
		1598	.fb_cursor = rivafb_cursor,
		1599	.fb_sync = rivafb_sync,
		1600	};
		1601
		1602	static int __devinit riva_set_fbinfo(struct fb_info *info)
		1603	{
		1604	struct riva_par par = (struct riva_par ) info->par;
		1605	unsigned int cmap_len;
		1606
		1607	info->flags = FBINFO_FLAG_DEFAULT;
		1608	info->var = rivafb_default_var;
		1609	info->fix = rivafb_fix;
		1610	info->fbops = &riva_fb_ops;
		1611	info->pseudo_palette = pseudo_palette;
		1612
		1613	#ifndef MODULE
		1614	if (mode_option)
		1615	fb_find_mode(&info->var, info, mode_option,
		1616	NULL, 0, NULL, 8);
		1617	#endif
		1618	if (par->use_default_var)
		1619	/* We will use the modified default var */
		1620	info->var = rivafb_default_var;
		1621
		1622	cmap_len = riva_get_cmap_len(&info->var);
		1623	fb_alloc_cmap(&info->cmap, cmap_len, 0);
		1624
		1625	info->pixmap.size = 64 * 1024;
		1626	info->pixmap.buf_align = 4;
		1627	info->pixmap.scan_align = 4;
		1628	info->pixmap.flags = FB_PIXMAP_SYSTEM;
		1629	return 0;
		1630	}
		1631
		1632	#ifdef CONFIG_PPC_OF
		1633	static int riva_get_EDID_OF(struct riva_par par, struct pci_dev pd)
		1634	{
		1635	struct device_node *dp;
		1636	unsigned char *pedid = NULL;
		1637
		1638	dp = pci_device_to_OF_node(pd);
		1639	pedid = (unsigned char *)get_property(dp, "EDID,B", 0);
		1640
		1641	if (pedid) {
		1642	par->EDID = pedid;
		1643	return 1;
		1644	} else
		1645	return 0;
		1646	}
		1647	#endif /* CONFIG_PPC_OF */
		1648
		1649	static int riva_dfp_parse_EDID(struct riva_par *par)
		1650	{
		1651	unsigned char *block = par->EDID;
		1652
		1653	if (!block)
		1654	return 0;
		1655
		1656	/* jump to detailed timing block section */
		1657	block += 54;
		1658
		1659	par->clock = (block[0] + (block[1] << 8));
		1660	par->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
		1661	par->hblank = (block[3] + ((block[4] & 0x0f) << 8));
		1662	par->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
		1663	par->vblank = (block[6] + ((block[7] & 0x0f) << 8));
		1664	par->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
		1665	par->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
		1666	par->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
		1667	par->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
		1668	par->interlaced = ((block[17] & 0x80) >> 7);
		1669	par->synct = ((block[17] & 0x18) >> 3);
		1670	par->misc = ((block[17] & 0x06) >> 1);
		1671	par->hAct_high = par->vAct_high = 0;
		1672	if (par->synct == 3) {
		1673	if (par->misc & 2)
		1674	par->hAct_high = 1;
		1675	if (par->misc & 1)
		1676	par->vAct_high = 1;
		1677	}
		1678
		1679	printk(KERN_INFO PFX
		1680	"detected DFP panel size from EDID: %dx%d\n",
		1681	par->panel_xres, par->panel_yres);
		1682	par->got_dfpinfo = 1;
		1683	return 1;
		1684	}
		1685
		1686	static void riva_update_default_var(struct fb_info *info)
		1687	{
		1688	struct fb_var_screeninfo *var = &rivafb_default_var;
		1689	struct riva_par par = (struct riva_par ) info->par;
		1690
		1691	var->xres = par->panel_xres;
		1692	var->yres = par->panel_yres;
		1693	var->xres_virtual = par->panel_xres;
		1694	var->yres_virtual = par->panel_yres;
		1695	var->xoffset = var->yoffset = 0;
		1696	var->bits_per_pixel = 8;
		1697	var->pixclock = 100000000 / par->clock;
		1698	var->left_margin = (par->hblank - par->hOver_plus - par->hSync_width);
		1699	var->right_margin = par->hOver_plus;
		1700	var->upper_margin = (par->vblank - par->vOver_plus - par->vSync_width);
		1701	var->lower_margin = par->vOver_plus;
		1702	var->hsync_len = par->hSync_width;
		1703	var->vsync_len = par->vSync_width;
		1704	var->sync = 0;
		1705
		1706	if (par->synct == 3) {
		1707	if (par->hAct_high)
		1708	var->sync \|= FB_SYNC_HOR_HIGH_ACT;
		1709	if (par->vAct_high)
		1710	var->sync \|= FB_SYNC_VERT_HIGH_ACT;
		1711	}
		1712
		1713	var->vmode = 0;
		1714	if (par->interlaced)
		1715	var->vmode \|= FB_VMODE_INTERLACED;
		1716
		1717	var->accel_flags \|= FB_ACCELF_TEXT;
		1718
		1719	par->use_default_var = 1;
		1720	}
		1721
		1722
		1723	static void riva_get_EDID(struct fb_info info, struct pci_dev pdev)
		1724	{
		1725	#ifdef CONFIG_PPC_OF
		1726	if (!riva_get_EDID_OF(info, pdev))
		1727	printk("rivafb: could not retrieve EDID from OF\n");
		1728	#else
		1729	/* XXX use other methods later */
		1730	#endif
		1731	}
		1732
		1733
		1734	static void riva_get_dfpinfo(struct fb_info *info)
		1735	{
		1736	struct riva_par par = (struct riva_par ) info->par;
		1737
		1738	if (riva_dfp_parse_EDID(par))
		1739	riva_update_default_var(info);
		1740
		1741	/* if user specified flatpanel, we respect that */
		1742	if (par->got_dfpinfo == 1)
		1743	par->FlatPanel = 1;
		1744	}
		1745
		1746	/* ------------------------------------------------------------------------- *
		1747	*
		1748	* PCI bus
		1749	*
		1750	* ------------------------------------------------------------------------- */
		1751
		1752	static int __devinit rivafb_probe(struct pci_dev *pd,
		1753	const struct pci_device_id *ent)
		1754	{
		1755	struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
		1756	struct riva_par *default_par;
		1757	struct fb_info *info;
		1758
		1759	assert(pd != NULL);
		1760	assert(rci != NULL);
		1761
		1762	info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
		1763	if (!info)
		1764	goto err_out;
		1765
		1766	default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
		1767	if (!default_par)
		1768	goto err_out_kfree;
		1769
		1770	memset(info, 0, sizeof(struct fb_info));
		1771	memset(default_par, 0, sizeof(struct riva_par));
		1772
		1773	info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
		1774	if (info->pixmap.addr == NULL)
		1775	goto err_out_kfree1;
		1776	memset(info->pixmap.addr, 0, 64 * 1024);
		1777
		1778	strcat(rivafb_fix.id, rci->name);
		1779	default_par->riva.Architecture = rci->arch_rev;
		1780
		1781	default_par->Chipset = (pd->vendor << 16) \| pd->device;
		1782	printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
		1783
		1784	default_par->FlatPanel = flatpanel;
		1785	if (flatpanel == 1)
		1786	printk(KERN_INFO PFX "flatpanel support enabled\n");
		1787	default_par->forceCRTC = forceCRTC;
		1788
		1789	rivafb_fix.mmio_len = pci_resource_len(pd, 0);
		1790	rivafb_fix.smem_len = pci_resource_len(pd, 1);
		1791
		1792	{
		1793	/* enable IO and mem if not already done */
		1794	unsigned short cmd;
		1795
		1796	pci_read_config_word(pd, PCI_COMMAND, &cmd);
		1797	cmd \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
		1798	pci_write_config_word(pd, PCI_COMMAND, cmd);
		1799	}
		1800
		1801	rivafb_fix.mmio_start = pci_resource_start(pd, 0);
		1802	rivafb_fix.smem_start = pci_resource_start(pd, 1);
		1803
		1804	if (!request_mem_region(rivafb_fix.mmio_start,
		1805	rivafb_fix.mmio_len, "rivafb")) {
		1806	printk(KERN_ERR PFX "cannot reserve MMIO region\n");
		1807	goto err_out_kfree2;
		1808	}
		1809
		1810	default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
		1811	rivafb_fix.mmio_len);
		1812	if (!default_par->ctrl_base) {
		1813	printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
		1814	goto err_out_free_base0;
		1815	}
		1816
		1817	info->par = default_par;
		1818
		1819	riva_get_EDID(info, pd);
		1820
		1821	riva_get_dfpinfo(info);
		1822
		1823	switch (default_par->riva.Architecture) {
		1824	case NV_ARCH_03:
		1825	/* Riva128's PRAMIN is in the "framebuffer" space
		1826	* Since these cards were never made with more than 8 megabytes
		1827	* we can safely allocate this separately.
		1828	*/
		1829	if (!request_mem_region(rivafb_fix.smem_start + 0x00C00000,
		1830	0x00008000, "rivafb")) {
		1831	printk(KERN_ERR PFX "cannot reserve PRAMIN region\n");
		1832	goto err_out_iounmap_ctrl;
		1833	}
		1834	default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
		1835	if (!default_par->riva.PRAMIN) {
		1836	printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
		1837	goto err_out_free_nv3_pramin;
		1838	}
		1839	rivafb_fix.accel = FB_ACCEL_NV3;
		1840	break;
		1841	case NV_ARCH_04:
		1842	case NV_ARCH_10:
		1843	case NV_ARCH_20:
		1844	default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
		1845	default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
		1846	rivafb_fix.accel = FB_ACCEL_NV4;
		1847	break;
		1848	}
		1849
		1850	riva_common_setup(default_par);
		1851
		1852	if (default_par->riva.Architecture == NV_ARCH_03) {
		1853	default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
		1854	}
		1855
		1856	rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
		1857	default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
		1858
		1859	if (!request_mem_region(rivafb_fix.smem_start,
		1860	rivafb_fix.smem_len, "rivafb")) {
		1861	printk(KERN_ERR PFX "cannot reserve FB region\n");
		1862	goto err_out_iounmap_nv3_pramin;
		1863	}
		1864
		1865	info->screen_base = ioremap(rivafb_fix.smem_start,
		1866	rivafb_fix.smem_len);
		1867	if (!info->screen_base) {
		1868	printk(KERN_ERR PFX "cannot ioremap FB base\n");
		1869	goto err_out_free_base1;
		1870	}
		1871
		1872	#ifdef CONFIG_MTRR
		1873	if (!nomtrr) {
		1874	default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
		1875	rivafb_fix.smem_len,
		1876	MTRR_TYPE_WRCOMB, 1);
		1877	if (default_par->mtrr.vram < 0) {
		1878	printk(KERN_ERR PFX "unable to setup MTRR\n");
		1879	} else {
		1880	default_par->mtrr.vram_valid = 1;
		1881	/* let there be speed */
		1882	printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
		1883	}
		1884	}
		1885	#endif /* CONFIG_MTRR */
		1886
		1887	if (riva_set_fbinfo(info) < 0) {
		1888	printk(KERN_ERR PFX "error setting initial video mode\n");
		1889	goto err_out_iounmap_fb;
		1890	}
		1891
		1892	if (register_framebuffer(info) < 0) {
		1893	printk(KERN_ERR PFX
		1894	"error registering riva framebuffer\n");
		1895	goto err_out_iounmap_fb;
		1896	}
		1897
		1898	pci_set_drvdata(pd, info);
		1899
		1900	printk(KERN_INFO PFX
475	giacomo	1901	"PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%x)\n",
472	giacomo	1902	default_par->riva.Architecture,
		1903	RIVAFB_VERSION,
		1904	info->fix.id,
		1905	info->fix.smem_len / (1024 * 1024),
477	giacomo	1906	(int)info->fix.smem_start);
472	giacomo	1907	return 0;
		1908
		1909	err_out_iounmap_fb:
		1910	iounmap(info->screen_base);
		1911	err_out_free_base1:
		1912	release_mem_region(rivafb_fix.smem_start, rivafb_fix.smem_len);
		1913	err_out_iounmap_nv3_pramin:
		1914	if (default_par->riva.Architecture == NV_ARCH_03)
		1915	iounmap((caddr_t)default_par->riva.PRAMIN);
		1916	err_out_free_nv3_pramin:
		1917	if (default_par->riva.Architecture == NV_ARCH_03)
		1918	release_mem_region(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
		1919	err_out_iounmap_ctrl:
		1920	iounmap(default_par->ctrl_base);
		1921	err_out_free_base0:
		1922	release_mem_region(rivafb_fix.mmio_start, rivafb_fix.mmio_len);
		1923	err_out_kfree2:
		1924	kfree(info->pixmap.addr);
		1925	err_out_kfree1:
		1926	kfree(default_par);
		1927	err_out_kfree:
		1928	kfree(info);
		1929	err_out:
		1930	return -ENODEV;
		1931	}
		1932
		1933	static void __exit rivafb_remove(struct pci_dev *pd)
		1934	{
		1935	struct fb_info *info = pci_get_drvdata(pd);
		1936	struct riva_par par = (struct riva_par ) info->par;
		1937
		1938	if (!info)
		1939	return;
		1940
		1941	unregister_framebuffer(info);
		1942	#ifdef CONFIG_MTRR
		1943	if (par->mtrr.vram_valid)
		1944	mtrr_del(par->mtrr.vram, info->fix.smem_start,
		1945	info->fix.smem_len);
		1946	#endif /* CONFIG_MTRR */
		1947
		1948	iounmap(par->ctrl_base);
		1949	iounmap(info->screen_base);
		1950
		1951	release_mem_region(info->fix.mmio_start,
		1952	info->fix.mmio_len);
		1953	release_mem_region(info->fix.smem_start,
		1954	info->fix.smem_len);
		1955
		1956	if (par->riva.Architecture == NV_ARCH_03) {
		1957	iounmap((caddr_t)par->riva.PRAMIN);
		1958	release_mem_region(info->fix.smem_start + 0x00C00000, 0x00008000);
		1959	}
		1960	kfree(info->pixmap.addr);
		1961	kfree(par);
		1962	kfree(info);
		1963	pci_set_drvdata(pd, NULL);
		1964	}
		1965
		1966	/* ------------------------------------------------------------------------- *
		1967	*
		1968	* initialization
		1969	*
		1970	* ------------------------------------------------------------------------- */
		1971
		1972	#ifndef MODULE
		1973	int __init rivafb_setup(char *options)
		1974	{
		1975	char *this_opt;
		1976
		1977	if (!options \|\| !*options)
		1978	return 0;
		1979
		1980	while ((this_opt = strsep(&options, ",")) != NULL) {
		1981	if (!strncmp(this_opt, "forceCRTC", 9)) {
		1982	char *p;
		1983
		1984	p = this_opt + 9;
		1985	if (!p \|\| !(++p)) continue;
		1986	forceCRTC = *p - '0';
		1987	if (forceCRTC < 0 \|\| forceCRTC > 1)
		1988	forceCRTC = -1;
		1989	} else if (!strncmp(this_opt, "flatpanel", 9)) {
		1990	flatpanel = 1;
		1991	#ifdef CONFIG_MTRR
		1992	} else if (!strncmp(this_opt, "nomtrr", 6)) {
		1993	nomtrr = 1;
		1994	#endif
		1995	} else
		1996	mode_option = this_opt;
		1997	}
		1998	return 0;
		1999	}
		2000	#endif /* !MODULE */
		2001
		2002	static struct pci_driver rivafb_driver = {
		2003	.name = "rivafb",
		2004	.id_table = rivafb_pci_tbl,
		2005	.probe = rivafb_probe,
		2006	.remove = __exit_p(rivafb_remove),
		2007	};
		2008
		2009
		2010
		2011	/* ------------------------------------------------------------------------- *
		2012	*
		2013	* modularization
		2014	*
		2015	* ------------------------------------------------------------------------- */
		2016
		2017	int __init rivafb_init(void)
		2018	{
		2019	if (pci_register_driver(&rivafb_driver) > 0)
		2020	return 0;
		2021	pci_unregister_driver(&rivafb_driver);
		2022	return -ENODEV;
		2023	}
		2024
		2025
		2026	#ifdef MODULE
		2027	static void __exit rivafb_exit(void)
		2028	{
		2029	pci_unregister_driver(&rivafb_driver);
		2030	}
		2031
		2032	module_init(rivafb_init);
		2033	module_exit(rivafb_exit);
		2034
		2035	MODULE_PARM(flatpanel, "i");
		2036	MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
		2037	MODULE_PARM(forceCRTC, "i");
		2038	MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
		2039
		2040	#ifdef CONFIG_MTRR
		2041	MODULE_PARM(nomtrr, "i");
		2042	MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
		2043	#endif
		2044	#endif /* MODULE */
		2045
		2046	MODULE_AUTHOR("Ani Joshi, maintainer");
		2047	MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
		2048	MODULE_LICENSE("GPL");

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(root)/shark/branches/xen/drivers/fb/riva/fbdev.c - Rev 1618