Rev 420 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 420 | giacomo | 1 | /* |
| 2 | * SMBus 2.0 driver for AMD-8111 IO-Hub. |
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| 3 | * |
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| 4 | * Copyright (c) 2002 Vojtech Pavlik |
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| 5 | * |
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| 6 | * This program is free software; you can redistribute it and/or modify |
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| 7 | * it under the terms of the GNU General Public License as published by |
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| 8 | * the Free Software Foundation version 2. |
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| 9 | */ |
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| 10 | |||
| 11 | #include <linux/module.h> |
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| 12 | #include <linux/pci.h> |
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| 13 | #include <linux/kernel.h> |
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| 14 | #include <linux/stddef.h> |
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| 15 | #include <linux/sched.h> |
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| 16 | #include <linux/ioport.h> |
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| 17 | #include <linux/init.h> |
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| 18 | #include <linux/i2c.h> |
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| 19 | #include <linux/delay.h> |
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| 20 | #include <asm/io.h> |
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| 21 | |||
| 22 | MODULE_LICENSE("GPL"); |
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| 23 | MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>"); |
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| 24 | MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver"); |
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| 25 | |||
| 26 | struct amd_smbus { |
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| 27 | struct pci_dev *dev; |
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| 28 | struct i2c_adapter adapter; |
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| 29 | int base; |
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| 30 | int size; |
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| 31 | }; |
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| 32 | |||
| 33 | /* |
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| 34 | * AMD PCI control registers definitions. |
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| 35 | */ |
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| 36 | |||
| 37 | #define AMD_PCI_MISC 0x48 |
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| 38 | |||
| 39 | #define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */ |
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| 40 | #define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */ |
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| 41 | #define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */ |
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| 42 | |||
| 43 | /* |
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| 44 | * ACPI 2.0 chapter 13 PCI interface definitions. |
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| 45 | */ |
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| 46 | |||
| 47 | #define AMD_EC_DATA 0x00 /* data register */ |
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| 48 | #define AMD_EC_SC 0x04 /* status of controller */ |
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| 49 | #define AMD_EC_CMD 0x04 /* command register */ |
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| 50 | #define AMD_EC_ICR 0x08 /* interrupt control register */ |
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| 51 | |||
| 52 | #define AMD_EC_SC_SMI 0x04 /* smi event pending */ |
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| 53 | #define AMD_EC_SC_SCI 0x02 /* sci event pending */ |
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| 54 | #define AMD_EC_SC_BURST 0x01 /* burst mode enabled */ |
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| 55 | #define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */ |
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| 56 | #define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */ |
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| 57 | #define AMD_EC_SC_OBF 0x01 /* data ready for host */ |
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| 58 | |||
| 59 | #define AMD_EC_CMD_RD 0x80 /* read EC */ |
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| 60 | #define AMD_EC_CMD_WR 0x81 /* write EC */ |
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| 61 | #define AMD_EC_CMD_BE 0x82 /* enable burst mode */ |
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| 62 | #define AMD_EC_CMD_BD 0x83 /* disable burst mode */ |
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| 63 | #define AMD_EC_CMD_QR 0x84 /* query EC */ |
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| 64 | |||
| 65 | /* |
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| 66 | * ACPI 2.0 chapter 13 access of registers of the EC |
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| 67 | */ |
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| 68 | |||
| 69 | unsigned int amd_ec_wait_write(struct amd_smbus *smbus) |
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| 70 | { |
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| 71 | int timeout = 500; |
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| 72 | |||
| 73 | while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF)) |
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| 74 | udelay(1); |
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| 75 | |||
| 76 | if (!timeout) { |
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| 77 | dev_warn(&smbus->dev->dev, "Timeout while waiting for IBF to clear\n"); |
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| 78 | return -1; |
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| 79 | } |
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| 80 | |||
| 81 | return 0; |
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| 82 | } |
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| 83 | |||
| 84 | unsigned int amd_ec_wait_read(struct amd_smbus *smbus) |
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| 85 | { |
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| 86 | int timeout = 500; |
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| 87 | |||
| 88 | while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF)) |
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| 89 | udelay(1); |
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| 90 | |||
| 91 | if (!timeout) { |
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| 92 | dev_warn(&smbus->dev->dev, "Timeout while waiting for OBF to set\n"); |
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| 93 | return -1; |
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| 94 | } |
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| 95 | |||
| 96 | return 0; |
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| 97 | } |
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| 98 | |||
| 99 | unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address, unsigned char *data) |
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| 100 | { |
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| 101 | if (amd_ec_wait_write(smbus)) |
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| 102 | return -1; |
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| 103 | outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD); |
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| 104 | |||
| 105 | if (amd_ec_wait_write(smbus)) |
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| 106 | return -1; |
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| 107 | outb(address, smbus->base + AMD_EC_DATA); |
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| 108 | |||
| 109 | if (amd_ec_wait_read(smbus)) |
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| 110 | return -1; |
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| 111 | *data = inb(smbus->base + AMD_EC_DATA); |
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| 112 | |||
| 113 | return 0; |
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| 114 | } |
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| 115 | |||
| 116 | unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address, unsigned char data) |
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| 117 | { |
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| 118 | if (amd_ec_wait_write(smbus)) |
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| 119 | return -1; |
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| 120 | outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD); |
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| 121 | |||
| 122 | if (amd_ec_wait_write(smbus)) |
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| 123 | return -1; |
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| 124 | outb(address, smbus->base + AMD_EC_DATA); |
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| 125 | |||
| 126 | if (amd_ec_wait_write(smbus)) |
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| 127 | return -1; |
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| 128 | outb(data, smbus->base + AMD_EC_DATA); |
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| 129 | |||
| 130 | return 0; |
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| 131 | } |
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| 132 | |||
| 133 | /* |
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| 134 | * ACPI 2.0 chapter 13 SMBus 2.0 EC register model |
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| 135 | */ |
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| 136 | |||
| 137 | #define AMD_SMB_PRTCL 0x00 /* protocol, PEC */ |
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| 138 | #define AMD_SMB_STS 0x01 /* status */ |
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| 139 | #define AMD_SMB_ADDR 0x02 /* address */ |
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| 140 | #define AMD_SMB_CMD 0x03 /* command */ |
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| 141 | #define AMD_SMB_DATA 0x04 /* 32 data registers */ |
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| 142 | #define AMD_SMB_BCNT 0x24 /* number of data bytes */ |
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| 143 | #define AMD_SMB_ALRM_A 0x25 /* alarm address */ |
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| 144 | #define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */ |
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| 145 | |||
| 146 | #define AMD_SMB_STS_DONE 0x80 |
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| 147 | #define AMD_SMB_STS_ALRM 0x40 |
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| 148 | #define AMD_SMB_STS_RES 0x20 |
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| 149 | #define AMD_SMB_STS_STATUS 0x1f |
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| 150 | |||
| 151 | #define AMD_SMB_STATUS_OK 0x00 |
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| 152 | #define AMD_SMB_STATUS_FAIL 0x07 |
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| 153 | #define AMD_SMB_STATUS_DNAK 0x10 |
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| 154 | #define AMD_SMB_STATUS_DERR 0x11 |
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| 155 | #define AMD_SMB_STATUS_CMD_DENY 0x12 |
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| 156 | #define AMD_SMB_STATUS_UNKNOWN 0x13 |
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| 157 | #define AMD_SMB_STATUS_ACC_DENY 0x17 |
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| 158 | #define AMD_SMB_STATUS_TIMEOUT 0x18 |
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| 159 | #define AMD_SMB_STATUS_NOTSUP 0x19 |
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| 160 | #define AMD_SMB_STATUS_BUSY 0x1A |
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| 161 | #define AMD_SMB_STATUS_PEC 0x1F |
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| 162 | |||
| 163 | #define AMD_SMB_PRTCL_WRITE 0x00 |
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| 164 | #define AMD_SMB_PRTCL_READ 0x01 |
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| 165 | #define AMD_SMB_PRTCL_QUICK 0x02 |
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| 166 | #define AMD_SMB_PRTCL_BYTE 0x04 |
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| 167 | #define AMD_SMB_PRTCL_BYTE_DATA 0x06 |
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| 168 | #define AMD_SMB_PRTCL_WORD_DATA 0x08 |
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| 169 | #define AMD_SMB_PRTCL_BLOCK_DATA 0x0a |
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| 170 | #define AMD_SMB_PRTCL_PROC_CALL 0x0c |
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| 171 | #define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d |
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| 172 | #define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a |
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| 173 | #define AMD_SMB_PRTCL_PEC 0x80 |
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| 174 | |||
| 175 | |||
| 176 | s32 amd8111_access(struct i2c_adapter * adap, u16 addr, unsigned short flags, |
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| 177 | char read_write, u8 command, int size, union i2c_smbus_data * data) |
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| 178 | { |
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| 179 | struct amd_smbus *smbus = adap->algo_data; |
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| 180 | unsigned char protocol, len, pec, temp[2]; |
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| 181 | int i; |
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| 182 | |||
| 183 | protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ : AMD_SMB_PRTCL_WRITE; |
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| 184 | pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0; |
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| 185 | |||
| 186 | switch (size) { |
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| 187 | |||
| 188 | case I2C_SMBUS_QUICK: |
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| 189 | protocol |= AMD_SMB_PRTCL_QUICK; |
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| 190 | read_write = I2C_SMBUS_WRITE; |
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| 191 | break; |
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| 192 | |||
| 193 | case I2C_SMBUS_BYTE: |
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| 194 | if (read_write == I2C_SMBUS_WRITE) |
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| 195 | amd_ec_write(smbus, AMD_SMB_DATA, data->byte); |
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| 196 | protocol |= AMD_SMB_PRTCL_BYTE; |
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| 197 | break; |
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| 198 | |||
| 199 | case I2C_SMBUS_BYTE_DATA: |
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| 200 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 201 | if (read_write == I2C_SMBUS_WRITE) |
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| 202 | amd_ec_write(smbus, AMD_SMB_DATA, data->byte); |
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| 203 | protocol |= AMD_SMB_PRTCL_BYTE_DATA; |
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| 204 | break; |
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| 205 | |||
| 206 | case I2C_SMBUS_WORD_DATA: |
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| 207 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 208 | if (read_write == I2C_SMBUS_WRITE) { |
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| 209 | amd_ec_write(smbus, AMD_SMB_DATA, data->word); |
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| 210 | amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8); |
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| 211 | } |
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| 212 | protocol |= AMD_SMB_PRTCL_WORD_DATA | pec; |
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| 213 | break; |
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| 214 | |||
| 215 | case I2C_SMBUS_BLOCK_DATA: |
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| 216 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 217 | if (read_write == I2C_SMBUS_WRITE) { |
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| 218 | len = min_t(u8, data->block[0], 32); |
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| 219 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
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| 220 | for (i = 0; i < len; i++) |
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| 221 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
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| 222 | } |
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| 223 | protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec; |
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| 224 | break; |
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| 225 | |||
| 226 | case I2C_SMBUS_I2C_BLOCK_DATA: |
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| 227 | len = min_t(u8, data->block[0], 32); |
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| 228 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 229 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
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| 230 | if (read_write == I2C_SMBUS_WRITE) |
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| 231 | for (i = 0; i < len; i++) |
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| 232 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
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| 233 | protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA; |
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| 234 | break; |
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| 235 | |||
| 236 | case I2C_SMBUS_PROC_CALL: |
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| 237 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 238 | amd_ec_write(smbus, AMD_SMB_DATA, data->word); |
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| 239 | amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8); |
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| 240 | protocol = AMD_SMB_PRTCL_PROC_CALL | pec; |
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| 241 | read_write = I2C_SMBUS_READ; |
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| 242 | break; |
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| 243 | |||
| 244 | case I2C_SMBUS_BLOCK_PROC_CALL: |
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| 245 | protocol |= pec; |
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| 246 | len = min_t(u8, data->block[0], 31); |
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| 247 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
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| 248 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
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| 249 | for (i = 0; i < len; i++) |
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| 250 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
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| 251 | protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec; |
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| 252 | read_write = I2C_SMBUS_READ; |
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| 253 | break; |
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| 254 | |||
| 255 | case I2C_SMBUS_WORD_DATA_PEC: |
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| 256 | case I2C_SMBUS_BLOCK_DATA_PEC: |
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| 257 | case I2C_SMBUS_PROC_CALL_PEC: |
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| 258 | case I2C_SMBUS_BLOCK_PROC_CALL_PEC: |
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| 259 | dev_warn(&adap->dev, "Unexpected software PEC transaction %d\n.", size); |
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| 260 | return -1; |
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| 261 | |||
| 262 | default: |
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| 263 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); |
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| 264 | return -1; |
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| 265 | } |
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| 266 | |||
| 267 | amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1); |
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| 268 | amd_ec_write(smbus, AMD_SMB_PRTCL, protocol); |
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| 269 | |||
| 270 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
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| 271 | |||
| 272 | if (~temp[0] & AMD_SMB_STS_DONE) { |
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| 273 | udelay(500); |
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| 274 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
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| 275 | } |
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| 276 | |||
| 277 | if (~temp[0] & AMD_SMB_STS_DONE) { |
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| 278 | i2c_delay(HZ/100); |
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| 279 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
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| 280 | } |
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| 281 | |||
| 282 | if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS)) |
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| 283 | return -1; |
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| 284 | |||
| 285 | if (read_write == I2C_SMBUS_WRITE) |
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| 286 | return 0; |
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| 287 | |||
| 288 | switch (size) { |
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| 289 | |||
| 290 | case I2C_SMBUS_BYTE: |
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| 291 | case I2C_SMBUS_BYTE_DATA: |
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| 292 | amd_ec_read(smbus, AMD_SMB_DATA, &data->byte); |
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| 293 | break; |
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| 294 | |||
| 295 | case I2C_SMBUS_WORD_DATA: |
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| 296 | case I2C_SMBUS_PROC_CALL: |
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| 297 | amd_ec_read(smbus, AMD_SMB_DATA, temp + 0); |
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| 298 | amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1); |
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| 299 | data->word = (temp[1] << 8) | temp[0]; |
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| 300 | break; |
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| 301 | |||
| 302 | case I2C_SMBUS_BLOCK_DATA: |
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| 303 | case I2C_SMBUS_BLOCK_PROC_CALL: |
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| 304 | amd_ec_read(smbus, AMD_SMB_BCNT, &len); |
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| 305 | len = min_t(u8, len, 32); |
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| 306 | case I2C_SMBUS_I2C_BLOCK_DATA: |
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| 307 | for (i = 0; i < len; i++) |
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| 308 | amd_ec_read(smbus, AMD_SMB_DATA + i, data->block + i + 1); |
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| 309 | data->block[0] = len; |
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| 310 | break; |
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| 311 | } |
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| 312 | |||
| 313 | return 0; |
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| 314 | } |
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| 315 | |||
| 316 | |||
| 317 | u32 amd8111_func(struct i2c_adapter *adapter) |
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| 318 | { |
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| 319 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | |
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| 320 | I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | |
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| 321 | I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | |
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| 322 | I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC; |
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| 323 | } |
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| 324 | |||
| 325 | static struct i2c_algorithm smbus_algorithm = { |
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| 326 | .name = "Non-I2C SMBus 2.0 adapter", |
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| 327 | .id = I2C_ALGO_SMBUS, |
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| 328 | .smbus_xfer = amd8111_access, |
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| 329 | .functionality = amd8111_func, |
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| 330 | }; |
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| 331 | |||
| 332 | |||
| 333 | static struct pci_device_id amd8111_ids[] = { |
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| 334 | { 0x1022, 0x746a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
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| 335 | { 0, } |
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| 336 | }; |
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| 337 | |||
| 338 | static int __devinit amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id) |
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| 339 | { |
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| 340 | struct amd_smbus *smbus; |
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| 341 | int error = -ENODEV; |
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| 342 | |||
| 343 | if (~pci_resource_flags(dev, 0) & IORESOURCE_IO) |
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| 344 | return -ENODEV; |
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| 345 | |||
| 346 | smbus = kmalloc(sizeof(struct amd_smbus), GFP_KERNEL); |
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| 347 | if (!smbus) |
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| 348 | return -ENOMEM; |
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| 349 | memset(smbus, 0, sizeof(struct amd_smbus)); |
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| 350 | |||
| 351 | smbus->dev = dev; |
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| 352 | smbus->base = pci_resource_start(dev, 0); |
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| 353 | smbus->size = pci_resource_len(dev, 0); |
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| 354 | |||
| 355 | if (!request_region(smbus->base, smbus->size, "amd8111 SMBus 2.0")) |
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| 356 | goto out_kfree; |
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| 357 | |||
| 358 | smbus->adapter.owner = THIS_MODULE; |
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| 359 | snprintf(smbus->adapter.name, I2C_NAME_SIZE, |
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| 360 | "SMBus2 AMD8111 adapter at %04x", smbus->base); |
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| 361 | smbus->adapter.class = I2C_ADAP_CLASS_SMBUS; |
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| 362 | smbus->adapter.algo = &smbus_algorithm; |
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| 363 | smbus->adapter.algo_data = smbus; |
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| 364 | |||
| 365 | /* set up the driverfs linkage to our parent device */ |
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| 366 | smbus->adapter.dev.parent = &dev->dev; |
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| 367 | |||
| 368 | error = i2c_add_adapter(&smbus->adapter); |
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| 369 | if (error) |
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| 370 | goto out_release_region; |
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| 371 | |||
| 372 | pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0); |
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| 373 | pci_set_drvdata(dev, smbus); |
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| 374 | return 0; |
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| 375 | |||
| 376 | out_release_region: |
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| 377 | release_region(smbus->base, smbus->size); |
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| 378 | out_kfree: |
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| 379 | kfree(smbus); |
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| 380 | return -1; |
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| 381 | } |
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| 382 | |||
| 383 | |||
| 384 | static void __devexit amd8111_remove(struct pci_dev *dev) |
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| 385 | { |
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| 386 | struct amd_smbus *smbus = pci_get_drvdata(dev); |
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| 387 | |||
| 388 | i2c_del_adapter(&smbus->adapter); |
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| 389 | release_region(smbus->base, smbus->size); |
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| 390 | kfree(smbus); |
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| 391 | } |
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| 392 | |||
| 393 | static struct pci_driver amd8111_driver = { |
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| 394 | .name = "amd8111 smbus 2", |
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| 395 | .id_table = amd8111_ids, |
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| 396 | .probe = amd8111_probe, |
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| 397 | .remove = __devexit_p(amd8111_remove), |
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| 398 | }; |
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| 399 | |||
| 400 | static int __init i2c_amd8111_init(void) |
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| 401 | { |
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| 402 | return pci_module_init(&amd8111_driver); |
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| 403 | } |
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| 404 | |||
| 405 | |||
| 406 | static void __exit i2c_amd8111_exit(void) |
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| 407 | { |
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| 408 | pci_unregister_driver(&amd8111_driver); |
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| 409 | } |
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| 410 | |||
| 411 | module_init(i2c_amd8111_init); |
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| 412 | module_exit(i2c_amd8111_exit); |