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/* ------------------------------------------------------------------------- */
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/* i2c-iop3xx.h algorithm driver definitions private to i2c-iop3xx.c         */
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/* ------------------------------------------------------------------------- */
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/*   Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
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 *                      <Peter dot Milne at D hyphen TACQ dot com>
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    This program is free software; you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation, version 2.
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    This program is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with this program; if not, write to the Free Software
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    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.                */
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/* ------------------------------------------------------------------------- */
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#ifndef I2C_IOP3XX_H
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#define I2C_IOP3XX_H 1
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/*
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 * iop321 hardware bit definitions
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 */
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#define IOP321_ICR_FAST_MODE    0x8000  /* 1=400kBps, 0=100kBps */
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#define IOP321_ICR_UNIT_RESET   0x4000  /* 1=RESET */
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#define IOP321_ICR_SADIE        0x2000  /* 1=Slave Detect Interrupt Enable */
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#define IOP321_ICR_ALDIE        0x1000  /* 1=Arb Loss Detect Interrupt Enable */
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#define IOP321_ICR_SSDIE        0x0800  /* 1=Slave STOP Detect Interrupt Enable */
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#define IOP321_ICR_BERRIE       0x0400  /* 1=Bus Error Interrupt Enable */
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#define IOP321_ICR_RXFULLIE     0x0200  /* 1=Receive Full Interrupt Enable */
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#define IOP321_ICR_TXEMPTYIE    0x0100  /* 1=Transmit Empty Interrupt Enable */
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#define IOP321_ICR_GCD          0x0080  /* 1=General Call Disable */
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/*
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 * IOP321_ICR_GCD: 1 disables response as slave. "This bit must be set
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 * when sending a master mode general call message from the I2C unit"
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 */
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#define IOP321_ICR_UE           0x0040  /* 1=Unit Enable */
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/*
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 * "NOTE: To avoid I2C bus integrity problems,
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 * the user needs to ensure that the GPIO Output Data Register -
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 * GPOD bits associated with an I2C port are cleared prior to setting
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 * the enable bit for that I2C serial port.
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 * The user prepares to enable I2C port 0 and
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 * I2C port 1 by clearing GPOD bits 7:6 and GPOD bits 5:4, respectively.
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 */
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#define IOP321_ICR_SCLEN        0x0020  /* 1=SCL enable for master mode */
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#define IOP321_ICR_MABORT       0x0010  /* 1=Send a STOP with no data
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                                         * NB TBYTE must be clear */
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#define IOP321_ICR_TBYTE        0x0008  /* 1=Send/Receive a byte. i2c clears */
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#define IOP321_ICR_NACK         0x0004  /* 1=reply with NACK */
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#define IOP321_ICR_MSTOP        0x0002  /* 1=send a STOP after next data byte */
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#define IOP321_ICR_MSTART       0x0001  /* 1=initiate a START */
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#define IOP321_ISR_BERRD        0x0400  /* 1=BUS ERROR Detected */
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#define IOP321_ISR_SAD          0x0200  /* 1=Slave ADdress Detected */
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#define IOP321_ISR_GCAD         0x0100  /* 1=General Call Address Detected */
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#define IOP321_ISR_RXFULL       0x0080  /* 1=Receive Full */
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#define IOP321_ISR_TXEMPTY      0x0040  /* 1=Transmit Empty */
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#define IOP321_ISR_ALD          0x0020  /* 1=Arbitration Loss Detected */
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#define IOP321_ISR_SSD          0x0010  /* 1=Slave STOP Detected */
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#define IOP321_ISR_BBUSY        0x0008  /* 1=Bus BUSY */
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#define IOP321_ISR_UNITBUSY     0x0004  /* 1=Unit Busy */
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#define IOP321_ISR_NACK         0x0002  /* 1=Unit Rx or Tx a NACK */
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#define IOP321_ISR_RXREAD       0x0001  /* 1=READ 0=WRITE (R/W bit of slave addr */
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#define IOP321_ISR_CLEARBITS    0x07f0
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#define IOP321_ISAR_SAMASK      0x007f
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#define IOP321_IDBR_MASK        0x00ff
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#define IOP321_IBMR_SCL         0x0002
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#define IOP321_IBMR_SDA         0x0001
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#define IOP321_GPOD_I2C0        0x00c0  /* clear these bits to enable ch0 */
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#define IOP321_GPOD_I2C1        0x0030  /* clear these bits to enable ch1 */
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#define MYSAR                   0x02    /* SWAG a suitable slave address */
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#define I2C_ERR                 321
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#define I2C_ERR_BERR            (I2C_ERR+0)
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#define I2C_ERR_ALD             (I2C_ERR+1)
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struct iop3xx_biu {                /* Bus Interface Unit - the hardware */
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/* physical hardware defs - regs*/
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        u32 *CR;
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        u32 *SR;
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        u32 *SAR;
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        u32 *DBR;
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        u32 *BMR;
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/* irq bit vector */
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        u32 irq;
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/* stored flags */
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        u32 SR_enabled, SR_received;
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};
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struct i2c_algo_iop3xx_data {
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        int channel;
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        wait_queue_head_t waitq;
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        spinlock_t lock;
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        int timeout;
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        struct iop3xx_biu* biu;
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};
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#define REGION_START(adap)      ((u32)((adap)->biu->CR))
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#define REGION_END(adap)        ((u32)((adap)->biu->BMR+1))
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#define REGION_LENGTH(adap)     (REGION_END(adap)-REGION_START(adap))
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#define IRQ_STATUS_MASK(adap)   (1<<adap->biu->irq)
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#endif /* I2C_IOP3XX_H */