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422 giacomo 1
/* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM
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 * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993
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 * derived from Data Sheet, Copyright Motorola 1984 (!).
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 * It was written to be part of the Linux operating system.
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 */
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/* permission is hereby granted to copy, modify and redistribute this code
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 * in terms of the GNU Library General Public License, Version 2 or later,
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 * at your option.
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 */
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#ifndef _MC146818RTC_H
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#define _MC146818RTC_H
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#include <asm/io.h>
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#include <linux/rtc.h>                  /* get the user-level API */
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#include <linux/spinlock.h>             /* spinlock_t */
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#include <asm/mc146818rtc.h>            /* register access macros */
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extern spinlock_t rtc_lock;             /* serialize CMOS RAM access */
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/**********************************************************************
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 * register summary
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 **********************************************************************/
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#define RTC_SECONDS             0
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#define RTC_SECONDS_ALARM       1
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#define RTC_MINUTES             2
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#define RTC_MINUTES_ALARM       3
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#define RTC_HOURS               4
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#define RTC_HOURS_ALARM         5
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/* RTC_*_alarm is always true if 2 MSBs are set */
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# define RTC_ALARM_DONT_CARE    0xC0
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#define RTC_DAY_OF_WEEK         6
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#define RTC_DAY_OF_MONTH        7
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#define RTC_MONTH               8
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#define RTC_YEAR                9
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/* control registers - Moto names
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 */
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#define RTC_REG_A               10
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#define RTC_REG_B               11
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#define RTC_REG_C               12
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#define RTC_REG_D               13
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/**********************************************************************
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 * register details
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 **********************************************************************/
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#define RTC_FREQ_SELECT RTC_REG_A
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/* update-in-progress  - set to "1" 244 microsecs before RTC goes off the bus,
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 * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete,
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 * totalling to a max high interval of 2.228 ms.
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 */
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# define RTC_UIP                0x80
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# define RTC_DIV_CTL            0x70
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   /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */
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#  define RTC_REF_CLCK_4MHZ     0x00
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#  define RTC_REF_CLCK_1MHZ     0x10
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#  define RTC_REF_CLCK_32KHZ    0x20
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   /* 2 values for divider stage reset, others for "testing purposes only" */
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#  define RTC_DIV_RESET1        0x60
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#  define RTC_DIV_RESET2        0x70
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  /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */
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# define RTC_RATE_SELECT        0x0F
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/**********************************************************************/
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#define RTC_CONTROL     RTC_REG_B
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# define RTC_SET 0x80           /* disable updates for clock setting */
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# define RTC_PIE 0x40           /* periodic interrupt enable */
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# define RTC_AIE 0x20           /* alarm interrupt enable */
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# define RTC_UIE 0x10           /* update-finished interrupt enable */
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# define RTC_SQWE 0x08          /* enable square-wave output */
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# define RTC_DM_BINARY 0x04     /* all time/date values are BCD if clear */
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# define RTC_24H 0x02           /* 24 hour mode - else hours bit 7 means pm */
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# define RTC_DST_EN 0x01        /* auto switch DST - works f. USA only */
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/**********************************************************************/
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#define RTC_INTR_FLAGS  RTC_REG_C
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/* caution - cleared by read */
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# define RTC_IRQF 0x80          /* any of the following 3 is active */
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# define RTC_PF 0x40
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# define RTC_AF 0x20
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# define RTC_UF 0x10
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/**********************************************************************/
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#define RTC_VALID       RTC_REG_D
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# define RTC_VRT 0x80           /* valid RAM and time */
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/**********************************************************************/
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#endif /* _MC146818RTC_H */