Rev 467 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 467 | giacomo | 1 | /* |
| 2 | * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer |
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| 3 | * |
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| 4 | * Copyright (c) 2000,2001 Ghozlane Toumi <gtoumi@messel.emse.fr> |
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| 5 | * |
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| 6 | * Created 28 Aug 2001 by Ghozlane Toumi |
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| 7 | */ |
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| 8 | |||
| 9 | |||
| 10 | #ifndef _SSTFB_H_ |
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| 11 | #define _SSTFB_H_ |
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| 12 | |||
| 13 | /* |
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| 14 | * |
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| 15 | * Debug Stuff |
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| 16 | * |
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| 17 | */ |
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| 18 | |||
| 19 | #ifdef SST_DEBUG |
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| 20 | # define dprintk(X...) printk("sstfb: " X) |
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| 21 | #else |
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| 22 | # define dprintk(X...) |
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| 23 | # undef SST_DEBUG_REG |
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| 24 | # undef SST_DEBUG_FUNC |
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| 25 | # undef SST_DEBUG_VAR |
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| 26 | #endif |
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| 27 | |||
| 28 | #if (SST_DEBUG_REG > 0) |
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| 29 | # define r_dprintk(X...) dprintk(X) |
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| 30 | #else |
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| 31 | # define r_dprintk(X...) |
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| 32 | #endif |
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| 33 | #if (SST_DEBUG_REG > 1) |
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| 34 | # define r_ddprintk(X...) dprintk(" " X) |
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| 35 | #else |
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| 36 | # define r_ddprintk(X...) |
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| 37 | #endif |
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| 38 | |||
| 39 | #if (SST_DEBUG_FUNC > 0) |
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| 40 | # define f_dprintk(X...) dprintk(X) |
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| 41 | #else |
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| 42 | # define f_dprintk(X...) |
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| 43 | #endif |
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| 44 | #if (SST_DEBUG_FUNC > 1) |
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| 45 | # define f_ddprintk(X...) dprintk(" " X) |
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| 46 | #else |
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| 47 | # define f_ddprintk(X...) |
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| 48 | #endif |
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| 49 | #if (SST_DEBUG_FUNC > 2) |
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| 50 | # define f_dddprintk(X...) dprintk(" " X) |
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| 51 | #else |
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| 52 | # define f_dddprintk(X...) |
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| 53 | #endif |
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| 54 | |||
| 55 | #if (SST_DEBUG_VAR > 0) |
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| 56 | # define v_dprintk(X...) dprintk(X) |
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| 57 | # define print_var(V, X...) \ |
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| 58 | { \ |
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| 59 | dprintk(X); \ |
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| 60 | printk(" :\n"); \ |
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| 61 | sst_dbg_print_var(V); \ |
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| 62 | } |
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| 63 | #else |
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| 64 | # define v_dprintk(X...) |
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| 65 | # define print_var(X,Y...) |
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| 66 | #endif |
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| 67 | |||
| 68 | #define eprintk(X...) printk(KERN_ERR "sstfb: " X) |
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| 69 | #define iprintk(X...) printk(KERN_INFO "sstfb: " X) |
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| 70 | #define wprintk(X...) printk(KERN_WARNING "sstfb: " X) |
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| 71 | |||
| 72 | #define BIT(x) (1ul<<(x)) |
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| 73 | #define POW2(x) (1ul<<(x)) |
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| 74 | |||
| 75 | #ifndef ABS |
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| 76 | # define ABS(x) (((x)<0)?-(x):(x)) |
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| 77 | #endif |
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| 78 | |||
| 79 | /* |
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| 80 | * |
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| 81 | * Const |
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| 82 | * |
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| 83 | */ |
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| 84 | |||
| 85 | /* pci stuff */ |
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| 86 | #define PCI_INIT_ENABLE 0x40 |
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| 87 | # define PCI_EN_INIT_WR BIT(0) |
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| 88 | # define PCI_EN_FIFO_WR BIT(1) |
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| 89 | # define PCI_REMAP_DAC BIT(2) |
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| 90 | #define PCI_VCLK_ENABLE 0xc0 /* enable video */ |
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| 91 | #define PCI_VCLK_DISABLE 0xe0 |
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| 92 | |||
| 93 | /* register offsets from memBaseAddr */ |
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| 94 | #define STATUS 0x0000 |
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| 95 | # define STATUS_FBI_BUSY BIT(7) |
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| 96 | #define FBZMODE 0x0110 |
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| 97 | # define EN_CLIPPING BIT(0) /* enable clipping */ |
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| 98 | # define EN_RGB_WRITE BIT(9) /* enable writes to rgb area */ |
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| 99 | # define EN_ALPHA_WRITE BIT(10) |
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| 100 | # define ENGINE_INVERT_Y BIT(17) /* invert Y origin (pipe) */ |
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| 101 | #define LFBMODE 0x0114 |
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| 102 | # define LFB_565 0 /* bits 3:0 .16 bits RGB */ |
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| 103 | # define LFB_888 4 /* 24 bits RGB */ |
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| 104 | # define LFB_8888 5 /* 32 bits ARGB */ |
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| 105 | # define WR_BUFF_FRONT 0 /* write buf select (front) */ |
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| 106 | # define WR_BUFF_BACK (1 << 4) /* back */ |
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| 107 | # define RD_BUFF_FRONT 0 /* read buff select (front) */ |
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| 108 | # define RD_BUFF_BACK (1 << 6) /* back */ |
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| 109 | # define EN_PXL_PIPELINE BIT(8) /* pixel pipeline (clip..)*/ |
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| 110 | # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */ |
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| 111 | # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */ |
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| 112 | # define LFB_INVERT_Y BIT(13) /* invert Y origin (LFB) */ |
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| 113 | # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */ |
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| 114 | # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */ |
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| 115 | #define CLIP_LEFT_RIGHT 0x0118 |
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| 116 | #define CLIP_LOWY_HIGHY 0x011c |
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| 117 | #define NOPCMD 0x0120 |
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| 118 | #define FASTFILLCMD 0x0124 |
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| 119 | #define SWAPBUFFCMD 0x0128 |
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| 120 | #define FBIINIT4 0x0200 /* misc controls */ |
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| 121 | # define FAST_PCI_READS 0 /* 1 waitstate */ |
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| 122 | # define SLOW_PCI_READS BIT(0) /* 2 ws */ |
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| 123 | # define LFB_READ_AHEAD BIT(1) |
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| 124 | #define BACKPORCH 0x0208 |
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| 125 | #define VIDEODIMENSIONS 0x020c |
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| 126 | #define FBIINIT0 0x0210 /* misc+fifo controls */ |
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| 127 | # define EN_VGA_PASSTHROUGH BIT(0) |
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| 128 | # define FBI_RESET BIT(1) |
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| 129 | # define FIFO_RESET BIT(2) |
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| 130 | #define FBIINIT1 0x0214 /* PCI + video controls */ |
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| 131 | # define VIDEO_MASK 0x8080010f /* masks video related bits V1+V2*/ |
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| 132 | # define FAST_PCI_WRITES 0 /* 0 ws */ |
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| 133 | # define SLOW_PCI_WRITES BIT(1) /* 1 ws */ |
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| 134 | # define EN_LFB_READ BIT(3) |
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| 135 | # define TILES_IN_X_SHIFT 4 |
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| 136 | # define VIDEO_RESET BIT(8) |
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| 137 | # define EN_BLANKING BIT(12) |
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| 138 | # define EN_DATA_OE BIT(13) |
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| 139 | # define EN_BLANK_OE BIT(14) |
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| 140 | # define EN_HVSYNC_OE BIT(15) |
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| 141 | # define EN_DCLK_OE BIT(16) |
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| 142 | # define SEL_INPUT_VCLK_2X 0 /* bit 17 */ |
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| 143 | # define SEL_INPUT_VCLK_SLAVE BIT(17) |
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| 144 | # define SEL_SOURCE_VCLK_SLAVE 0 /* bits 21:20 */ |
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| 145 | # define SEL_SOURCE_VCLK_2X_DIV2 (0x01 << 20) |
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| 146 | # define SEL_SOURCE_VCLK_2X_SEL (0x02 << 20) |
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| 147 | # define EN_24BPP BIT(22) |
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| 148 | # define TILES_IN_X_MSB_SHIFT 24 /* v2 */ |
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| 149 | # define VCLK_2X_SEL_DEL_SHIFT 27 /* vclk out delay 0,4,6,8ns */ |
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| 150 | # define VCLK_DEL_SHIFT 29 /* vclk in delay */ |
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| 151 | #define FBIINIT2 0x0218 /* Dram controls */ |
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| 152 | # define EN_FAST_RAS_READ BIT(5) |
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| 153 | # define EN_DRAM_OE BIT(6) |
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| 154 | # define EN_FAST_RD_AHEAD_WR BIT(7) |
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| 155 | # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */ |
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| 156 | # define SWAP_DACVSYNC 0 |
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| 157 | # define SWAP_DACDATA0 (1 << 9) |
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| 158 | # define SWAP_FIFO_STALL (2 << 9) |
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| 159 | # define EN_RD_AHEAD_FIFO BIT(21) |
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| 160 | # define EN_DRAM_REFRESH BIT(22) |
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| 161 | # define DRAM_REFRESH_16 (0x30 << 23) /* dram 16 ms */ |
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| 162 | #define DAC_READ FBIINIT2 /* in remap mode */ |
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| 163 | #define FBIINIT3 0x021c /* fbi controls */ |
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| 164 | # define DISABLE_TEXTURE BIT(6) |
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| 165 | # define Y_SWAP_ORIGIN_SHIFT 22 /* Y swap substraction value */ |
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| 166 | #define HSYNC 0x0220 |
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| 167 | #define VSYNC 0x0224 |
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| 168 | #define DAC_DATA 0x022c |
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| 169 | # define DAC_READ_CMD BIT(11) /* set read dacreg mode */ |
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| 170 | #define FBIINIT5 0x0244 /* v2 specific */ |
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| 171 | # define FBIINIT5_MASK 0xfa40ffff /* mask video bits*/ |
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| 172 | # define HDOUBLESCAN BIT(20) |
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| 173 | # define VDOUBLESCAN BIT(21) |
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| 174 | # define HSYNC_HIGH BIT(23) |
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| 175 | # define VSYNC_HIGH BIT(24) |
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| 176 | # define INTERLACE BIT(26) |
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| 177 | #define FBIINIT6 0x0248 /* v2 specific */ |
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| 178 | # define TILES_IN_X_LSB_SHIFT 30 /* v2 */ |
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| 179 | #define FBIINIT7 0x024c /* v2 specific */ |
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| 180 | |||
| 181 | #define BLTSRCBASEADDR 0x02c0 /* BitBLT Source base address */ |
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| 182 | #define BLTDSTBASEADDR 0x02c4 /* BitBLT Destination base address */ |
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| 183 | #define BLTXYSTRIDES 0x02c8 /* BitBLT Source and Destination strides */ |
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| 184 | #define BLTSRCCHROMARANGE 0x02cc /* BitBLT Source Chroma key range */ |
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| 185 | #define BLTDSTCHROMARANGE 0x02d0 /* BitBLT Destination Chroma key range */ |
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| 186 | #define BLTCLIPX 0x02d4 /* BitBLT Min/Max X clip values */ |
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| 187 | #define BLTCLIPY 0x02d8 /* BitBLT Min/Max Y clip values */ |
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| 188 | #define BLTSRCXY 0x02e0 /* BitBLT Source starting XY coordinates */ |
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| 189 | #define BLTDSTXY 0x02e4 /* BitBLT Destination starting XY coordinates */ |
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| 190 | #define BLTSIZE 0x02e8 /* BitBLT width and height */ |
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| 191 | #define BLTROP 0x02ec /* BitBLT Raster operations */ |
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| 192 | # define BLTROP_COPY 0x0cccc |
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| 193 | # define BLTROP_INVERT 0x05555 |
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| 194 | # define BLTROP_XOR 0x06666 |
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| 195 | #define BLTCOLOR 0x02f0 /* BitBLT and foreground background colors */ |
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| 196 | #define BLTCOMMAND 0x02f8 /* BitBLT command mode (v2 specific) */ |
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| 197 | # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */ |
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| 198 | # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */ |
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| 199 | # define BLT_RECFILL_BITBLT 2 /* BitBLT Rectangle Fill */ |
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| 200 | # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */ |
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| 201 | #define BLTDATA 0x02fc /* BitBLT data for CPU-to-Screen BitBLTs */ |
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| 202 | # define LAUNCH_BITBLT BIT(31) /* Launch BitBLT in BltCommand, bltDstXY or bltSize */ |
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| 203 | |||
| 204 | /* Dac Registers */ |
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| 205 | #define DACREG_WMA 0x0 /* pixel write mode address */ |
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| 206 | #define DACREG_LUT 0x01 /* color value */ |
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| 207 | #define DACREG_RMR 0x02 /* pixel mask */ |
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| 208 | #define DACREG_RMA 0x03 /* pixel read mode address */ |
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| 209 | /*Dac registers in indexed mode (TI, ATT dacs) */ |
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| 210 | #define DACREG_ADDR_I DACREG_WMA |
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| 211 | #define DACREG_DATA_I DACREG_RMR |
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| 212 | #define DACREG_RMR_I 0x00 |
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| 213 | #define DACREG_CR0_I 0x01 |
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| 214 | # define DACREG_CR0_EN_INDEXED BIT(0) /* enable indexec mode */ |
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| 215 | # define DACREG_CR0_8BIT BIT(1) /* set dac to 8 bits/read */ |
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| 216 | # define DACREG_CR0_PWDOWN BIT(3) /* powerdown dac */ |
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| 217 | # define DACREG_CR0_16BPP 0x30 /* mode 3 */ |
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| 218 | # define DACREG_CR0_24BPP 0x50 /* mode 5 */ |
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| 219 | #define DACREG_CR1_I 0x05 |
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| 220 | #define DACREG_CC_I 0x06 |
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| 221 | # define DACREG_CC_CLKA BIT(7) /* clk A controled by regs */ |
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| 222 | # define DACREG_CC_CLKA_C (2<<4) /* clk A uses reg C */ |
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| 223 | # define DACREG_CC_CLKB BIT(3) /* clk B controled by regs */ |
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| 224 | # define DACREG_CC_CLKB_D 3 /* clkB uses reg D */ |
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| 225 | #define DACREG_AC0_I 0x48 /* clock A reg C */ |
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| 226 | #define DACREG_AC1_I 0x49 |
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| 227 | #define DACREG_BD0_I 0x6c /* clock B reg D */ |
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| 228 | #define DACREG_BD1_I 0x6d |
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| 229 | |||
| 230 | /* identification constants */ |
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| 231 | #define DACREG_MIR_TI 0x97 |
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| 232 | #define DACREG_DIR_TI 0x09 |
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| 233 | #define DACREG_MIR_ATT 0x84 |
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| 234 | #define DACREG_DIR_ATT 0x09 |
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| 235 | /* ics dac specific registers */ |
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| 236 | #define DACREG_ICS_PLLWMA 0x04 /* PLL write mode address */ |
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| 237 | #define DACREG_ICS_PLLDATA 0x05 /* PLL data /parameter */ |
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| 238 | #define DACREG_ICS_CMD 0x06 /* command */ |
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| 239 | # define DACREG_ICS_CMD_16BPP 0x50 /* ics color mode 6 (16bpp bypass)*/ |
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| 240 | # define DACREG_ICS_CMD_24BPP 0x70 /* ics color mode 7 (24bpp bypass)*/ |
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| 241 | # define DACREG_ICS_CMD_PWDOWN BIT(0) /* powerdown dac */ |
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| 242 | #define DACREG_ICS_PLLRMA 0x07 /* PLL read mode address */ |
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| 243 | /* |
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| 244 | * pll parameter register: |
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| 245 | * indexed : write addr to PLLWMA, write data in PLLDATA. |
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| 246 | * for reads use PLLRMA . |
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| 247 | * 8 freq registers (0-7) for video clock (CLK0) |
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| 248 | * 2 freq registers (a-b) for graphic clock (CLK1) |
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| 249 | */ |
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| 250 | #define DACREG_ICS_PLL_CLK0_1_INI 0x55 /* initial pll M value for freq f1 */ |
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| 251 | #define DACREG_ICS_PLL_CLK0_7_INI 0x71 /* f7 */ |
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| 252 | #define DACREG_ICS_PLL_CLK1_B_INI 0x79 /* fb */ |
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| 253 | #define DACREG_ICS_PLL_CTRL 0x0e |
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| 254 | # define DACREG_ICS_CLK0 BIT(5) |
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| 255 | # define DACREG_ICS_CLK0_0 0 |
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| 256 | # define DACREG_ICS_CLK1_A 0 /* bit4 */ |
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| 257 | |||
| 258 | /* sst default init registers */ |
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| 259 | #define FBIINIT0_DEFAULT EN_VGA_PASSTHROUGH |
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| 260 | |||
| 261 | #define FBIINIT1_DEFAULT \ |
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| 262 | ( \ |
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| 263 | FAST_PCI_WRITES \ |
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| 264 | /* SLOW_PCI_WRITES*/ \ |
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| 265 | | VIDEO_RESET \ |
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| 266 | | 10 << TILES_IN_X_SHIFT\ |
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| 267 | | SEL_SOURCE_VCLK_2X_SEL\ |
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| 268 | | EN_LFB_READ \ |
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| 269 | ) |
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| 270 | |||
| 271 | #define FBIINIT2_DEFAULT \ |
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| 272 | ( \ |
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| 273 | SWAP_DACVSYNC \ |
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| 274 | | EN_DRAM_OE \ |
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| 275 | | DRAM_REFRESH_16 \ |
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| 276 | | EN_DRAM_REFRESH \ |
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| 277 | | EN_FAST_RAS_READ \ |
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| 278 | | EN_RD_AHEAD_FIFO \ |
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| 279 | | EN_FAST_RD_AHEAD_WR \ |
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| 280 | ) |
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| 281 | |||
| 282 | #define FBIINIT3_DEFAULT \ |
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| 283 | ( DISABLE_TEXTURE ) |
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| 284 | |||
| 285 | #define FBIINIT4_DEFAULT \ |
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| 286 | ( \ |
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| 287 | FAST_PCI_READS \ |
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| 288 | /* SLOW_PCI_READS*/ \ |
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| 289 | | LFB_READ_AHEAD \ |
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| 290 | ) |
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| 291 | /* Careful with this one : writing back the data just read will trash the DAC |
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| 292 | reading some fields give logic value on pins, but setting this field will |
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| 293 | set the source signal driving the pin. conclusion : just use the default |
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| 294 | as a base before writing back . |
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| 295 | */ |
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| 296 | #define FBIINIT6_DEFAULT (0x0) |
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| 297 | |||
| 298 | /* |
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| 299 | * |
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| 300 | * Misc Const |
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| 301 | * |
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| 302 | */ |
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| 303 | |||
| 304 | /* used to know witch clock to set */ |
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| 305 | enum { |
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| 306 | VID_CLOCK=0, |
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| 307 | GFX_CLOCK=1, |
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| 308 | }; |
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| 309 | |||
| 310 | /* freq max */ |
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| 311 | #define DAC_FREF 14318 /* DAC reference freq (Khz) */ |
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| 312 | #define VCO_MAX 260000 |
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| 313 | |||
| 314 | /* |
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| 315 | * driver structs |
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| 316 | */ |
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| 317 | |||
| 318 | struct pll_timing { |
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| 319 | unsigned int m; |
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| 320 | unsigned int n; |
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| 321 | unsigned int p; |
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| 322 | }; |
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| 323 | |||
| 324 | struct dac_switch { |
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| 325 | char * name; |
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| 326 | int (*detect) (struct fb_info *info); |
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| 327 | int (*set_pll) (struct fb_info *info, const struct pll_timing *t, const int clock); |
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| 328 | void (*set_vidmod) (struct fb_info *info, const int bpp); |
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| 329 | }; |
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| 330 | |||
| 331 | struct sst_spec { |
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| 332 | char * name; |
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| 333 | int default_gfx_clock; /* 50000 for voodoo1, 75000 for voodoo2 */ |
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| 334 | int max_gfxclk; /* ! in Mhz ie 60 for voodoo 1 */ |
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| 335 | }; |
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| 336 | |||
| 337 | struct sstfb_par { |
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| 338 | unsigned int yDim; |
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| 339 | unsigned int hSyncOn; /* hsync_len */ |
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| 340 | unsigned int hSyncOff; /* left_margin + xres + right_margin */ |
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| 341 | unsigned int hBackPorch;/* left_margin */ |
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| 342 | unsigned int vSyncOn; |
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| 343 | unsigned int vSyncOff; |
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| 344 | unsigned int vBackPorch; |
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| 345 | struct pll_timing pll; |
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| 346 | unsigned int tiles_in_X;/* num of tiles in X res */ |
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| 347 | unsigned long mmio_vbase; |
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| 348 | struct dac_switch dac_sw; /* dac specific functions */ |
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| 349 | struct pci_dev *dev; |
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| 350 | int type; |
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| 351 | u8 revision; |
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| 352 | int gfx_clock; /* status */ |
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| 353 | }; |
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| 354 | |||
| 355 | #endif /* _SSTFB_H_ */ |