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629 | giacomo | 1 | /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */ |
2 | /* |
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3 | Written 1996-1998 by Donald Becker. |
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4 | |||
5 | This software may be used and distributed according to the terms |
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6 | of the GNU Public License, incorporated herein by reference. |
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7 | |||
8 | This driver is for the 3Com "Vortex" and "Boomerang" series ethercards. |
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9 | Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597 |
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10 | and the EtherLink XL 3c900 and 3c905 cards. |
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11 | |||
12 | The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O |
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13 | Center of Excellence in Space Data and Information Sciences |
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14 | Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771 |
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15 | */ |
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16 | |||
17 | /* |
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18 | 15Apr00, Andrew Morton <andrewm@uow.edu.au> |
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19 | - Don't set RxComplete in boomerang interrupt enable reg |
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20 | - Added standard spinlocking. |
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21 | - Removed setting/clearing of dev->interrupt |
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22 | - Removed vp->in_interrupt |
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23 | - spinlock in vortex_timer to protect mdio functions |
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24 | - disable local interrupts around call to vortex_interrupt in |
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25 | vortex_tx_timeout() (So vortex_interrupt can use spin_lock()) |
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26 | - Removed global save/restore_flags() and cli() from get_stats |
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27 | and vortex_start_xmit() |
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28 | - Select window 3 in vortex_timer()'s write to Wn3_MAC_Ctrl |
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29 | - In vortex_start_xmit(), move the lock to _after_ we've altered |
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30 | vp->cur_tx and vp->tx_full. This defeats the race between |
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31 | vortex_start_xmit() and vortex_interrupt which was identified |
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32 | by Bogdan Costescu. |
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33 | - Merged back support for six new cards from various sources |
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34 | - Tell it that 3c905C has NWAY |
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35 | - Fix handling of SetStatusEnd in 'Too much work..' code, as |
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36 | per 2.3.99's 3c575_cb (Dave Hinds). Added vp->deferred for this. |
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37 | |||
38 | 24May00 <2.2.16-pre4> andrewm |
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39 | - Replace union wn3_config with BFINS/BFEXT manipulation for |
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40 | sparc64 (Pete Zaitcev, Peter Jones) |
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41 | - Use insl_ns/outsl_ns for __powerpc__ (Andreas Tobler) |
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42 | - In vortex_error, do_tx_reset and vortex_tx_timeout(Vortex): clear |
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43 | tbusy and force a BH rerun to better recover from errors. |
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44 | |||
45 | 24Jun00 <2.2.16> andrewm |
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46 | - Better handling of shared interrupts |
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47 | - Reset the transmitter in vortex_error() on both maxcollisions and Tx reclaim error |
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48 | - Split the ISR into vortex_interrupt and boomerang_interrupt. This is |
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49 | to fix once-and-for-all the dubious testing of vortex status bits on |
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50 | boomerang/hurricane/cyclone/tornado NICs. |
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51 | - Fixed crash under OOM during vortex_open() (Mark Hemment) |
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52 | - Fix Rx cessation problem during OOM (help from Mark Hemment) |
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53 | |||
54 | 01Aug00 <2.2.17-pre14> andrewm |
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55 | - Added 3c556 support (Fred Maciel) |
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56 | |||
57 | 16Aug00 <2.2.17-pre17> andrem |
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58 | - In vortex_error: don't reset the Tx after txReclaim or maxCollisions errors |
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59 | - In vortex_error(do_tx_reset): only reset dev->tbusy for vortex-style NICs. |
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60 | - In vortex_open(), set vp->tx_full to zero (else we get errors if the device was |
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61 | closed with a full Tx ring). |
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62 | |||
63 | 17Oct00 <2.2.18-pre16> andrewm |
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64 | - Added support for the 3c556B Laptop Hurricane (Louis Gerbarg) |
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65 | - Backported transceiver options handling from 2.4. This changes the semantics |
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66 | of forcing full duplex in the `options' parm! (It's better to use |
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67 | `full_duplex' anyway). See Documentation/vortex.txt (Maciej Rozycki). |
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68 | - Set PCI latency timer to maximum for the 3c590 (From Donald's driver) |
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69 | - Removed all the CARDBUS code (it's never used). |
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70 | - Added INVERT_MII_PWR, EEPROM_8BIT, EEPROM_OFFSET. Use them. |
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71 | - Use EEPROM_8BIT for the 3c555 |
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72 | - Merged ACPI WOL support from Donald's drivers. |
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73 | - Sort-of backported Donald's new medialock code. Called it duplexlock |
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74 | and we now prefer to use `full_duplex=[-1,0,1]' to force duplex mode. |
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75 | - Merged the rx_oom_timer from 2.4. This gives better handling of OOM |
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76 | conditions. Backed out the previous way of handling this. |
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77 | - Replace suser() with capable(CAP_NET_ADMIN) in ioctl(). |
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78 | |||
79 | 07Jan01 <2.2.19-pre6> andrewm |
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80 | - Add HAS_NWAY to "3c900 Cyclone 10Mbps TPO" |
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81 | - Added and used wait_for_completion(). 3c905CX problems. |
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82 | - Removed the code for older kernel versions. |
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83 | - Add HAS_NWAY to 3cSOHO100-TX (Brett Frankenberger) |
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84 | - Search for phy 24 first for 3c905CX. (D Becker) |
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85 | - Don't free skbs we don't own on oom path in vortex_open(). |
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86 | - Added explicit `medialock' flag so we can truly |
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87 | lock the media type down with `options'. |
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88 | - In vortex_error(), only reset the up/down load engine, not all the |
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89 | interface stuff. |
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90 | - Added and used EEPROM_NORESET for 3c556B PM resumes. |
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91 | - Enable WOL with the `enable_wol' module parm |
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92 | - Give the 3c980 HAS_NWAY |
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93 | |||
94 | - See http://www.uow.edu.au/~andrewm/linux/#3c59x-2.2 for more details. |
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95 | */ |
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96 | |||
97 | static char version[] = |
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98 | "3c59x.c 18Feb01 Donald Becker and others http://www.scyld.com/network/vortex.html\n"; |
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99 | |||
100 | /* "Knobs" that adjust features and parameters. */ |
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101 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. |
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102 | Setting to > 1512 effectively disables this feature. */ |
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103 | static const int rx_copybreak = 200; |
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104 | /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */ |
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105 | static const int mtu = 1500; |
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106 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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107 | static int max_interrupt_work = 20; |
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108 | |||
109 | /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */ |
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110 | //#define vortex_debug debug |
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111 | #ifdef VORTEX_DEBUG |
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112 | static int vortex_debug = VORTEX_DEBUG; |
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113 | #else |
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114 | static int vortex_debug = 0; |
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115 | #endif |
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116 | |||
117 | /* Some values here only for performance evaluation and path-coverage |
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118 | debugging. */ |
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119 | static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0, rx_csumhits; |
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120 | |||
121 | /* A few values that may be tweaked. */ |
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122 | /* Time in jiffies before concluding the transmitter is hung. */ |
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123 | #define TX_TIMEOUT ((400*HZ)/1000) |
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124 | |||
125 | /* Keep the ring sizes a power of two for efficiency. */ |
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126 | #define TX_RING_SIZE 16 |
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127 | #define RX_RING_SIZE 32 |
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128 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
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129 | |||
130 | #include <linux/config.h> |
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131 | #include <linux/version.h> |
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132 | #include <linux/kernel.h> |
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133 | #include <linux/sched.h> |
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134 | #include <linux/string.h> |
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135 | #include <linux/timer.h> |
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136 | #include <linux/errno.h> |
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137 | #include <linux/in.h> |
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138 | #include <linux/ioport.h> |
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139 | #include <linux/malloc.h> |
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140 | #include <linux/interrupt.h> |
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141 | #include <linux/pci.h> |
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142 | #include <linux/netdevice.h> |
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143 | #include <linux/etherdevice.h> |
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144 | #include <linux/skbuff.h> |
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145 | #include <linux/delay.h> |
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146 | #include <linux/module.h> |
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147 | #include <asm/irq.h> /* For NR_IRQS only. */ |
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148 | #include <asm/bitops.h> |
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149 | #include <asm/io.h> |
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150 | |||
151 | /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. |
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152 | This is only in the support-all-kernels source code. */ |
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153 | |||
154 | #define RUN_AT(x) (jiffies + (x)) |
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155 | |||
156 | |||
157 | MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); |
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158 | MODULE_DESCRIPTION("3Com 3c590/3c900 series Vortex/Boomerang driver"); |
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159 | MODULE_PARM(debug, "i"); |
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160 | MODULE_PARM(options, "1-" __MODULE_STRING(8) "i"); |
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161 | MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i"); |
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162 | MODULE_PARM(enable_wol, "1-" __MODULE_STRING(8) "i"); |
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163 | MODULE_PARM(rx_copybreak, "i"); |
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164 | MODULE_PARM(max_interrupt_work, "i"); |
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165 | MODULE_PARM(compaq_ioaddr, "i"); |
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166 | MODULE_PARM(compaq_irq, "i"); |
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167 | MODULE_PARM(compaq_device_id, "i"); |
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168 | |||
169 | /* Operational parameter that usually are not changed. */ |
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170 | |||
171 | /* The Vortex size is twice that of the original EtherLinkIII series: the |
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172 | runtime register window, window 1, is now always mapped in. |
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173 | The Boomerang size is twice as large as the Vortex -- it has additional |
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174 | bus master control registers. */ |
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175 | #define VORTEX_TOTAL_SIZE 0x20 |
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176 | #define BOOMERANG_TOTAL_SIZE 0x40 |
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177 | |||
178 | /* Set iff a MII transceiver on any interface requires mdio preamble. |
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179 | This only set with the original DP83840 on older 3c905 boards, so the extra |
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180 | code size of a per-interface flag is not worthwhile. */ |
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181 | static char mii_preamble_required = 0; |
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182 | |||
183 | /* |
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184 | Theory of Operation |
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185 | |||
186 | I. Board Compatibility |
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187 | |||
188 | This device driver is designed for the 3Com FastEtherLink and FastEtherLink |
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189 | XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs |
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190 | versions of the FastEtherLink cards. The supported product IDs are |
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191 | 3c590, 3c592, 3c595, 3c597, 3c900, 3c905 |
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192 | |||
193 | The related ISA 3c515 is supported with a separate driver, 3c515.c, included |
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194 | with the kernel source or available from |
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195 | cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html |
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196 | |||
197 | II. Board-specific settings |
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198 | |||
199 | PCI bus devices are configured by the system at boot time, so no jumpers |
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200 | need to be set on the board. The system BIOS should be set to assign the |
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201 | PCI INTA signal to an otherwise unused system IRQ line. |
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202 | |||
203 | The EEPROM settings for media type and forced-full-duplex are observed. |
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204 | The EEPROM media type should be left at the default "autoselect" unless using |
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205 | 10base2 or AUI connections which cannot be reliably detected. |
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206 | |||
207 | III. Driver operation |
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208 | |||
209 | The 3c59x series use an interface that's very similar to the previous 3c5x9 |
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210 | series. The primary interface is two programmed-I/O FIFOs, with an |
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211 | alternate single-contiguous-region bus-master transfer (see next). |
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212 | |||
213 | The 3c900 "Boomerang" series uses a full-bus-master interface with separate |
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214 | lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet, |
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215 | DEC Tulip and Intel Speedo3. The first chip version retains a compatible |
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216 | programmed-I/O interface that has been removed in 'B' and subsequent board |
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217 | revisions. |
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218 | |||
219 | One extension that is advertised in a very large font is that the adapters |
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220 | are capable of being bus masters. On the Vortex chip this capability was |
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221 | only for a single contiguous region making it far less useful than the full |
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222 | bus master capability. There is a significant performance impact of taking |
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223 | an extra interrupt or polling for the completion of each transfer, as well |
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224 | as difficulty sharing the single transfer engine between the transmit and |
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225 | receive threads. Using DMA transfers is a win only with large blocks or |
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226 | with the flawed versions of the Intel Orion motherboard PCI controller. |
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227 | |||
228 | The Boomerang chip's full-bus-master interface is useful, and has the |
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229 | currently-unused advantages over other similar chips that queued transmit |
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230 | packets may be reordered and receive buffer groups are associated with a |
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231 | single frame. |
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232 | |||
233 | With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme. |
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234 | Rather than a fixed intermediate receive buffer, this scheme allocates |
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235 | full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as |
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236 | the copying breakpoint: it is chosen to trade-off the memory wasted by |
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237 | passing the full-sized skbuff to the queue layer for all frames vs. the |
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238 | copying cost of copying a frame to a correctly-sized skbuff. |
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239 | |||
240 | |||
241 | IIIC. Synchronization |
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242 | The driver runs as two independent, single-threaded flows of control. One |
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243 | is the send-packet routine, which enforces single-threaded use by the |
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244 | dev->tbusy flag. The other thread is the interrupt handler, which is single |
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245 | threaded by the hardware and other software. |
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246 | |||
247 | IV. Notes |
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248 | |||
249 | Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development |
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250 | 3c590, 3c595, and 3c900 boards. |
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251 | The name "Vortex" is the internal 3Com project name for the PCI ASIC, and |
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252 | the EISA version is called "Demon". According to Terry these names come |
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253 | from rides at the local amusement park. |
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254 | |||
255 | The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes! |
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256 | This driver only supports ethernet packets because of the skbuff allocation |
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257 | limit of 4K. |
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258 | */ |
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259 | |||
260 | /* Added by Nino - Begin */ |
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261 | extern int pci20to26_find_class(unsigned int class_code, int index, BYTE *bus, BYTE *dev); |
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262 | extern int pci20to26_read_config_byte(unsigned int bus, unsigned int dev, int where, u8 *val); |
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263 | extern int pci20to26_read_config_word(unsigned int bus, unsigned int dev, int where, u16 *val); |
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264 | extern int pci20to26_read_config_dword(unsigned int bus, unsigned int dev, int where, u32 *val); |
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265 | extern int pci20to26_write_config_byte(unsigned int bus, unsigned int dev, int where, u8 val); |
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266 | extern int pci20to26_write_config_word(unsigned int bus, unsigned int dev, int where, u16 val); |
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267 | extern int pci20to26_write_config_dword(unsigned int bus, unsigned int dev, int where, u32 val); |
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268 | #ifndef CONFIG_PCI |
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269 | #define CONFIG_PCI |
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270 | #endif |
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271 | /* Added by Nino - End */ |
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272 | |||
273 | /* This table drives the PCI probe routines. It's mostly boilerplate in all |
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274 | of the drivers, and will likely be provided by some future kernel. |
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275 | */ |
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276 | enum pci_flags_bit { |
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277 | PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, |
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278 | PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3, |
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279 | }; |
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280 | struct pci_id_info { |
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281 | const char *name; |
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282 | u16 vendor_id, device_id, device_id_mask, flags; |
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283 | int drv_flags, io_size; |
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284 | struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev, |
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285 | long ioaddr, int irq, int chip_idx, int fnd_cnt); |
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286 | }; |
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287 | |||
288 | enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8, |
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289 | HAS_PWR_CTRL=0x10, HAS_MII=0x20, HAS_NWAY=0x40, HAS_CB_FNS=0x80, |
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290 | INVERT_MII_PWR=0x100, EEPROM_8BIT=0x200, EEPROM_OFFSET=0x400, |
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291 | EEPROM_NORESET=0x800}; |
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292 | static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
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293 | struct device *dev, long ioaddr, |
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294 | int irq, int dev_id, int card_idx); |
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295 | static struct pci_id_info pci_tbl[] = { |
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296 | {"3c590 Vortex 10Mbps", 0x10B7, 0x5900, 0xffff, |
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297 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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298 | {"3c592 EISA 10mbps Demon/Vortex", 0x10B7, 0x5920, 0xffff, /* AKPM: from Don's 3c59x_cb.c 0.49H */ |
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299 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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300 | {"3c597 EISA Fast Demon/Vortex", 0x10B7, 0x5970, 0xffff, /* AKPM: from Don's 3c59x_cb.c 0.49H */ |
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301 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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302 | {"3c595 Vortex 100baseTx", 0x10B7, 0x5950, 0xffff, |
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303 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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304 | {"3c595 Vortex 100baseT4", 0x10B7, 0x5951, 0xffff, |
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305 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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306 | {"3c595 Vortex 100base-MII", 0x10B7, 0x5952, 0xffff, |
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307 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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308 | |||
309 | #define EISA_TBL_OFFSET 6 /* AKPM: the offset of this entry */ |
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310 | {"3Com Vortex", 0x10B7, 0x5900, 0xff00, |
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311 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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312 | {"3c900 Boomerang 10baseT", 0x10B7, 0x9000, 0xffff, |
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313 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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314 | {"3c900 Boomerang 10Mbps Combo", 0x10B7, 0x9001, 0xffff, |
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315 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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316 | {"3c900 Cyclone 10Mbps Combo", 0x10B7, 0x9005, 0xffff, |
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317 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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318 | {"3c900B-FL Cyclone 10base-FL", 0x10B7, 0x900A, 0xffff, |
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319 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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320 | {"3c900 Cyclone 10Mbps TPO", 0x10B7, 0x9004, 0xffff, /* AKPM: from Don's 0.99M */ |
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321 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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322 | {"3c900 Cyclone 10Mbps TPC", 0x10B7, 0x9006, 0xffff, /* AKPM: from Don's 0.99M */ |
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323 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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324 | {"3c905 Boomerang 100baseTx", 0x10B7, 0x9050, 0xffff, |
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325 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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326 | {"3c905 Boomerang 100baseT4", 0x10B7, 0x9051, 0xffff, |
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327 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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1014 | pj | 328 | {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)", 0x10B7, 0x9202, 0xffff, |
329 | PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_MII, 128, vortex_probe1}, |
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629 | giacomo | 330 | {"3c905B Cyclone 100baseTx", 0x10B7, 0x9055, 0xffff, |
331 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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332 | {"3c905B Cyclone 10/100/BNC", 0x10B7, 0x9058, 0xffff, |
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333 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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334 | {"3c905B-FX Cyclone 100baseFx", 0x10B7, 0x905A, 0xffff, |
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335 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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336 | {"3c905C Tornado", 0x10B7, 0x9200, 0xffff, |
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337 | PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY, 128, vortex_probe1}, |
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338 | {"3c980 Cyclone", 0x10B7, 0x9800, 0xfff0, |
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339 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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340 | {"3cSOHO100-TX Hurricane", 0x10B7, 0x7646, 0xffff, |
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341 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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342 | {"3c555 Laptop Hurricane", 0x10B7, 0x5055, 0xffff, |
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343 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT, 128, vortex_probe1}, |
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344 | {"3c556 10/100 Mini PCI Adapter", 0x10B7, 0x6055, 0xffff, |
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345 | PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR, 128, vortex_probe1}, |
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346 | {"3c556B Laptop Hurricane", 0x10B7, 0x6056, 0xffff, |
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347 | PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|EEPROM_NORESET, 128, vortex_probe1}, |
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348 | {"3c575 Boomerang CardBus", 0x10B7, 0x5057, 0xffff, |
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349 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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350 | {"3CCFE575 Cyclone CardBus", 0x10B7, 0x5157, 0xffff, |
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351 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
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352 | 128, vortex_probe1}, |
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353 | {"3CCFE656 Cyclone CardBus", 0x10B7, 0x6560, 0xffff, |
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354 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
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355 | 128, vortex_probe1}, |
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356 | {"3CCFEM656 Cyclone CardBus", 0x10B7, 0x6562, 0xffff, /* AKPM: From the 2.3 driver ? */ |
||
357 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
||
358 | 128, vortex_probe1}, |
||
359 | {"3c575 series CardBus (unknown version)", 0x10B7, 0x5057, 0xf0ff, |
||
360 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
||
361 | {"3c450 HomePNA Tornado", 0x10B7, 0x4500, 0xffff, /* AKPM: from Don's 0.99P */ |
||
362 | PCI_USES_IO|PCI_USES_MASTER, IS_TORNADO|HAS_NWAY, 128, vortex_probe1}, |
||
363 | {"3Com Boomerang (unknown version)", 0x10B7, 0x9000, 0xff00, |
||
364 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
||
365 | {0,}, /* 0 terminated list. */ |
||
366 | }; |
||
367 | |||
368 | /* Operational definitions. |
||
369 | These are not used by other compilation units and thus are not |
||
370 | exported in a ".h" file. |
||
371 | |||
372 | First the windows. There are eight register windows, with the command |
||
373 | and status registers available in each. |
||
374 | */ |
||
375 | #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) |
||
376 | #define EL3_CMD 0x0e |
||
377 | #define EL3_STATUS 0x0e |
||
378 | |||
379 | /* The top five bits written to EL3_CMD are a command, the lower |
||
380 | 11 bits are the parameter, if applicable. |
||
381 | Note that 11 parameters bits was fine for ethernet, but the new chip |
||
382 | can handle FDDI length frames (~4500 octets) and now parameters count |
||
383 | 32-bit 'Dwords' rather than octets. */ |
||
384 | |||
385 | enum vortex_cmd { |
||
386 | TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, |
||
387 | RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, |
||
388 | UpStall = 6<<11, UpUnstall = (6<<11)+1, |
||
389 | DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, |
||
390 | RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, |
||
391 | FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, |
||
392 | SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, |
||
393 | SetTxThreshold = 18<<11, SetTxStart = 19<<11, |
||
394 | StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, |
||
395 | StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,}; |
||
396 | |||
397 | /* The SetRxFilter command accepts the following classes: */ |
||
398 | enum RxFilter { |
||
399 | RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }; |
||
400 | |||
401 | /* Bits in the general status register. */ |
||
402 | enum vortex_status { |
||
403 | IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, |
||
404 | TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, |
||
405 | IntReq = 0x0040, StatsFull = 0x0080, |
||
406 | DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, |
||
407 | DMAInProgress = 1<<11, /* DMA controller is still busy.*/ |
||
408 | CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/ |
||
409 | }; |
||
410 | |||
411 | /* Register window 1 offsets, the window used in normal operation. |
||
412 | On the Vortex this window is always mapped at offsets 0x10-0x1f. */ |
||
413 | enum Window1 { |
||
414 | TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, |
||
415 | RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B, |
||
416 | TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ |
||
417 | }; |
||
418 | enum Window0 { |
||
419 | Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ |
||
420 | Wn0EepromData = 12, /* Window 0: EEPROM results register. */ |
||
421 | IntrStatus=0x0E, /* Valid in all windows. */ |
||
422 | }; |
||
423 | enum Win0_EEPROM_bits { |
||
424 | EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, |
||
425 | EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ |
||
426 | EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ |
||
427 | }; |
||
428 | /* EEPROM locations. */ |
||
429 | enum eeprom_offset { |
||
430 | PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3, |
||
431 | EtherLink3ID=7, IFXcvrIO=8, IRQLine=9, |
||
432 | NodeAddr01=10, NodeAddr23=11, NodeAddr45=12, |
||
433 | DriverTune=13, Checksum=15}; |
||
434 | |||
435 | enum Window2 { /* Window 2. */ |
||
436 | Wn2_ResetOptions=12, |
||
437 | }; |
||
438 | enum Window3 { /* Window 3: MAC/config bits. */ |
||
439 | Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8, |
||
440 | }; |
||
441 | |||
442 | #define BFEXT(value, offset, bitcount) \ |
||
443 | ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1)) |
||
444 | |||
445 | #define BFINS(lhs, rhs, offset, bitcount) \ |
||
446 | (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \ |
||
447 | (((rhs) & ((1 << (bitcount)) - 1)) << (offset))) |
||
448 | |||
449 | #define RAM_SIZE(v) BFEXT(v, 0, 3) |
||
450 | #define RAM_WIDTH(v) BFEXT(v, 3, 1) |
||
451 | #define RAM_SPEED(v) BFEXT(v, 4, 2) |
||
452 | #define ROM_SIZE(v) BFEXT(v, 6, 2) |
||
453 | #define RAM_SPLIT(v) BFEXT(v, 16, 2) |
||
454 | #define XCVR(v) BFEXT(v, 20, 4) |
||
455 | #define AUTOSELECT(v) BFEXT(v, 24, 1) |
||
456 | |||
457 | enum Window4 { /* Window 4: Xcvr/media bits. */ |
||
458 | Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10, |
||
459 | }; |
||
460 | enum Win4_Media_bits { |
||
461 | Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ |
||
462 | Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ |
||
463 | Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ |
||
464 | Media_LnkBeat = 0x0800, |
||
465 | }; |
||
466 | enum Window7 { /* Window 7: Bus Master control. */ |
||
467 | Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12, |
||
468 | }; |
||
469 | /* Boomerang bus master control registers. */ |
||
470 | enum MasterCtrl { |
||
471 | PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, |
||
472 | TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38, |
||
473 | }; |
||
474 | |||
475 | /* The Rx and Tx descriptor lists. |
||
476 | Caution Alpha hackers: these types are 32 bits! Note also the 8 byte |
||
477 | alignment contraint on tx_ring[] and rx_ring[]. */ |
||
478 | #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ |
||
479 | struct boom_rx_desc { |
||
480 | u32 next; /* Last entry points to 0. */ |
||
481 | s32 status; |
||
482 | u32 addr; /* Up to 63 addr/len pairs possible. */ |
||
483 | s32 length; /* Set LAST_FRAG to indicate last pair. */ |
||
484 | }; |
||
485 | /* Values for the Rx status entry. */ |
||
486 | enum rx_desc_status { |
||
487 | RxDComplete=0x00008000, RxDError=0x4000, |
||
488 | /* See boomerang_rx() for actual error bits */ |
||
489 | IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27, |
||
490 | IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31, |
||
491 | }; |
||
492 | |||
493 | struct boom_tx_desc { |
||
494 | u32 next; /* Last entry points to 0. */ |
||
495 | s32 status; /* bits 0:12 length, others see below. */ |
||
496 | u32 addr; |
||
497 | s32 length; |
||
498 | }; |
||
499 | |||
500 | /* Values for the Tx status entry. */ |
||
501 | enum tx_desc_status { |
||
502 | CRCDisable=0x2000, TxDComplete=0x8000, |
||
503 | AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000, |
||
504 | TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */ |
||
505 | }; |
||
506 | |||
507 | /* Chip features we care about in vp->capabilities, read from the EEPROM. */ |
||
508 | enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 }; |
||
509 | |||
510 | struct vortex_private { |
||
511 | /* The Rx and Tx rings should be quad-word-aligned. */ |
||
512 | struct boom_rx_desc rx_ring[RX_RING_SIZE]; |
||
513 | struct boom_tx_desc tx_ring[TX_RING_SIZE]; |
||
514 | /* The addresses of transmit- and receive-in-place skbuffs. */ |
||
515 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
||
516 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; |
||
517 | struct device *next_module; |
||
518 | void *priv_addr; |
||
519 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ |
||
520 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ |
||
521 | struct net_device_stats stats; |
||
522 | struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ |
||
523 | |||
524 | /* PCI configuration space information. */ |
||
525 | u8 pci_bus, pci_devfn; /* PCI bus location, for power management. */ |
||
526 | char *cb_fn_base; /* CardBus function status addr space. */ |
||
527 | int chip_id; |
||
528 | |||
529 | /* The remainder are related to chip state, mostly media selection. */ |
||
530 | struct timer_list timer; /* Media selection timer. */ |
||
531 | struct timer_list rx_oom_timer; /* Rx skb allocation retry timer */ |
||
532 | int options; /* User-settable misc. driver options. */ |
||
533 | unsigned int media_override:4, /* Passed-in media type. */ |
||
534 | default_media:4, /* Read from the EEPROM/Wn3_Config. */ |
||
535 | full_duplex:1, /* User wants FD (or we're running at FD) */ |
||
536 | duplexlock:1, /* User has forced duplex */ |
||
537 | autoselect:1, /* Can use NWAY negotiation */ |
||
538 | bus_master:1, /* Vortex can only do a fragment bus-m. */ |
||
539 | full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */ |
||
540 | tx_full:1, |
||
541 | enable_wol:1, |
||
542 | medialock:1; |
||
543 | u16 status_enable; |
||
544 | u16 intr_enable; |
||
545 | u16 available_media; /* From Wn3_Options. */ |
||
546 | u16 capabilities, info1, info2; /* Various, from EEPROM. */ |
||
547 | u16 advertising; /* NWay media advertisement */ |
||
548 | unsigned char phys[2]; /* MII device addresses. */ |
||
549 | u16 deferred; /* Resend these interrupts when we |
||
550 | * bale from the ISR */ |
||
551 | spinlock_t lock; |
||
552 | }; |
||
553 | |||
554 | /* The action to take with a media selection timer tick. |
||
555 | Note that we deviate from the 3Com order by checking 10base2 before AUI. |
||
556 | */ |
||
557 | enum xcvr_types { |
||
558 | XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, |
||
559 | XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10, |
||
560 | }; |
||
561 | |||
562 | static struct media_table { |
||
563 | char *name; |
||
564 | unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ |
||
565 | mask:8, /* The transceiver-present bit in Wn3_Config.*/ |
||
566 | next:8; /* The media type to try next. */ |
||
567 | int wait; /* Time before we check media status. */ |
||
568 | } media_tbl[] = { |
||
569 | { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10}, |
||
570 | { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10}, |
||
571 | { "undefined", 0, 0x80, XCVR_10baseT, 10000}, |
||
572 | { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10}, |
||
573 | { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10}, |
||
574 | { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10}, |
||
575 | { "MII", 0, 0x41, XCVR_10baseT, 3*HZ }, |
||
576 | { "undefined", 0, 0x01, XCVR_10baseT, 10000}, |
||
577 | { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ}, |
||
578 | { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ }, |
||
579 | { "Default", 0, 0xFF, XCVR_10baseT, 10000}, |
||
580 | }; |
||
581 | |||
582 | static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]); |
||
583 | static int vortex_open(struct device *dev); |
||
584 | static void mdio_sync(long ioaddr, int bits); |
||
585 | static int mdio_read(long ioaddr, int phy_id, int location); |
||
586 | static void mdio_write(long ioaddr, int phy_id, int location, int value); |
||
587 | static void vortex_timer(unsigned long arg); |
||
588 | static void rx_oom_timer(unsigned long arg); |
||
589 | static int vortex_start_xmit(struct sk_buff *skb, struct device *dev); |
||
590 | static int boomerang_start_xmit(struct sk_buff *skb, struct device *dev); |
||
591 | static int vortex_rx(struct device *dev); |
||
592 | static int boomerang_rx(struct device *dev); |
||
593 | static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs); |
||
594 | static void boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs); |
||
595 | static int vortex_close(struct device *dev); |
||
596 | static void update_stats(long ioaddr, struct device *dev); |
||
597 | static struct net_device_stats *vortex_get_stats(struct device *dev); |
||
598 | static void set_rx_mode(struct device *dev); |
||
599 | static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd); |
||
600 | static void acpi_wake(int pci_bus, int pci_devfn); |
||
601 | static void acpi_set_WOL(struct device *dev); |
||
602 | |||
603 | |||
604 | #if 0 |
||
605 | #warning dev_alloc_skb_debug is defined! |
||
606 | #define dev_alloc_skb dev_alloc_skb_debug |
||
607 | #endif |
||
608 | |||
609 | /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ |
||
610 | /* Option count limit only -- unlimited interfaces are supported. */ |
||
611 | #define MAX_UNITS 8 |
||
612 | static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1}; |
||
613 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
||
614 | static int enable_wol[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
||
615 | /* A list of all installed Vortex devices, for removing the driver module. */ |
||
616 | static struct device *root_vortex_dev = NULL; |
||
617 | |||
618 | #ifdef MODULE |
||
619 | /* Variables to work-around the Compaq PCI BIOS32 problem. */ |
||
620 | static int compaq_ioaddr = 0, compaq_irq = 0, compaq_device_id = 0x5900; |
||
621 | |||
622 | int init_module(void) |
||
623 | { |
||
624 | if (vortex_debug) |
||
625 | printk(KERN_INFO "%s", version); |
||
626 | return vortex_scan(0, pci_tbl); |
||
627 | } |
||
628 | |||
629 | #else |
||
630 | int tc59x_probe(struct device *dev) |
||
631 | { |
||
632 | static int scanned=0; |
||
633 | if(scanned++) |
||
634 | return -ENODEV; |
||
635 | //printk(KERN_INFO "%s", version); |
||
636 | return vortex_scan(dev, pci_tbl); |
||
637 | } |
||
638 | #endif /* not MODULE */ |
||
639 | |||
640 | static void wait_for_completion(struct device *dev, int cmd) |
||
641 | { |
||
642 | int i; |
||
643 | |||
644 | outw(cmd, dev->base_addr + EL3_CMD); |
||
645 | for (i = 0; i < 2000; i++) { |
||
646 | if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) |
||
647 | return; |
||
648 | } |
||
649 | |||
650 | /* OK, that didn't work. Do it the slow way. One second */ |
||
651 | for (i = 0; i < 100000; i++) { |
||
652 | if (!(inw(dev->base_addr + EL3_STATUS) & CmdInProgress)) { |
||
653 | if (vortex_debug > 1) |
||
654 | printk(KERN_INFO "%s: command 0x%04x took %d usecs!\n", |
||
655 | dev->name, cmd, i * 10); |
||
656 | return; |
||
657 | } |
||
658 | udelay(10); |
||
659 | } |
||
660 | printk(KERN_ERR "%s: command 0x%04x did not complete! Status=0x%x\n", |
||
661 | dev->name, cmd, inw(dev->base_addr + EL3_STATUS)); |
||
662 | } |
||
663 | |||
664 | static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]) |
||
665 | { |
||
666 | int cards_found = 0; |
||
667 | |||
668 | /* Allow an EISA-only driver. */ |
||
669 | #if defined(CONFIG_PCI) || (defined(MODULE) && !defined(NO_PCI)) |
||
670 | /* Ideally we would detect all cards in slot order. That would |
||
671 | be best done a central PCI probe dispatch, which wouldn't work |
||
672 | well with the current structure. So instead we detect 3Com cards |
||
673 | in slot order. */ |
||
674 | if (pcibios_present()) { |
||
675 | static int pci_index = 0; |
||
676 | unsigned char pci_bus, pci_device_fn; |
||
677 | |||
678 | for (;pci_index < 0xff; pci_index++) { |
||
679 | u16 vendor, device, pci_command, new_command, pwr_cmd; |
||
680 | int chip_idx, irq; |
||
681 | long ioaddr; |
||
682 | |||
683 | if (pci20to26_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index, |
||
684 | &pci_bus, &pci_device_fn) != PCIBIOS_SUCCESSFUL) |
||
685 | break; |
||
686 | pci20to26_read_config_word(pci_bus, pci_device_fn, |
||
687 | PCI_VENDOR_ID, &vendor); |
||
688 | pci20to26_read_config_word(pci_bus, pci_device_fn, |
||
689 | PCI_DEVICE_ID, &device); |
||
690 | for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) |
||
691 | if (vendor == pci_tbl[chip_idx].vendor_id |
||
692 | && (device & pci_tbl[chip_idx].device_id_mask) == |
||
693 | pci_tbl[chip_idx].device_id) |
||
694 | break; |
||
695 | if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */ |
||
696 | continue; |
||
697 | |||
698 | /* The Cyclone requires config space re-write if powered down. */ |
||
699 | acpi_wake(pci_bus, pci_device_fn); |
||
700 | |||
701 | { |
||
702 | #if 0 //defined(PCI_SUPPORT_VER2) |
||
703 | struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn); |
||
704 | ioaddr = pdev->base_address[0] & ~3; |
||
705 | irq = pdev->irq; |
||
706 | #else |
||
707 | u32 pci_ioaddr; |
||
708 | u8 pci_irq_line; |
||
709 | pci20to26_read_config_byte(pci_bus, pci_device_fn, |
||
710 | PCI_INTERRUPT_LINE, &pci_irq_line); |
||
711 | pci20to26_read_config_dword(pci_bus, pci_device_fn, |
||
712 | PCI_BASE_ADDRESS_0, &pci_ioaddr); |
||
713 | ioaddr = pci_ioaddr & ~3; |
||
714 | irq = pci_irq_line; |
||
715 | #endif |
||
716 | } |
||
717 | |||
718 | /* Power-up the card. */ |
||
719 | pci20to26_read_config_word(pci_bus, pci_device_fn, |
||
720 | 0xe0, &pwr_cmd); |
||
721 | if (pwr_cmd & 0x3) { |
||
722 | /* Save the ioaddr and IRQ info! */ |
||
723 | printk(KERN_INFO " A 3Com network adapter is powered down!" |
||
724 | " Setting the power state %4.4x->%4.4x.\n", |
||
725 | pwr_cmd, pwr_cmd & ~3); |
||
726 | pci20to26_write_config_word(pci_bus, pci_device_fn, |
||
727 | 0xe0, pwr_cmd & ~3); |
||
728 | printk(KERN_INFO " Setting the IRQ to %d, IOADDR to %#lx.\n", |
||
729 | irq, ioaddr); |
||
730 | pci20to26_write_config_byte(pci_bus, pci_device_fn, |
||
731 | PCI_INTERRUPT_LINE, irq); |
||
732 | pci20to26_write_config_dword(pci_bus, pci_device_fn, |
||
733 | PCI_BASE_ADDRESS_0, ioaddr); |
||
734 | } |
||
735 | |||
736 | if (ioaddr == 0) { |
||
737 | printk(KERN_WARNING " A 3Com network adapter has been found, " |
||
738 | "however it has not been assigned an I/O address.\n" |
||
739 | " You may need to power-cycle the machine for this " |
||
740 | "device to work!\n"); |
||
741 | continue; |
||
742 | } |
||
743 | |||
744 | if (check_region(ioaddr, pci_tbl[chip_idx].io_size)) |
||
745 | continue; |
||
746 | |||
747 | /* Activate the card. */ |
||
748 | pci20to26_read_config_word(pci_bus, pci_device_fn, |
||
749 | PCI_COMMAND, &pci_command); |
||
750 | new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO; |
||
751 | if (pci_command != new_command) { |
||
752 | printk(KERN_INFO " The PCI BIOS has not enabled the device " |
||
753 | "at %d/%d. Updating PCI command %4.4x->%4.4x.\n", |
||
754 | pci_bus, pci_device_fn, pci_command, new_command); |
||
755 | pci20to26_write_config_word(pci_bus, pci_device_fn, |
||
756 | PCI_COMMAND, new_command); |
||
757 | } |
||
758 | |||
759 | dev = vortex_probe1(pci_bus, pci_device_fn, dev, ioaddr, irq, |
||
760 | chip_idx, cards_found); |
||
761 | |||
762 | if (dev) { |
||
763 | if ((device & 0xff00) == 0x5900) { |
||
764 | /* Get and check the latency values. On the 3c590 series |
||
765 | the latency timer must be set to the maximum value to avoid |
||
766 | data corruption that occurs when the timer expires during |
||
767 | a transfer -- a bug in the Vortex chip only. */ |
||
768 | u8 pci_latency; |
||
769 | u8 new_latency = 248; |
||
770 | |||
771 | pci20to26_read_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, &pci_latency); |
||
772 | if (pci_latency < new_latency) { |
||
773 | printk(KERN_INFO "%s: Overriding PCI latency" |
||
774 | " timer (CFLT) setting of %d, new value is %d.\n", |
||
775 | dev->name, pci_latency, new_latency); |
||
776 | pci20to26_write_config_byte(pci_bus, pci_device_fn, PCI_LATENCY_TIMER, new_latency); |
||
777 | } |
||
778 | } |
||
779 | dev = 0; |
||
780 | cards_found++; |
||
781 | } |
||
782 | } |
||
783 | } |
||
784 | #endif /* NO_PCI */ |
||
785 | |||
786 | /* Now check all slots of the EISA bus. */ |
||
787 | if (EISA_bus) { |
||
788 | static long ioaddr = 0x1000; |
||
789 | for ( ; ioaddr < 0x9000; ioaddr += 0x1000) { |
||
790 | int device_id; |
||
791 | if (check_region(ioaddr, VORTEX_TOTAL_SIZE)) |
||
792 | continue; |
||
793 | /* Check the standard EISA ID register for an encoded '3Com'. */ |
||
794 | if (inw(ioaddr + 0xC80) != 0x6d50) |
||
795 | continue; |
||
796 | /* Check for a product that we support, 3c59{2,7} any rev. */ |
||
797 | device_id = (inb(ioaddr + 0xC82)<<8) + inb(ioaddr + 0xC83); |
||
798 | if ((device_id & 0xFF00) != 0x5900) |
||
799 | continue; |
||
800 | vortex_probe1(0, 0, dev, ioaddr, inw(ioaddr + 0xC88) >> 12, |
||
801 | EISA_TBL_OFFSET, cards_found); |
||
802 | dev = 0; |
||
803 | cards_found++; |
||
804 | } |
||
805 | } |
||
806 | |||
807 | #ifdef MODULE |
||
808 | /* Special code to work-around the Compaq PCI BIOS32 problem. */ |
||
809 | if (compaq_ioaddr) { |
||
810 | vortex_probe1(0, 0, dev, compaq_ioaddr, compaq_irq, |
||
811 | compaq_device_id, cards_found++); |
||
812 | dev = 0; |
||
813 | } |
||
814 | #endif |
||
815 | |||
816 | return cards_found ? 0 : -ENODEV; |
||
817 | } |
||
818 | |||
819 | static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
||
820 | struct device *dev, long ioaddr, |
||
821 | int irq, int chip_idx, int card_idx) |
||
822 | { |
||
823 | struct vortex_private *vp; |
||
824 | int option; |
||
825 | unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ |
||
826 | int i; |
||
827 | |||
828 | dev = init_etherdev(dev, 0); |
||
829 | if (dev == NULL) { |
||
830 | printk(KERN_EMERG "3c59x: init_etherdev failed\n"); |
||
831 | return NULL; |
||
832 | } |
||
833 | |||
834 | printk(KERN_INFO "%s: 3Com %s at 0x%lx, ", |
||
835 | dev->name, pci_tbl[chip_idx].name, ioaddr); |
||
836 | |||
837 | dev->base_addr = ioaddr; |
||
838 | dev->irq = irq; |
||
839 | dev->mtu = mtu; |
||
840 | |||
841 | /* Make certain the descriptor lists are aligned. */ |
||
842 | { |
||
843 | void *mem = kmalloc(sizeof(*vp) + 15, GFP_KERNEL); |
||
844 | if (!mem) { |
||
845 | printk(KERN_EMERG "3c59x: out of memory for dev->priv\n"); |
||
846 | unregister_netdev(dev); |
||
847 | kfree(dev); |
||
848 | return NULL; |
||
849 | } |
||
850 | vp = (void *)(((long)mem + 15) & ~15); |
||
851 | memset(vp, 0, sizeof(*vp)); |
||
852 | vp->priv_addr = mem; |
||
853 | } |
||
854 | dev->priv = vp; |
||
855 | |||
856 | vp->next_module = root_vortex_dev; |
||
857 | root_vortex_dev = dev; |
||
858 | |||
859 | spin_lock_init(&vp->lock); |
||
860 | vp->chip_id = chip_idx; |
||
861 | vp->pci_bus = pci_bus; |
||
862 | vp->pci_devfn = pci_devfn; |
||
863 | |||
864 | /* The lower four bits are the media type. */ |
||
865 | option = -1; |
||
866 | if (dev->mem_start) |
||
867 | option = dev->mem_start; |
||
868 | else if (card_idx < MAX_UNITS) |
||
869 | option = options[card_idx]; |
||
870 | |||
871 | if (option >= 0) { |
||
872 | vp->media_override = ((option & 7) == 2) ? 0 : option & 15; |
||
873 | if (vp->media_override != 7) |
||
874 | vp->medialock = 1; |
||
875 | if (option & 0x200) { |
||
876 | vp->full_duplex = 1; |
||
877 | vp->duplexlock = 1; |
||
878 | printk( "\n" KERN_WARNING |
||
879 | "%s: forcing duplex via options is deprecated - use `full_duplex'.\n", |
||
880 | dev->name); |
||
881 | } |
||
882 | vp->bus_master = (option & 16) ? 1 : 0; |
||
883 | } else { |
||
884 | vp->media_override = 7; |
||
885 | vp->full_duplex = 0; |
||
886 | vp->bus_master = 0; |
||
887 | } |
||
888 | if (card_idx < MAX_UNITS) { |
||
889 | if (enable_wol[card_idx] > 0) |
||
890 | vp->enable_wol = 1; |
||
891 | if (full_duplex[card_idx] == 0) { /* full_duplex=0 : force half duplex */ |
||
892 | vp->duplexlock = 1; |
||
893 | } |
||
894 | if (full_duplex[card_idx] > 0) { /* full_duplex=1: force full duplex */ |
||
895 | vp->duplexlock = 1; |
||
896 | vp->full_duplex = 1; |
||
897 | } |
||
898 | /* full_duplex=-1: duplex is not forced */ |
||
899 | } |
||
900 | vp->options = option; |
||
901 | |||
902 | /* Read the station address from the EEPROM. */ |
||
903 | EL3WINDOW(0); |
||
904 | { |
||
905 | int base; |
||
906 | |||
907 | if (pci_tbl[chip_idx].drv_flags & EEPROM_8BIT) |
||
908 | base = 0x230; |
||
909 | else if (pci_tbl[chip_idx].drv_flags & EEPROM_OFFSET) |
||
910 | base = EEPROM_Read + 0x30; |
||
911 | else |
||
912 | base = EEPROM_Read; |
||
913 | |||
914 | for (i = 0; i < 0x40; i++) { |
||
915 | int timer; |
||
916 | outw(base + i, ioaddr + Wn0EepromCmd); |
||
917 | /* Pause for at least 162 us. for the read to take place. */ |
||
918 | for (timer = 10; timer >= 0; timer--) { |
||
919 | udelay(162); |
||
920 | if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0) |
||
921 | break; |
||
922 | } |
||
923 | eeprom[i] = inw(ioaddr + Wn0EepromData); |
||
924 | } |
||
925 | } |
||
926 | |||
927 | for (i = 0; i < 0x18; i++) |
||
928 | checksum ^= eeprom[i]; |
||
929 | checksum = (checksum ^ (checksum >> 8)) & 0xff; |
||
930 | if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ |
||
931 | while (i < 0x21) |
||
932 | checksum ^= eeprom[i++]; |
||
933 | checksum = (checksum ^ (checksum >> 8)) & 0xff; |
||
934 | } |
||
935 | if (checksum != 0x00 && !(pci_tbl[chip_idx].drv_flags & IS_TORNADO)) |
||
936 | printk(" ***INVALID CHECKSUM %4.4x*** ", checksum); |
||
937 | |||
938 | for (i = 0; i < 3; i++) |
||
939 | ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]); |
||
940 | for (i = 0; i < 6; i++) |
||
941 | printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]); |
||
942 | #ifdef __sparc__ |
||
943 | printk(", IRQ %s\n", __irq_itoa(dev->irq)); |
||
944 | #else |
||
945 | printk(", IRQ %d\n", dev->irq); |
||
946 | /* Tell them about an invalid IRQ. */ |
||
947 | if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS)) |
||
948 | printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n", |
||
949 | dev->irq); |
||
950 | #endif |
||
951 | |||
952 | if (pci_tbl[vp->chip_id].drv_flags & HAS_CB_FNS) { |
||
953 | u32 fn_st_addr; /* Cardbus function status space */ |
||
954 | u16 n; |
||
955 | pci20to26_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_2, |
||
956 | &fn_st_addr); |
||
957 | if (fn_st_addr) |
||
958 | vp->cb_fn_base = ioremap(fn_st_addr & ~3, 128); |
||
959 | printk("%s: CardBus functions mapped %8.8x->%p (PCMCIA committee" |
||
960 | " brain-damage).\n", dev->name, fn_st_addr, vp->cb_fn_base); |
||
961 | EL3WINDOW(2); |
||
962 | |||
963 | n = inw(ioaddr + Wn2_ResetOptions) & ~0x4010; |
||
964 | n |= 0x10; |
||
965 | if (pci_tbl[chip_idx].drv_flags & INVERT_MII_PWR) |
||
966 | n |= 0x4000; |
||
967 | outw(n, ioaddr + Wn2_ResetOptions); |
||
968 | } |
||
969 | |||
970 | /* Extract our information from the EEPROM data. */ |
||
971 | vp->info1 = eeprom[13]; |
||
972 | vp->info2 = eeprom[15]; |
||
973 | vp->capabilities = eeprom[16]; |
||
974 | |||
975 | if (!vp->duplexlock && (vp->info1 & 0x8000)) |
||
976 | vp->full_duplex = 1; |
||
977 | |||
978 | { |
||
979 | char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; |
||
980 | unsigned int config; |
||
981 | EL3WINDOW(3); |
||
982 | vp->available_media = inw(ioaddr + Wn3_Options); |
||
983 | if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ |
||
984 | vp->available_media = 0x40; |
||
985 | config = inl(ioaddr + Wn3_Config); |
||
986 | if (vortex_debug > 1) |
||
987 | printk(KERN_DEBUG " Internal config register is %4.4x, " |
||
988 | "transceivers %#x.\n", config, inw(ioaddr + Wn3_Options)); |
||
989 | printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", |
||
990 | 8 << RAM_SIZE(config), |
||
991 | RAM_WIDTH(config) ? "word" : "byte", |
||
992 | ram_split[RAM_SPLIT(config)], |
||
993 | AUTOSELECT(config) ? "autoselect/" : "", |
||
994 | XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" : |
||
995 | media_tbl[XCVR(config)].name); |
||
996 | vp->default_media = XCVR(config); |
||
997 | vp->autoselect = AUTOSELECT(config); |
||
998 | } |
||
999 | |||
1000 | if (vp->media_override != 7) { |
||
1001 | printk(KERN_INFO " Media override to transceiver type %d (%s).\n", |
||
1002 | vp->media_override, media_tbl[vp->media_override].name); |
||
1003 | dev->if_port = vp->media_override; |
||
1004 | } else |
||
1005 | dev->if_port = vp->default_media; |
||
1006 | |||
1007 | if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
||
1008 | int phy, phy_idx = 0; |
||
1009 | EL3WINDOW(4); |
||
1010 | mii_preamble_required++; |
||
1011 | mii_preamble_required++; |
||
1012 | mdio_read(ioaddr, 24, 1); |
||
1013 | for (phy = 0; phy < 32 && phy_idx < 1; phy++) { |
||
1014 | int mii_status, phyx; |
||
1015 | |||
1016 | /* |
||
1017 | * For the 3c905CX we look at index 24 first, because it bogusly |
||
1018 | * reports an external PHY at all indices |
||
1019 | */ |
||
1020 | if (phy == 0) |
||
1021 | phyx = 24; |
||
1022 | else if (phy <= 24) |
||
1023 | phyx = phy - 1; |
||
1024 | else |
||
1025 | phyx = phy; |
||
1026 | mii_status = mdio_read(ioaddr, phyx, 1); |
||
1027 | if (mii_status && mii_status != 0xffff) { |
||
1028 | vp->phys[phy_idx++] = phyx; |
||
1029 | printk(KERN_INFO " MII transceiver found at address %d," |
||
1030 | " status %4x.\n", phyx, mii_status); |
||
1031 | if ((mii_status & 0x0040) == 0) |
||
1032 | mii_preamble_required++; |
||
1033 | } |
||
1034 | } |
||
1035 | mii_preamble_required--; |
||
1036 | if (phy_idx == 0) { |
||
1037 | printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n"); |
||
1038 | vp->phys[0] = 24; |
||
1039 | } else { |
||
1040 | vp->advertising = mdio_read(ioaddr, vp->phys[0], 4); |
||
1041 | if (vp->full_duplex) { |
||
1042 | /* Only advertise the FD media types. */ |
||
1043 | vp->advertising &= ~0x02A0; |
||
1044 | mdio_write(ioaddr, vp->phys[0], 4, vp->advertising); |
||
1045 | } |
||
1046 | } |
||
1047 | } |
||
1048 | |||
1049 | if (vp->enable_wol && (vp->capabilities & CapPwrMgmt)) |
||
1050 | acpi_set_WOL(dev); |
||
1051 | |||
1052 | if (vp->capabilities & CapBusMaster) { |
||
1053 | vp->full_bus_master_tx = 1; |
||
1054 | printk(KERN_INFO" Enabling bus-master transmits and %s receives.\n", |
||
1055 | (vp->info2 & 1) ? "early" : "whole-frame" ); |
||
1056 | vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2; |
||
1057 | } |
||
1058 | |||
1059 | /* We do a request_region() to register /proc/ioports info. */ |
||
1060 | request_region(ioaddr, pci_tbl[chip_idx].io_size, dev->name); |
||
1061 | |||
1062 | /* The 3c59x-specific entries in the device structure. */ |
||
1063 | dev->open = vortex_open; |
||
1064 | dev->hard_start_xmit = vp->full_bus_master_tx ? |
||
1065 | boomerang_start_xmit : vortex_start_xmit; |
||
1066 | dev->stop = vortex_close; |
||
1067 | dev->get_stats = vortex_get_stats; |
||
1068 | dev->do_ioctl = vortex_ioctl; |
||
1069 | dev->set_multicast_list = set_rx_mode; |
||
1070 | |||
1071 | return dev; |
||
1072 | } |
||
1073 | |||
1074 | |||
1075 | static int |
||
1076 | vortex_open(struct device *dev) |
||
1077 | { |
||
1078 | long ioaddr = dev->base_addr; |
||
1079 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1080 | unsigned int config; |
||
1081 | int i, retval; |
||
1082 | |||
1083 | MOD_INC_USE_COUNT; |
||
1084 | |||
1085 | if (vp->enable_wol) |
||
1086 | acpi_wake(vp->pci_bus, vp->pci_devfn); |
||
1087 | |||
1088 | /* Before initializing select the active media port. */ |
||
1089 | EL3WINDOW(3); |
||
1090 | config = inl(ioaddr + Wn3_Config); |
||
1091 | |||
1092 | if (vp->media_override != 7) { |
||
1093 | if (vortex_debug > 1) |
||
1094 | printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n", |
||
1095 | dev->name, vp->media_override, |
||
1096 | media_tbl[vp->media_override].name); |
||
1097 | dev->if_port = vp->media_override; |
||
1098 | } else if (vp->autoselect && pci_tbl[vp->chip_id].drv_flags & HAS_NWAY) { |
||
1099 | if (vortex_debug > 1) |
||
1100 | printk(KERN_INFO "%s: using NWAY from config\n", dev->name); |
||
1101 | dev->if_port = XCVR_NWAY; |
||
1102 | } else if (vp->autoselect) { |
||
1103 | /* Find first available media type, starting with 100baseTx. */ |
||
1104 | dev->if_port = XCVR_100baseTx; |
||
1105 | while (! (vp->available_media & media_tbl[dev->if_port].mask)) |
||
1106 | dev->if_port = media_tbl[dev->if_port].next; |
||
1107 | } else |
||
1108 | dev->if_port = vp->default_media; |
||
1109 | |||
1110 | printk(KERN_INFO "%s: Initial media type %s.\n", dev->name, media_tbl[dev->if_port].name); |
||
1111 | |||
1112 | if (!vp->duplexlock && (vp->info1 & 0x8000)) |
||
1113 | vp->full_duplex = 1; |
||
1114 | |||
1115 | config = BFINS(config, dev->if_port, 20, 4); |
||
1116 | outl(config, ioaddr + Wn3_Config); |
||
1117 | |||
1118 | if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
||
1119 | int mii_reg1, mii_reg5; |
||
1120 | EL3WINDOW(4); |
||
1121 | /* Read BMSR (reg1) only to clear old status. */ |
||
1122 | mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1); |
||
1123 | mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
||
1124 | if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) |
||
1125 | ; /* No MII device or no link partner report */ |
||
1126 | else if (!vp->duplexlock && |
||
1127 | ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */ |
||
1128 | || (mii_reg5 & 0x00C0) == 0x0040)) /* 10T-FD, but not 100-HD */ |
||
1129 | vp->full_duplex = 1; |
||
1130 | printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x," |
||
1131 | " setting %s-duplex.\n", dev->name, vp->phys[0], |
||
1132 | mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half"); |
||
1133 | EL3WINDOW(3); |
||
1134 | } |
||
1135 | |||
1136 | /* Set the full-duplex bit. */ |
||
1137 | outb((vp->full_duplex ? 0x20 : 0) | (dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl); |
||
1138 | |||
1139 | if (vortex_debug > 1) { |
||
1140 | printk(KERN_DEBUG "%s: vortex_open() InternalConfig %8.8x.\n", dev->name, config); |
||
1141 | } |
||
1142 | |||
1143 | wait_for_completion(dev, TxReset); |
||
1144 | wait_for_completion(dev, RxReset); |
||
1145 | |||
1146 | outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD); |
||
1147 | |||
1148 | /* Use the now-standard shared IRQ implementation. */ |
||
1149 | if ((retval = request_irq(dev->irq, vp->full_bus_master_tx ? |
||
1150 | &boomerang_interrupt : &vortex_interrupt, |
||
1151 | SA_SHIRQ, dev->name, dev))) { |
||
1152 | printk(KERN_ERR "%s: Cannot allocate IRQ #%d\n", dev->name, dev->irq); |
||
1153 | goto out; |
||
1154 | } |
||
1155 | |||
1156 | if (vortex_debug > 1) { |
||
1157 | EL3WINDOW(4); |
||
1158 | printk(KERN_DEBUG "%s: vortex_open() irq %d media status %4.4x.\n", |
||
1159 | dev->name, dev->irq, inw(ioaddr + Wn4_Media)); |
||
1160 | } |
||
1161 | |||
1162 | /* Set the station address and mask in window 2 each time opened. */ |
||
1163 | EL3WINDOW(2); |
||
1164 | for (i = 0; i < 6; i++) |
||
1165 | outb(dev->dev_addr[i], ioaddr + i); |
||
1166 | for (; i < 12; i+=2) |
||
1167 | outw(0, ioaddr + i); |
||
1168 | |||
1169 | if (dev->if_port == XCVR_10base2) |
||
1170 | /* Start the thinnet transceiver. We should really wait 50ms...*/ |
||
1171 | outw(StartCoax, ioaddr + EL3_CMD); |
||
1172 | if (dev->if_port != XCVR_NWAY) { |
||
1173 | EL3WINDOW(4); |
||
1174 | outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) | |
||
1175 | media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
||
1176 | } |
||
1177 | |||
1178 | /* Switch to the stats window, and clear all stats by reading. */ |
||
1179 | outw(StatsDisable, ioaddr + EL3_CMD); |
||
1180 | EL3WINDOW(6); |
||
1181 | for (i = 0; i < 10; i++) |
||
1182 | inb(ioaddr + i); |
||
1183 | inw(ioaddr + 10); |
||
1184 | inw(ioaddr + 12); |
||
1185 | /* New: On the Vortex we must also clear the BadSSD counter. */ |
||
1186 | EL3WINDOW(4); |
||
1187 | inb(ioaddr + 12); |
||
1188 | /* ..and on the Boomerang we enable the extra statistics bits. */ |
||
1189 | outw(0x0040, ioaddr + Wn4_NetDiag); |
||
1190 | |||
1191 | /* Switch to register set 7 for normal use. */ |
||
1192 | EL3WINDOW(7); |
||
1193 | |||
1194 | if (vp->full_bus_master_rx) { /* Boomerang bus master. */ |
||
1195 | vp->cur_rx = vp->dirty_rx = 0; |
||
1196 | /* Initialize the RxEarly register as recommended. */ |
||
1197 | outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1198 | outl(0x0020, ioaddr + PktStatus); |
||
1199 | if (vortex_debug > 2) |
||
1200 | printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name); |
||
1201 | for (i = 0; i < RX_RING_SIZE; i++) { |
||
1202 | struct sk_buff *skb; |
||
1203 | vp->rx_ring[i].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[i+1])); |
||
1204 | vp->rx_ring[i].status = 0; /* Clear complete bit. */ |
||
1205 | vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); |
||
1206 | skb = dev_alloc_skb(PKT_BUF_SZ); |
||
1207 | vp->rx_skbuff[i] = skb; |
||
1208 | if (skb == NULL) |
||
1209 | break; /* Bad news! */ |
||
1210 | skb->dev = dev; /* Mark as being used by this device. */ |
||
1211 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1212 | vp->rx_ring[i].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
||
1213 | } |
||
1214 | if (i != RX_RING_SIZE) { |
||
1215 | int j; |
||
1216 | printk(KERN_EMERG "%s: no memory for rx ring\n", dev->name); |
||
1217 | for (j = 0; j < i; j++) { |
||
1218 | if (vp->rx_skbuff[j]) |
||
1219 | dev_kfree_skb(vp->rx_skbuff[j]); |
||
1220 | } |
||
1221 | retval = -ENOMEM; |
||
1222 | goto out_free_irq; |
||
1223 | } |
||
1224 | /* Wrap the ring. */ |
||
1225 | vp->rx_ring[i-1].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[0])); |
||
1226 | outl(virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr); |
||
1227 | } |
||
1228 | if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ |
||
1229 | vp->cur_tx = vp->dirty_tx = 0; |
||
1230 | outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */ |
||
1231 | /* Clear the Tx ring. */ |
||
1232 | for (i = 0; i < TX_RING_SIZE; i++) |
||
1233 | vp->tx_skbuff[i] = 0; |
||
1234 | outl(0, ioaddr + DownListPtr); |
||
1235 | } |
||
1236 | /* Set receiver mode: presumably accept b-case and phys addr only. */ |
||
1237 | set_rx_mode(dev); |
||
1238 | outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ |
||
1239 | |||
1240 | dev->tbusy = 0; |
||
1241 | dev->start = 1; |
||
1242 | vp->tx_full = 0; |
||
1243 | |||
1244 | outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */ |
||
1245 | outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */ |
||
1246 | /* Allow status bits to be seen. */ |
||
1247 | vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete| |
||
1248 | (vp->full_bus_master_tx ? DownComplete : TxAvailable) | |
||
1249 | (vp->full_bus_master_rx ? UpComplete : RxComplete) | |
||
1250 | (vp->bus_master ? DMADone : 0); |
||
1251 | vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | |
||
1252 | (vp->full_bus_master_rx ? 0 : RxComplete) | |
||
1253 | StatsFull | HostError | TxComplete | IntReq |
||
1254 | | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; |
||
1255 | outw(vp->status_enable, ioaddr + EL3_CMD); |
||
1256 | /* Ack all pending events, and set active indicator mask. */ |
||
1257 | outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, |
||
1258 | ioaddr + EL3_CMD); |
||
1259 | outw(vp->intr_enable, ioaddr + EL3_CMD); |
||
1260 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
||
1261 | writel(0x8000, vp->cb_fn_base + 4); |
||
1262 | |||
1263 | init_timer(&vp->timer); |
||
1264 | vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait); |
||
1265 | vp->timer.data = (unsigned long)dev; |
||
1266 | vp->timer.function = &vortex_timer; /* timer handler */ |
||
1267 | add_timer(&vp->timer); |
||
1268 | |||
1269 | init_timer(&vp->rx_oom_timer); |
||
1270 | vp->rx_oom_timer.data = (unsigned long)dev; |
||
1271 | vp->rx_oom_timer.function = rx_oom_timer; |
||
1272 | |||
1273 | return 0; |
||
1274 | |||
1275 | out_free_irq: |
||
1276 | free_irq(dev->irq, dev); |
||
1277 | out: |
||
1278 | return retval; |
||
1279 | } |
||
1280 | |||
1281 | static void vortex_timer(unsigned long data) |
||
1282 | { |
||
1283 | struct device *dev = (struct device *)data; |
||
1284 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1285 | long ioaddr = dev->base_addr; |
||
1286 | int next_tick = 60 * HZ; |
||
1287 | int ok = 0; |
||
1288 | int media_status, mii_status, old_window; |
||
1289 | |||
1290 | if (vortex_debug > 1) |
||
1291 | printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n", |
||
1292 | dev->name, media_tbl[dev->if_port].name); |
||
1293 | |||
1294 | if (vp->medialock) |
||
1295 | goto leave_media_alone; |
||
1296 | disable_irq(dev->irq); |
||
1297 | old_window = inw(ioaddr + EL3_CMD) >> 13; |
||
1298 | EL3WINDOW(4); |
||
1299 | media_status = inw(ioaddr + Wn4_Media); |
||
1300 | switch (dev->if_port) { |
||
1301 | case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: |
||
1302 | if (media_status & Media_LnkBeat) { |
||
1303 | ok = 1; |
||
1304 | if (vortex_debug > 1) |
||
1305 | printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n", |
||
1306 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1307 | } else if (vortex_debug > 1) |
||
1308 | printk(KERN_DEBUG "%s: Media %s is has no link beat, %x.\n", |
||
1309 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1310 | break; |
||
1311 | case XCVR_MII: case XCVR_NWAY: |
||
1312 | { |
||
1313 | unsigned long flags; |
||
1314 | spin_lock_irqsave(&vp->lock, flags); |
||
1315 | mii_status = mdio_read(ioaddr, vp->phys[0], 1); |
||
1316 | ok = 1; |
||
1317 | if (vortex_debug > 1) |
||
1318 | printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n", |
||
1319 | dev->name, mii_status); |
||
1320 | if (mii_status & 0x0004) { |
||
1321 | int mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
||
1322 | if (!vp->duplexlock && mii_reg5 != 0xffff) { |
||
1323 | int duplex = (mii_reg5&0x0100) || |
||
1324 | (mii_reg5 & 0x01C0) == 0x0040; |
||
1325 | if (vp->full_duplex != duplex) { |
||
1326 | vp->full_duplex = duplex; |
||
1327 | printk(KERN_INFO "%s: Setting %s-duplex based on MII " |
||
1328 | "#%d link partner capability of %4.4x.\n", |
||
1329 | dev->name, vp->full_duplex ? "full" : "half", |
||
1330 | vp->phys[0], mii_reg5); |
||
1331 | /* Set the full-duplex bit. */ |
||
1332 | EL3WINDOW(3); |
||
1333 | outb((vp->full_duplex ? 0x20 : 0) | |
||
1334 | (dev->mtu > 1500 ? 0x40 : 0), |
||
1335 | ioaddr + Wn3_MAC_Ctrl); |
||
1336 | } |
||
1337 | next_tick = 60*HZ; |
||
1338 | } |
||
1339 | } |
||
1340 | spin_unlock_irqrestore(&vp->lock, flags); |
||
1341 | } |
||
1342 | break; |
||
1343 | default: /* Other media types handled by Tx timeouts. */ |
||
1344 | if (vortex_debug > 1) |
||
1345 | printk(KERN_DEBUG "%s: Media %s has no indication, %x.\n", |
||
1346 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1347 | ok = 1; |
||
1348 | } |
||
1349 | if ( ! ok) { |
||
1350 | unsigned int config; |
||
1351 | |||
1352 | do { |
||
1353 | dev->if_port = media_tbl[dev->if_port].next; |
||
1354 | } while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); |
||
1355 | if (dev->if_port == XCVR_Default) { /* Go back to default. */ |
||
1356 | dev->if_port = vp->default_media; |
||
1357 | if (vortex_debug > 1) |
||
1358 | printk(KERN_DEBUG "%s: Media selection failing, using default " |
||
1359 | "%s port.\n", |
||
1360 | dev->name, media_tbl[dev->if_port].name); |
||
1361 | } else { |
||
1362 | if (vortex_debug > 1) |
||
1363 | printk(KERN_DEBUG "%s: Media selection failed, now trying " |
||
1364 | "%s port.\n", |
||
1365 | dev->name, media_tbl[dev->if_port].name); |
||
1366 | next_tick = media_tbl[dev->if_port].wait; |
||
1367 | } |
||
1368 | outw((media_status & ~(Media_10TP|Media_SQE)) | |
||
1369 | media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
||
1370 | |||
1371 | EL3WINDOW(3); |
||
1372 | config = inl(ioaddr + Wn3_Config); |
||
1373 | config = BFINS(config, dev->if_port, 20, 4); |
||
1374 | outl(config, ioaddr + Wn3_Config); |
||
1375 | |||
1376 | outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, |
||
1377 | ioaddr + EL3_CMD); |
||
1378 | } |
||
1379 | EL3WINDOW(old_window); |
||
1380 | enable_irq(dev->irq); |
||
1381 | |||
1382 | leave_media_alone: |
||
1383 | if (vortex_debug > 2) |
||
1384 | printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n", |
||
1385 | dev->name, media_tbl[dev->if_port].name); |
||
1386 | |||
1387 | vp->timer.expires = RUN_AT(next_tick); |
||
1388 | add_timer(&vp->timer); |
||
1389 | if (vp->deferred) |
||
1390 | outw(FakeIntr, ioaddr + EL3_CMD); |
||
1391 | return; |
||
1392 | } |
||
1393 | |||
1394 | static void vortex_tx_timeout(struct device *dev) |
||
1395 | { |
||
1396 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1397 | long ioaddr = dev->base_addr; |
||
1398 | |||
1399 | printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n", |
||
1400 | dev->name, inb(ioaddr + TxStatus), |
||
1401 | inw(ioaddr + EL3_STATUS)); |
||
1402 | /* Slight code bloat to be user friendly. */ |
||
1403 | if ((inb(ioaddr + TxStatus) & 0x88) == 0x88) |
||
1404 | printk(KERN_ERR "%s: Transmitter encountered 16 collisions --" |
||
1405 | " network cable problem?\n", dev->name); |
||
1406 | if (inw(ioaddr + EL3_STATUS) & IntLatch) { |
||
1407 | printk(KERN_ERR "%s: Interrupt posted but not delivered --" |
||
1408 | " IRQ blocked by another device?\n", dev->name); |
||
1409 | /* Bad idea here.. but we might as well handle a few events. */ |
||
1410 | { |
||
1411 | /* |
||
1412 | * AKPM: block interrupts because vortex_interrupt |
||
1413 | * does a bare spin_lock() |
||
1414 | */ |
||
1415 | unsigned long flags; |
||
1416 | __save_flags(flags); |
||
1417 | __cli(); |
||
1418 | if (vp->full_bus_master_tx) |
||
1419 | boomerang_interrupt(dev->irq, dev, 0); |
||
1420 | else |
||
1421 | vortex_interrupt(dev->irq, dev, 0); |
||
1422 | __restore_flags(flags); |
||
1423 | } |
||
1424 | } |
||
1425 | |||
1426 | if (vp->full_bus_master_tx) { |
||
1427 | int i; |
||
1428 | printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d " |
||
1429 | "current %d.\n", |
||
1430 | vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx, vp->cur_tx); |
||
1431 | printk(KERN_DEBUG " Transmit list %8.8x vs. %p.\n", |
||
1432 | inl(ioaddr + DownListPtr), |
||
1433 | &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); |
||
1434 | for (i = 0; i < TX_RING_SIZE; i++) { |
||
1435 | printk(KERN_DEBUG " %d: @%p length %8.8x status %8.8x\n", i, |
||
1436 | &vp->tx_ring[i], |
||
1437 | le32_to_cpu(vp->tx_ring[i].length), |
||
1438 | le32_to_cpu(vp->tx_ring[i].status)); |
||
1439 | } |
||
1440 | } |
||
1441 | wait_for_completion(dev, TxReset); |
||
1442 | vp->stats.tx_errors++; |
||
1443 | if (vp->full_bus_master_tx) { |
||
1444 | if (vortex_debug > 0) |
||
1445 | printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", |
||
1446 | dev->name); |
||
1447 | if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0) |
||
1448 | outl(virt_to_bus(&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]), |
||
1449 | ioaddr + DownListPtr); |
||
1450 | if (vp->tx_full && (vp->cur_tx - vp->dirty_tx <= TX_RING_SIZE - 1)) { |
||
1451 | vp->tx_full = 0; |
||
1452 | clear_bit(0, (void*)&dev->tbusy); |
||
1453 | } |
||
1454 | outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); |
||
1455 | outw(DownUnstall, ioaddr + EL3_CMD); |
||
1456 | } else { |
||
1457 | vp->stats.tx_dropped++; |
||
1458 | clear_bit(0, (void*)&dev->tbusy); |
||
1459 | } |
||
1460 | |||
1461 | /* Issue Tx Enable */ |
||
1462 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1463 | dev->trans_start = jiffies; |
||
1464 | |||
1465 | /* Switch to register set 7 for normal use. */ |
||
1466 | EL3WINDOW(7); |
||
1467 | } |
||
1468 | |||
1469 | /* |
||
1470 | * Handle uncommon interrupt sources. This is a separate routine to minimize |
||
1471 | * the cache impact. |
||
1472 | */ |
||
1473 | static void |
||
1474 | vortex_error(struct device *dev, int status) |
||
1475 | { |
||
1476 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1477 | long ioaddr = dev->base_addr; |
||
1478 | int do_tx_reset = 0; |
||
1479 | |||
1480 | if (status & TxComplete) { /* Really "TxError" for us. */ |
||
1481 | unsigned char tx_status = inb(ioaddr + TxStatus); |
||
1482 | /* Presumably a tx-timeout. We must merely re-enable. */ |
||
1483 | if (vortex_debug > 2 |
||
1484 | || (tx_status != 0x88 && vortex_debug > 0)) |
||
1485 | printk(KERN_DEBUG"%s: Transmit error, Tx status register %2.2x.\n", |
||
1486 | dev->name, tx_status); |
||
1487 | if (tx_status & 0x14) vp->stats.tx_fifo_errors++; |
||
1488 | if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
||
1489 | outb(0, ioaddr + TxStatus); |
||
1490 | if (tx_status & 0x30) /* txJabber or txUnderrun */ |
||
1491 | do_tx_reset = 1; |
||
1492 | else /* Merely re-enable the transmitter. */ |
||
1493 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1494 | } |
||
1495 | if (status & RxEarly) { /* Rx early is unused. */ |
||
1496 | vortex_rx(dev); |
||
1497 | outw(AckIntr | RxEarly, ioaddr + EL3_CMD); |
||
1498 | } |
||
1499 | if (status & StatsFull) { /* Empty statistics. */ |
||
1500 | static int DoneDidThat = 0; |
||
1501 | if (vortex_debug > 4) |
||
1502 | printk(KERN_DEBUG "%s: Updating stats.\n", dev->name); |
||
1503 | update_stats(ioaddr, dev); |
||
1504 | /* HACK: Disable statistics as an interrupt source. */ |
||
1505 | /* This occurs when we have the wrong media type! */ |
||
1506 | if (DoneDidThat == 0 && |
||
1507 | inw(ioaddr + EL3_STATUS) & StatsFull) { |
||
1508 | printk(KERN_WARNING "%s: Updating statistics failed, disabling " |
||
1509 | "stats as an interrupt source.\n", dev->name); |
||
1510 | EL3WINDOW(5); |
||
1511 | outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD); |
||
1512 | EL3WINDOW(7); |
||
1513 | DoneDidThat++; |
||
1514 | } |
||
1515 | } |
||
1516 | if (status & IntReq) { /* Restore all interrupt sources. */ |
||
1517 | outw(vp->status_enable, ioaddr + EL3_CMD); |
||
1518 | outw(vp->intr_enable, ioaddr + EL3_CMD); |
||
1519 | } |
||
1520 | if (status & HostError) { |
||
1521 | u16 fifo_diag; |
||
1522 | EL3WINDOW(4); |
||
1523 | fifo_diag = inw(ioaddr + Wn4_FIFODiag); |
||
1524 | if (vortex_debug > 0) |
||
1525 | printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n", |
||
1526 | dev->name, fifo_diag); |
||
1527 | /* Adapter failure requires Tx/Rx reset and reinit. */ |
||
1528 | if (vp->full_bus_master_tx) { |
||
1529 | wait_for_completion(dev, TotalReset|0xff); |
||
1530 | /* Re-enable the receiver. */ |
||
1531 | outw(RxEnable, ioaddr + EL3_CMD); |
||
1532 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1533 | } else if (fifo_diag & 0x0400) |
||
1534 | do_tx_reset = 1; |
||
1535 | if (fifo_diag & 0x3000) { |
||
1536 | wait_for_completion(dev, RxReset); |
||
1537 | /* Set the Rx filter to the current state. */ |
||
1538 | set_rx_mode(dev); |
||
1539 | outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ |
||
1540 | outw(AckIntr | HostError, ioaddr + EL3_CMD); |
||
1541 | } |
||
1542 | } |
||
1543 | if (do_tx_reset) { |
||
1544 | wait_for_completion(dev, TxReset); |
||
1545 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1546 | if (!vp->full_bus_master_tx) { |
||
1547 | clear_bit(0, (void*)&dev->tbusy); |
||
1548 | mark_bh(NET_BH); |
||
1549 | } |
||
1550 | } |
||
1551 | |||
1552 | } |
||
1553 | |||
1554 | static int |
||
1555 | vortex_start_xmit(struct sk_buff *skb, struct device *dev) |
||
1556 | { |
||
1557 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1558 | long ioaddr = dev->base_addr; |
||
1559 | |||
1560 | if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
||
1561 | if (jiffies - dev->trans_start >= TX_TIMEOUT) |
||
1562 | vortex_tx_timeout(dev); |
||
1563 | return 1; |
||
1564 | } |
||
1565 | if (vortex_debug > 3) |
||
1566 | printk(KERN_DEBUG "%s: Trying to send a boomerang packet, Tx index %d.\n", |
||
1567 | dev->name, vp->cur_tx); |
||
1568 | |||
1569 | /* Put out the doubleword header... */ |
||
1570 | outl(skb->len, ioaddr + TX_FIFO); |
||
1571 | if (vp->bus_master) { |
||
1572 | /* Set the bus-master controller to transfer the packet. */ |
||
1573 | outl(virt_to_bus(skb->data), ioaddr + Wn7_MasterAddr); |
||
1574 | outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
||
1575 | vp->tx_skb = skb; |
||
1576 | outw(StartDMADown, ioaddr + EL3_CMD); |
||
1577 | /* dev->tbusy will be cleared at the DMADone interrupt. */ |
||
1578 | } else { |
||
1579 | /* ... and the packet rounded to a doubleword. */ |
||
1580 | #ifdef __powerpc__ |
||
1581 | outsl_ns(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); |
||
1582 | #else |
||
1583 | outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); |
||
1584 | #endif |
||
1585 | dev_kfree_skb(skb); |
||
1586 | if (inw(ioaddr + TxFree) > 1536) { |
||
1587 | clear_bit(0, (void*)&dev->tbusy); |
||
1588 | } else |
||
1589 | /* Interrupt us when the FIFO has room for max-sized packet. */ |
||
1590 | outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1591 | } |
||
1592 | |||
1593 | dev->trans_start = jiffies; |
||
1594 | |||
1595 | /* Clear the Tx status stack. */ |
||
1596 | { |
||
1597 | int tx_status; |
||
1598 | int i = 32; |
||
1599 | |||
1600 | while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) { |
||
1601 | if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ |
||
1602 | if (vortex_debug > 2) |
||
1603 | printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n", |
||
1604 | dev->name, tx_status); |
||
1605 | if (tx_status & 0x04) vp->stats.tx_fifo_errors++; |
||
1606 | if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
||
1607 | if (tx_status & 0x30) |
||
1608 | wait_for_completion(dev, TxReset); |
||
1609 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1610 | } |
||
1611 | outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */ |
||
1612 | } |
||
1613 | } |
||
1614 | vp->stats.tx_bytes += skb->len; |
||
1615 | return 0; |
||
1616 | } |
||
1617 | |||
1618 | static int |
||
1619 | boomerang_start_xmit(struct sk_buff *skb, struct device *dev) |
||
1620 | { |
||
1621 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1622 | long ioaddr = dev->base_addr; |
||
1623 | |||
1624 | if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
||
1625 | if (jiffies - dev->trans_start >= TX_TIMEOUT) |
||
1626 | vortex_tx_timeout(dev); |
||
1627 | return 1; |
||
1628 | } else { |
||
1629 | /* Calculate the next Tx descriptor entry. */ |
||
1630 | int entry = vp->cur_tx % TX_RING_SIZE; |
||
1631 | struct boom_tx_desc *prev_entry = |
||
1632 | &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]; |
||
1633 | unsigned long flags; |
||
1634 | |||
1635 | if (vortex_debug > 3) |
||
1636 | printk(KERN_DEBUG "%s: Trying to send a boomerang packet, Tx index %d.\n", |
||
1637 | dev->name, vp->cur_tx); |
||
1638 | if (vp->tx_full) { |
||
1639 | if (vortex_debug > 0) |
||
1640 | printk(KERN_WARNING "%s: Tx Ring full, refusing to send buffer.\n", |
||
1641 | dev->name); |
||
1642 | return 1; |
||
1643 | } |
||
1644 | vp->tx_skbuff[entry] = skb; |
||
1645 | vp->tx_ring[entry].next = 0; |
||
1646 | vp->tx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->data)); |
||
1647 | vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG); |
||
1648 | vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); |
||
1649 | |||
1650 | spin_lock_irqsave(&vp->lock, flags); |
||
1651 | wait_for_completion(dev, DownStall); |
||
1652 | prev_entry->next = cpu_to_le32(virt_to_bus(&vp->tx_ring[entry])); |
||
1653 | if (inl(ioaddr + DownListPtr) == 0) { |
||
1654 | outl(virt_to_bus(&vp->tx_ring[entry]), ioaddr + DownListPtr); |
||
1655 | queued_packet++; |
||
1656 | } |
||
1657 | |||
1658 | vp->cur_tx++; |
||
1659 | if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) |
||
1660 | vp->tx_full = 1; |
||
1661 | else { /* Clear previous interrupt enable. */ |
||
1662 | prev_entry->status &= cpu_to_le32(~TxIntrUploaded); |
||
1663 | clear_bit(0, (void*)&dev->tbusy); |
||
1664 | } |
||
1665 | outw(DownUnstall, ioaddr + EL3_CMD); |
||
1666 | spin_unlock_irqrestore(&vp->lock, flags); |
||
1667 | dev->trans_start = jiffies; |
||
1668 | vp->stats.tx_bytes += skb->len; |
||
1669 | return 0; |
||
1670 | } |
||
1671 | } |
||
1672 | |||
1673 | /* The interrupt handler does all of the Rx thread work and cleans up |
||
1674 | after the Tx thread. */ |
||
1675 | |||
1676 | /* |
||
1677 | * This is the ISR for the vortex series chips. |
||
1678 | * full_bus_master_tx == 0 && full_bus_master_rx == 0 |
||
1679 | */ |
||
1680 | |||
1681 | static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
||
1682 | { |
||
1683 | struct device *dev = dev_id; |
||
1684 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1685 | long ioaddr; |
||
1686 | int status; |
||
1687 | int work_done = max_interrupt_work; |
||
1688 | |||
1689 | ioaddr = dev->base_addr; |
||
1690 | spin_lock(&vp->lock); |
||
1691 | status = inw(ioaddr + EL3_STATUS); |
||
1692 | if ((status & IntLatch) == 0) { |
||
1693 | if (vortex_debug > 5) |
||
1694 | printk(KERN_DEBUG "%s: no vortex interrupt pending\n", dev->name); |
||
1695 | goto no_int; /* Happens during shared interrupts */ |
||
1696 | } |
||
1697 | |||
1698 | if (status & IntReq) { |
||
1699 | status |= vp->deferred; |
||
1700 | vp->deferred = 0; |
||
1701 | } |
||
1702 | |||
1703 | if (vortex_debug > 4) |
||
1704 | printk(KERN_DEBUG "%s: vortex_interrupt, status %4.4x, latency %d ticks.\n", |
||
1705 | dev->name, status, inb(ioaddr + Timer)); |
||
1706 | |||
1707 | do { |
||
1708 | if (vortex_debug > 5) |
||
1709 | printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n", |
||
1710 | dev->name, status); |
||
1711 | |||
1712 | if (status & RxComplete) |
||
1713 | vortex_rx(dev); |
||
1714 | |||
1715 | if (status & TxAvailable) { |
||
1716 | if (vortex_debug > 5) |
||
1717 | printk(KERN_DEBUG " TX room bit was handled.\n"); |
||
1718 | /* There's room in the FIFO for a full-sized packet. */ |
||
1719 | outw(AckIntr | TxAvailable, ioaddr + EL3_CMD); |
||
1720 | clear_bit(0, (void*)&dev->tbusy); |
||
1721 | mark_bh(NET_BH); |
||
1722 | } |
||
1723 | |||
1724 | if (status & DMADone) { |
||
1725 | if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) { |
||
1726 | outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ |
||
1727 | dev_kfree_skb(vp->tx_skb); /* Release the transfered buffer */ |
||
1728 | if (inw(ioaddr + TxFree) > 1536) { |
||
1729 | clear_bit(0, (void*)&dev->tbusy); |
||
1730 | mark_bh(NET_BH); |
||
1731 | } else /* Interrupt when FIFO has room for max-sized packet. */ |
||
1732 | outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1733 | } |
||
1734 | } |
||
1735 | |||
1736 | /* Check for all uncommon interrupts at once. */ |
||
1737 | if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { |
||
1738 | if (status == 0xffff) |
||
1739 | break; |
||
1740 | vortex_error(dev, status); |
||
1741 | } |
||
1742 | |||
1743 | if (--work_done < 0) { |
||
1744 | printk(KERN_WARNING "%s: Too much work in interrupt, status " |
||
1745 | "%4.4x.\n", dev->name, status); |
||
1746 | /* Disable all pending interrupts. */ |
||
1747 | do { |
||
1748 | vp->deferred |= status; |
||
1749 | outw(SetStatusEnb | (~vp->deferred & vp->status_enable), |
||
1750 | ioaddr + EL3_CMD); |
||
1751 | outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); |
||
1752 | } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch); |
||
1753 | /* The timer will reenable interrupts. */ |
||
1754 | mod_timer(&vp->timer, RUN_AT(1)); |
||
1755 | break; |
||
1756 | } |
||
1757 | |||
1758 | /* Acknowledge the IRQ. */ |
||
1759 | outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
||
1760 | } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete)); |
||
1761 | |||
1762 | if (vortex_debug > 4) |
||
1763 | printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n", |
||
1764 | dev->name, status); |
||
1765 | |||
1766 | no_int: |
||
1767 | spin_unlock(&vp->lock); |
||
1768 | } |
||
1769 | |||
1770 | /* |
||
1771 | * This is the ISR for the boomerang/cyclone/hurricane/tornado series chips. |
||
1772 | * full_bus_master_tx == 1 && full_bus_master_rx == 1 |
||
1773 | */ |
||
1774 | |||
1775 | static void boomerang_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
||
1776 | { |
||
1777 | struct device *dev = dev_id; |
||
1778 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1779 | long ioaddr; |
||
1780 | int status; |
||
1781 | int work_done = max_interrupt_work; |
||
1782 | |||
1783 | ioaddr = dev->base_addr; |
||
1784 | spin_lock(&vp->lock); |
||
1785 | status = inw(ioaddr + EL3_STATUS); |
||
1786 | if ((status & IntLatch) == 0) { |
||
1787 | if (vortex_debug > 5) |
||
1788 | printk(KERN_DEBUG "%s: no boomerang interrupt pending\n", dev->name); |
||
1789 | goto no_int; /* Happens during shared interrupts */ |
||
1790 | } |
||
1791 | |||
1792 | if (status & IntReq) { |
||
1793 | status |= vp->deferred; |
||
1794 | vp->deferred = 0; |
||
1795 | } |
||
1796 | |||
1797 | if (vortex_debug > 4) |
||
1798 | printk(KERN_DEBUG "%s: boomerang interrupt, status %04x, latency %d, cur_rx %d, dirty_rx %d\n", |
||
1799 | dev->name, status, inb(ioaddr + Timer), vp->cur_rx, vp->dirty_rx); |
||
1800 | |||
1801 | do { |
||
1802 | if (vortex_debug > 5) |
||
1803 | printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n", |
||
1804 | dev->name, status); |
||
1805 | |||
1806 | if (status & UpComplete) { |
||
1807 | outw(AckIntr | UpComplete, ioaddr + EL3_CMD); |
||
1808 | boomerang_rx(dev); |
||
1809 | } |
||
1810 | |||
1811 | if (status & DownComplete) { |
||
1812 | unsigned int dirty_tx = vp->dirty_tx; |
||
1813 | |||
1814 | while (vp->cur_tx - dirty_tx > 0) { |
||
1815 | int entry = dirty_tx % TX_RING_SIZE; |
||
1816 | if (inl(ioaddr + DownListPtr) == |
||
1817 | virt_to_bus(&vp->tx_ring[entry])) |
||
1818 | break; /* It still hasn't been processed. */ |
||
1819 | if (vp->tx_skbuff[entry]) { |
||
1820 | dev_kfree_skb(vp->tx_skbuff[entry]); |
||
1821 | vp->tx_skbuff[entry] = 0; |
||
1822 | } |
||
1823 | /* vp->stats.tx_packets++; Counted below. */ |
||
1824 | dirty_tx++; |
||
1825 | } |
||
1826 | vp->dirty_tx = dirty_tx; |
||
1827 | outw(AckIntr | DownComplete, ioaddr + EL3_CMD); |
||
1828 | if (vp->tx_full && (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) { |
||
1829 | vp->tx_full = 0; |
||
1830 | clear_bit(0, (void*)&dev->tbusy); |
||
1831 | mark_bh(NET_BH); |
||
1832 | } |
||
1833 | } |
||
1834 | |||
1835 | /* Check for all uncommon interrupts at once. */ |
||
1836 | if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { |
||
1837 | if (status == 0xffff) |
||
1838 | break; |
||
1839 | vortex_error(dev, status); |
||
1840 | } |
||
1841 | |||
1842 | if (--work_done < 0) { |
||
1843 | printk(KERN_WARNING "%s: Too much work in interrupt, status " |
||
1844 | "%4.4x.\n", dev->name, status); |
||
1845 | /* Disable all pending interrupts. */ |
||
1846 | do { |
||
1847 | vp->deferred |= status; |
||
1848 | outw(SetStatusEnb | (~vp->deferred & vp->status_enable), |
||
1849 | ioaddr + EL3_CMD); |
||
1850 | outw(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD); |
||
1851 | } while ((status = inw(ioaddr + EL3_CMD)) & IntLatch); |
||
1852 | /* The timer will reenable interrupts. */ |
||
1853 | mod_timer(&vp->timer, RUN_AT(1)); |
||
1854 | break; |
||
1855 | } |
||
1856 | |||
1857 | /* Acknowledge the IRQ. */ |
||
1858 | outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
||
1859 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
||
1860 | writel(0x8000, vp->cb_fn_base + 4); |
||
1861 | |||
1862 | } while ((status = inw(ioaddr + EL3_STATUS)) & IntLatch); |
||
1863 | |||
1864 | if (vortex_debug > 4) |
||
1865 | printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n", |
||
1866 | dev->name, status); |
||
1867 | |||
1868 | no_int: |
||
1869 | spin_unlock(&vp->lock); |
||
1870 | } |
||
1871 | |||
1872 | static int vortex_rx(struct device *dev) |
||
1873 | { |
||
1874 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1875 | long ioaddr = dev->base_addr; |
||
1876 | int i; |
||
1877 | short rx_status; |
||
1878 | |||
1879 | if (vortex_debug > 5) |
||
1880 | printk(KERN_DEBUG" In vortex_rx(), status %4.4x, rx_status %4.4x.\n", |
||
1881 | inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
||
1882 | while ((rx_status = inw(ioaddr + RxStatus)) > 0) { |
||
1883 | if (rx_status & 0x4000) { /* Error, update stats. */ |
||
1884 | unsigned char rx_error = inb(ioaddr + RxErrors); |
||
1885 | if (vortex_debug > 2) |
||
1886 | printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
||
1887 | vp->stats.rx_errors++; |
||
1888 | if (rx_error & 0x01) vp->stats.rx_over_errors++; |
||
1889 | if (rx_error & 0x02) vp->stats.rx_length_errors++; |
||
1890 | if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
||
1891 | if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
||
1892 | if (rx_error & 0x10) vp->stats.rx_length_errors++; |
||
1893 | } else { |
||
1894 | /* The packet length: up to 4.5K!. */ |
||
1895 | int pkt_len = rx_status & 0x1fff; |
||
1896 | struct sk_buff *skb; |
||
1897 | |||
1898 | skb = dev_alloc_skb(pkt_len + 5); |
||
1899 | if (vortex_debug > 4) |
||
1900 | printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
||
1901 | pkt_len, rx_status); |
||
1902 | if (skb != NULL) { |
||
1903 | skb->dev = dev; |
||
1904 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1905 | /* 'skb_put()' points to the start of sk_buff data area. */ |
||
1906 | if (vp->bus_master && |
||
1907 | ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) { |
||
1908 | outl(virt_to_bus(skb_put(skb, pkt_len)), |
||
1909 | ioaddr + Wn7_MasterAddr); |
||
1910 | outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
||
1911 | outw(StartDMAUp, ioaddr + EL3_CMD); |
||
1912 | while (inw(ioaddr + Wn7_MasterStatus) & 0x8000) |
||
1913 | ; |
||
1914 | } else { |
||
1915 | #ifdef __powerpc__ |
||
1916 | insl_ns(ioaddr + RX_FIFO, skb_put(skb, pkt_len), |
||
1917 | (pkt_len + 3) >> 2); |
||
1918 | #else |
||
1919 | insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len), |
||
1920 | (pkt_len + 3) >> 2); |
||
1921 | #endif |
||
1922 | } |
||
1923 | outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */ |
||
1924 | skb->protocol = eth_type_trans(skb, dev); |
||
1925 | netif_rx(skb); |
||
1926 | dev->last_rx = jiffies; |
||
1927 | vp->stats.rx_packets++; |
||
1928 | vp->stats.rx_bytes += skb->len; |
||
1929 | /* Wait a limited time to go to next packet. */ |
||
1930 | for (i = 200; i >= 0; i--) |
||
1931 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1932 | break; |
||
1933 | continue; |
||
1934 | } else if (vortex_debug) |
||
1935 | printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of " |
||
1936 | "size %d.\n", dev->name, pkt_len); |
||
1937 | } |
||
1938 | vp->stats.rx_dropped++; |
||
1939 | wait_for_completion(dev, RxDiscard); |
||
1940 | } |
||
1941 | |||
1942 | return 0; |
||
1943 | } |
||
1944 | |||
1945 | static int |
||
1946 | boomerang_rx(struct device *dev) |
||
1947 | { |
||
1948 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1949 | int entry = vp->cur_rx % RX_RING_SIZE; |
||
1950 | long ioaddr = dev->base_addr; |
||
1951 | int rx_status; |
||
1952 | int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx; |
||
1953 | |||
1954 | if (vortex_debug > 5) |
||
1955 | printk(KERN_DEBUG " In boomerang_rx(), status %4.4x, rx_status " |
||
1956 | "%4.4x.\n", |
||
1957 | inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
||
1958 | while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){ |
||
1959 | if (--rx_work_limit < 0) |
||
1960 | break; |
||
1961 | if (rx_status & RxDError) { /* Error, update stats. */ |
||
1962 | unsigned char rx_error = rx_status >> 16; |
||
1963 | if (vortex_debug > 2) |
||
1964 | printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
||
1965 | vp->stats.rx_errors++; |
||
1966 | if (rx_error & 0x01) vp->stats.rx_over_errors++; |
||
1967 | if (rx_error & 0x02) vp->stats.rx_length_errors++; |
||
1968 | if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
||
1969 | if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
||
1970 | if (rx_error & 0x10) vp->stats.rx_length_errors++; |
||
1971 | } else { |
||
1972 | /* The packet length: up to 4.5K!. */ |
||
1973 | int pkt_len = rx_status & 0x1fff; |
||
1974 | struct sk_buff *skb; |
||
1975 | |||
1976 | vp->stats.rx_bytes += pkt_len; |
||
1977 | if (vortex_debug > 4) |
||
1978 | printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
||
1979 | pkt_len, rx_status); |
||
1980 | |||
1981 | /* Check if the packet is long enough to just accept without |
||
1982 | copying to a properly sized skbuff. */ |
||
1983 | if (pkt_len < rx_copybreak |
||
1984 | && (skb = dev_alloc_skb(pkt_len + 2)) != 0) { |
||
1985 | skb->dev = dev; |
||
1986 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1987 | /* 'skb_put()' points to the start of sk_buff data area. */ |
||
1988 | memcpy(skb_put(skb, pkt_len), |
||
1989 | bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
||
1990 | pkt_len); |
||
1991 | rx_copy++; |
||
1992 | } else { |
||
1993 | void *temp; |
||
1994 | /* Pass up the skbuff already on the Rx ring. */ |
||
1995 | skb = vp->rx_skbuff[entry]; |
||
1996 | vp->rx_skbuff[entry] = NULL; |
||
1997 | temp = skb_put(skb, pkt_len); |
||
1998 | /* Remove this checking code for final release. */ |
||
1999 | if (bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)) != temp) |
||
2000 | printk(KERN_ERR "%s: Warning -- the skbuff addresses do not match" |
||
2001 | " in boomerang_rx: %p vs. %p.\n", dev->name, |
||
2002 | bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
||
2003 | temp); |
||
2004 | rx_nocopy++; |
||
2005 | } |
||
2006 | skb->protocol = eth_type_trans(skb, dev); |
||
2007 | { /* Use hardware checksum info. */ |
||
2008 | int csum_bits = rx_status & 0xee000000; |
||
2009 | if (csum_bits && |
||
2010 | (csum_bits == (IPChksumValid | TCPChksumValid) || |
||
2011 | csum_bits == (IPChksumValid | UDPChksumValid))) { |
||
2012 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
||
2013 | rx_csumhits++; |
||
2014 | } |
||
2015 | } |
||
2016 | netif_rx(skb); |
||
2017 | dev->last_rx = jiffies; |
||
2018 | vp->stats.rx_packets++; |
||
2019 | } |
||
2020 | entry = (++vp->cur_rx) % RX_RING_SIZE; |
||
2021 | } |
||
2022 | /* Refill the Rx ring buffers. */ |
||
2023 | for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) { |
||
2024 | struct sk_buff *skb; |
||
2025 | entry = vp->dirty_rx % RX_RING_SIZE; |
||
2026 | if (vp->rx_skbuff[entry] == NULL) { |
||
2027 | skb = dev_alloc_skb(PKT_BUF_SZ); |
||
2028 | if (skb == NULL) { |
||
2029 | static unsigned long last_jif; |
||
2030 | if ((jiffies - last_jif) > 10 * HZ) { |
||
2031 | printk(KERN_WARNING "%s: memory shortage\n", dev->name); |
||
2032 | last_jif = jiffies; |
||
2033 | } |
||
2034 | if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) |
||
2035 | mod_timer(&vp->rx_oom_timer, RUN_AT(HZ * 1)); |
||
2036 | break; /* Bad news! */ |
||
2037 | } |
||
2038 | skb->dev = dev; /* Mark as being used by this device. */ |
||
2039 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
2040 | vp->rx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
||
2041 | vp->rx_skbuff[entry] = skb; |
||
2042 | } |
||
2043 | vp->rx_ring[entry].status = 0; /* Clear complete bit. */ |
||
2044 | outw(UpUnstall, ioaddr + EL3_CMD); |
||
2045 | } |
||
2046 | return 0; |
||
2047 | } |
||
2048 | |||
2049 | /* |
||
2050 | * If we've hit a total OOM refilling the Rx ring we poll once a second |
||
2051 | * for some memory. Otherwise there is no way to restart the rx process. |
||
2052 | */ |
||
2053 | static void |
||
2054 | rx_oom_timer(unsigned long arg) |
||
2055 | { |
||
2056 | struct device *dev = (struct device *)arg; |
||
2057 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2058 | |||
2059 | spin_lock_irq(&vp->lock); |
||
2060 | if ((vp->cur_rx - vp->dirty_rx) == RX_RING_SIZE) /* This test is redundant, but makes me feel good */ |
||
2061 | boomerang_rx(dev); |
||
2062 | if (vortex_debug > 1) { |
||
2063 | printk(KERN_DEBUG "%s: rx_oom_timer %s\n", dev->name, |
||
2064 | ((vp->cur_rx - vp->dirty_rx) != RX_RING_SIZE) ? "succeeded" : "retrying"); |
||
2065 | } |
||
2066 | spin_unlock_irq(&vp->lock); |
||
2067 | } |
||
2068 | |||
2069 | static int |
||
2070 | vortex_close(struct device *dev) |
||
2071 | { |
||
2072 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2073 | long ioaddr = dev->base_addr; |
||
2074 | int i; |
||
2075 | |||
2076 | dev->start = 0; |
||
2077 | dev->tbusy = 1; |
||
2078 | |||
2079 | if (vortex_debug > 1) { |
||
2080 | printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n", |
||
2081 | dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus)); |
||
2082 | printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d" |
||
2083 | " tx_queued %d Rx pre-checksummed %d.\n", |
||
2084 | dev->name, rx_nocopy, rx_copy, queued_packet, rx_csumhits); |
||
2085 | } |
||
2086 | |||
2087 | del_timer(&vp->timer); |
||
2088 | del_timer(&vp->rx_oom_timer); |
||
2089 | |||
2090 | /* Turn off statistics ASAP. We update vp->stats below. */ |
||
2091 | outw(StatsDisable, ioaddr + EL3_CMD); |
||
2092 | |||
2093 | /* Disable the receiver and transmitter. */ |
||
2094 | outw(RxDisable, ioaddr + EL3_CMD); |
||
2095 | outw(TxDisable, ioaddr + EL3_CMD); |
||
2096 | |||
2097 | if (dev->if_port == XCVR_10base2) |
||
2098 | /* Turn off thinnet power. Green! */ |
||
2099 | outw(StopCoax, ioaddr + EL3_CMD); |
||
2100 | |||
2101 | free_irq(dev->irq, dev); |
||
2102 | |||
2103 | outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); |
||
2104 | |||
2105 | update_stats(ioaddr, dev); |
||
2106 | if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */ |
||
2107 | outl(0, ioaddr + UpListPtr); |
||
2108 | for (i = 0; i < RX_RING_SIZE; i++) |
||
2109 | if (vp->rx_skbuff[i]) { |
||
2110 | dev_kfree_skb(vp->rx_skbuff[i]); |
||
2111 | vp->rx_skbuff[i] = 0; |
||
2112 | } |
||
2113 | } |
||
2114 | if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */ |
||
2115 | outl(0, ioaddr + DownListPtr); |
||
2116 | for (i = 0; i < TX_RING_SIZE; i++) |
||
2117 | if (vp->tx_skbuff[i]) { |
||
2118 | dev_kfree_skb(vp->tx_skbuff[i]); |
||
2119 | vp->tx_skbuff[i] = 0; |
||
2120 | } |
||
2121 | } |
||
2122 | |||
2123 | if (vp->enable_wol && (vp->capabilities & CapPwrMgmt)) |
||
2124 | acpi_set_WOL(dev); |
||
2125 | MOD_DEC_USE_COUNT; |
||
2126 | |||
2127 | return 0; |
||
2128 | } |
||
2129 | |||
2130 | static struct net_device_stats *vortex_get_stats(struct device *dev) |
||
2131 | { |
||
2132 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2133 | unsigned long flags; |
||
2134 | |||
2135 | if (dev->start) { |
||
2136 | spin_lock_irqsave(&vp->lock, flags); |
||
2137 | update_stats(dev->base_addr, dev); |
||
2138 | spin_unlock_irqrestore(&vp->lock, flags); |
||
2139 | } |
||
2140 | return &vp->stats; |
||
2141 | } |
||
2142 | |||
2143 | /* Update statistics. |
||
2144 | Unlike with the EL3 we need not worry about interrupts changing |
||
2145 | the window setting from underneath us, but we must still guard |
||
2146 | against a race condition with a StatsUpdate interrupt updating the |
||
2147 | table. This is done by checking that the ASM (!) code generated uses |
||
2148 | atomic updates with '+='. |
||
2149 | */ |
||
2150 | static void update_stats(long ioaddr, struct device *dev) |
||
2151 | { |
||
2152 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2153 | |||
2154 | /* Unlike the 3c5x9 we need not turn off stats updates while reading. */ |
||
2155 | /* Switch to the stats window, and read everything. */ |
||
2156 | EL3WINDOW(6); |
||
2157 | vp->stats.tx_carrier_errors += inb(ioaddr + 0); |
||
2158 | vp->stats.tx_heartbeat_errors += inb(ioaddr + 1); |
||
2159 | /* Multiple collisions. */ inb(ioaddr + 2); |
||
2160 | vp->stats.collisions += inb(ioaddr + 3); |
||
2161 | vp->stats.tx_window_errors += inb(ioaddr + 4); |
||
2162 | vp->stats.rx_fifo_errors += inb(ioaddr + 5); |
||
2163 | vp->stats.tx_packets += inb(ioaddr + 6); |
||
2164 | vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4; |
||
2165 | /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */ |
||
2166 | /* Tx deferrals */ inb(ioaddr + 8); |
||
2167 | /* Don't bother with register 9, an extension of registers 6&7. |
||
2168 | If we do use the 6&7 values the atomic update assumption above |
||
2169 | is invalid. */ |
||
2170 | inw(ioaddr + 10); /* Total Rx and Tx octets. */ |
||
2171 | inw(ioaddr + 12); |
||
2172 | /* New: On the Vortex we must also clear the BadSSD counter. */ |
||
2173 | EL3WINDOW(4); |
||
2174 | inb(ioaddr + 12); |
||
2175 | |||
2176 | /* We change back to window 7 (not 1) with the Vortex. */ |
||
2177 | EL3WINDOW(7); |
||
2178 | return; |
||
2179 | } |
||
2180 | |||
2181 | static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd) |
||
2182 | { |
||
2183 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2184 | long ioaddr = dev->base_addr; |
||
2185 | u16 *data = (u16 *)&rq->ifr_data; |
||
2186 | int phy = vp->phys[0] & 0x1f; |
||
2187 | int retval; |
||
2188 | unsigned long flags; |
||
2189 | |||
2190 | spin_lock_irqsave(&vp->lock, flags); |
||
2191 | |||
2192 | switch(cmd) { |
||
2193 | case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ |
||
2194 | data[0] = phy; |
||
2195 | case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ |
||
2196 | EL3WINDOW(4); |
||
2197 | data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f); |
||
2198 | retval = 0; |
||
2199 | break; |
||
2200 | case SIOCDEVPRIVATE+2: /* Write the specified MII register */ |
||
2201 | if (!capable(CAP_NET_ADMIN)) { |
||
2202 | retval = -EPERM; |
||
2203 | } else { |
||
2204 | EL3WINDOW(4); |
||
2205 | mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]); |
||
2206 | retval = 0; |
||
2207 | } |
||
2208 | break; |
||
2209 | default: |
||
2210 | retval = -EOPNOTSUPP; |
||
2211 | } |
||
2212 | |||
2213 | spin_unlock_irqrestore(&vp->lock, flags); |
||
2214 | return retval; |
||
2215 | } |
||
2216 | |||
2217 | /* Pre-Cyclone chips have no documented multicast filter, so the only |
||
2218 | multicast setting is to receive all multicast frames. At least |
||
2219 | the chip has a very clean way to set the mode, unlike many others. */ |
||
2220 | static void set_rx_mode(struct device *dev) |
||
2221 | { |
||
2222 | long ioaddr = dev->base_addr; |
||
2223 | int new_mode; |
||
2224 | |||
2225 | if (dev->flags & IFF_PROMISC) { |
||
2226 | if (vortex_debug > 0) |
||
2227 | printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name); |
||
2228 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm; |
||
2229 | } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) { |
||
2230 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast; |
||
2231 | } else |
||
2232 | new_mode = SetRxFilter | RxStation | RxBroadcast; |
||
2233 | |||
2234 | outw(new_mode, ioaddr + EL3_CMD); |
||
2235 | } |
||
2236 | |||
2237 | |||
2238 | /* MII transceiver control section. |
||
2239 | Read and write the MII registers using software-generated serial |
||
2240 | MDIO protocol. See the MII specifications or DP83840A data sheet |
||
2241 | for details. */ |
||
2242 | |||
2243 | /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually |
||
2244 | met by back-to-back PCI I/O cycles, but we insert a delay to avoid |
||
2245 | "overclocking" issues. */ |
||
2246 | #define mdio_delay() inl(mdio_addr) |
||
2247 | |||
2248 | #define MDIO_SHIFT_CLK 0x01 |
||
2249 | #define MDIO_DIR_WRITE 0x04 |
||
2250 | #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) |
||
2251 | #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) |
||
2252 | #define MDIO_DATA_READ 0x02 |
||
2253 | #define MDIO_ENB_IN 0x00 |
||
2254 | |||
2255 | /* Generate the preamble required for initial synchronization and |
||
2256 | a few older transceivers. */ |
||
2257 | static void mdio_sync(long ioaddr, int bits) |
||
2258 | { |
||
2259 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2260 | |||
2261 | /* Establish sync by sending at least 32 logic ones. */ |
||
2262 | while (-- bits >= 0) { |
||
2263 | outw(MDIO_DATA_WRITE1, mdio_addr); |
||
2264 | mdio_delay(); |
||
2265 | outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); |
||
2266 | mdio_delay(); |
||
2267 | } |
||
2268 | } |
||
2269 | |||
2270 | static int mdio_read(long ioaddr, int phy_id, int location) |
||
2271 | { |
||
2272 | int i; |
||
2273 | int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; |
||
2274 | unsigned int retval = 0; |
||
2275 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2276 | |||
2277 | if (mii_preamble_required) |
||
2278 | mdio_sync(ioaddr, 32); |
||
2279 | |||
2280 | /* Shift the read command bits out. */ |
||
2281 | for (i = 14; i >= 0; i--) { |
||
2282 | int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
||
2283 | outw(dataval, mdio_addr); |
||
2284 | mdio_delay(); |
||
2285 | outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
||
2286 | mdio_delay(); |
||
2287 | } |
||
2288 | /* Read the two transition, 16 data, and wire-idle bits. */ |
||
2289 | for (i = 19; i > 0; i--) { |
||
2290 | outw(MDIO_ENB_IN, mdio_addr); |
||
2291 | mdio_delay(); |
||
2292 | retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); |
||
2293 | outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
||
2294 | mdio_delay(); |
||
2295 | } |
||
2296 | #if 0 |
||
2297 | return (retval>>1) & 0x1ffff; |
||
2298 | #else |
||
2299 | return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; |
||
2300 | #endif |
||
2301 | } |
||
2302 | |||
2303 | static void mdio_write(long ioaddr, int phy_id, int location, int value) |
||
2304 | { |
||
2305 | int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; |
||
2306 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2307 | int i; |
||
2308 | |||
2309 | if (mii_preamble_required) |
||
2310 | mdio_sync(ioaddr, 32); |
||
2311 | |||
2312 | /* Shift the command bits out. */ |
||
2313 | for (i = 31; i >= 0; i--) { |
||
2314 | int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
||
2315 | outw(dataval, mdio_addr); |
||
2316 | mdio_delay(); |
||
2317 | outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
||
2318 | mdio_delay(); |
||
2319 | } |
||
2320 | /* Leave the interface idle. */ |
||
2321 | for (i = 1; i >= 0; i--) { |
||
2322 | outw(MDIO_ENB_IN, mdio_addr); |
||
2323 | mdio_delay(); |
||
2324 | outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
||
2325 | mdio_delay(); |
||
2326 | } |
||
2327 | |||
2328 | return; |
||
2329 | } |
||
2330 | |||
2331 | /* ACPI: Advanced Configuration and Power Interface. */ |
||
2332 | /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */ |
||
2333 | static void acpi_set_WOL(struct device *dev) |
||
2334 | { |
||
2335 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
2336 | long ioaddr = dev->base_addr; |
||
2337 | |||
2338 | /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */ |
||
2339 | EL3WINDOW(7); |
||
2340 | outw(2, ioaddr + 0x0c); |
||
2341 | /* The RxFilter must accept the WOL frames. */ |
||
2342 | outw(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD); |
||
2343 | outw(RxEnable, ioaddr + EL3_CMD); |
||
2344 | /* Change the power state to D3; RxEnable doesn't take effect. */ |
||
2345 | pci20to26_write_config_word(vp->pci_bus, vp->pci_devfn, 0xe0, 0x8103); |
||
2346 | } |
||
2347 | |||
2348 | /* Change from D3 (sleep) to D0 (active). |
||
2349 | Problem: The Cyclone forgets all PCI config info during the transition! */ |
||
2350 | static void acpi_wake(int bus, int devfn) |
||
2351 | { |
||
2352 | u32 base0, base1, romaddr; |
||
2353 | u16 pci_command, pwr_command; |
||
2354 | u8 pci_latency, pci_cacheline, irq; |
||
2355 | |||
2356 | pci20to26_read_config_word(bus, devfn, 0xe0, &pwr_command); |
||
2357 | if ((pwr_command & 3) == 0) |
||
2358 | return; |
||
2359 | pci20to26_read_config_word( bus, devfn, PCI_COMMAND, &pci_command); |
||
2360 | pci20to26_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &base0); |
||
2361 | pci20to26_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_1, &base1); |
||
2362 | pci20to26_read_config_dword(bus, devfn, PCI_ROM_ADDRESS, &romaddr); |
||
2363 | pci20to26_read_config_byte( bus, devfn, PCI_LATENCY_TIMER, &pci_latency); |
||
2364 | pci20to26_read_config_byte( bus, devfn, PCI_CACHE_LINE_SIZE, &pci_cacheline); |
||
2365 | pci20to26_read_config_byte( bus, devfn, PCI_INTERRUPT_LINE, &irq); |
||
2366 | |||
2367 | pci20to26_write_config_word( bus, devfn, 0xe0, 0x0000); |
||
2368 | pci20to26_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, base0); |
||
2369 | pci20to26_write_config_dword(bus, devfn, PCI_BASE_ADDRESS_1, base1); |
||
2370 | pci20to26_write_config_dword(bus, devfn, PCI_ROM_ADDRESS, romaddr); |
||
2371 | pci20to26_write_config_byte( bus, devfn, PCI_INTERRUPT_LINE, irq); |
||
2372 | pci20to26_write_config_byte( bus, devfn, PCI_LATENCY_TIMER, pci_latency); |
||
2373 | pci20to26_write_config_byte( bus, devfn, PCI_CACHE_LINE_SIZE, pci_cacheline); |
||
2374 | pci20to26_write_config_word( bus, devfn, PCI_COMMAND, pci_command | 5); |
||
2375 | } |
||
2376 | |||
2377 | |||
2378 | #ifdef MODULE |
||
2379 | void cleanup_module(void) |
||
2380 | { |
||
2381 | struct device *next_dev; |
||
2382 | |||
2383 | /* No need to check MOD_IN_USE, as sys_delete_module() checks. */ |
||
2384 | while (root_vortex_dev) { |
||
2385 | struct vortex_private *vp=(void *)(root_vortex_dev->priv); |
||
2386 | int drv_flags = pci_tbl[vp->chip_id].drv_flags; |
||
2387 | next_dev = vp->next_module; |
||
2388 | unregister_netdev(root_vortex_dev); |
||
2389 | outw((drv_flags & EEPROM_NORESET) ? (TotalReset|0x10) : TotalReset, |
||
2390 | root_vortex_dev->base_addr + EL3_CMD); |
||
2391 | release_region(root_vortex_dev->base_addr, |
||
2392 | pci_tbl[vp->chip_id].io_size); |
||
2393 | kfree(root_vortex_dev); |
||
2394 | kfree(vp->priv_addr); |
||
2395 | root_vortex_dev = next_dev; |
||
2396 | } |
||
2397 | } |
||
2398 | |||
2399 | #endif /* MODULE */ |
||
2400 | |||
2401 | /* |
||
2402 | * Local variables: |
||
2403 | * c-indent-level: 4 |
||
2404 | * c-basic-offset: 4 |
||
2405 | * tab-width: 4 |
||
2406 | * End: |
||
2407 | */ |