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587 giacomo 1
/*
2
 *      drivers/pci/setup-bus.c
3
 *
4
 * Extruded from code written by
5
 *      Dave Rusling (david.rusling@reo.mts.dec.com)
6
 *      David Mosberger (davidm@cs.arizona.edu)
7
 *      David Miller (davem@redhat.com)
8
 *
9
 * Support routines for initializing a PCI subsystem.
10
 */
11
 
12
/*
13
 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14
 *           PCI-PCI bridges cleanup, sorted resource allocation.
15
 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16
 *           Converted to allocation in 3 passes, which gives
17
 *           tighter packing. Prefetchable range support.
18
 */
19
 
20
#include <linuxcomp.h>
21
 
22
#include <linux/init.h>
23
#include <linux/kernel.h>
24
#include <linux/module.h>
25
#include <linux/pci.h>
26
#include <linux/errno.h>
27
#include <linux/ioport.h>
28
#include <linux/cache.h>
29
#include <linux/slab.h>
30
 
31
 
32
#define DEBUG_CONFIG 0
33
#if DEBUG_CONFIG
34
# define DBGC(args)     printk args
35
#else
36
# define DBGC(args)
37
#endif
38
 
39
#define ROUND_UP(x, a)          (((x) + (a) - 1) & ~((a) - 1))
40
 
41
/*
42
 * FIXME: IO should be max 256 bytes.  However, since we may
43
 * have a P2P bridge below a cardbus bridge, we need 4K.
44
 */
45
#define CARDBUS_IO_SIZE         (4096)
46
#define CARDBUS_MEM_SIZE        (32*1024*1024)
47
 
48
static int __devinit
49
pbus_assign_resources_sorted(struct pci_bus *bus)
50
{
51
        struct pci_dev *dev;
52
        struct resource *res;
53
        struct resource_list head, *list, *tmp;
54
        int idx, found_vga = 0;
55
 
56
        head.next = NULL;
57
        list_for_each_entry(dev, &bus->devices, bus_list) {
58
                u16 class = dev->class >> 8;
59
 
60
                if (class == PCI_CLASS_DISPLAY_VGA
61
                                || class == PCI_CLASS_NOT_DEFINED_VGA)
62
                        found_vga = 1;
63
 
64
                pdev_sort_resources(dev, &head);
65
        }
66
 
67
        for (list = head.next; list;) {
68
                res = list->res;
69
                idx = res - &list->dev->resource[0];
70
                pci_assign_resource(list->dev, idx);
71
                tmp = list;
72
                list = list->next;
73
                kfree(tmp);
74
        }
75
 
76
        return found_vga;
77
}
78
 
79
static void __devinit
80
pci_setup_cardbus(struct pci_bus *bus)
81
{
82
        struct pci_dev *bridge = bus->self;
83
        struct pci_bus_region region;
84
 
85
        printk("PCI: Bus %d, cardbus bridge: %s\n",
86
                bus->number, pci_name(bridge));
87
 
88
        pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
89
        if (bus->resource[0]->flags & IORESOURCE_IO) {
90
                /*
91
                 * The IO resource is allocated a range twice as large as it
92
                 * would normally need.  This allows us to set both IO regs.
93
                 */
94
                printk("  IO window: %08lx-%08lx\n",
95
                        region.start, region.end);
96
                pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
97
                                        region.start);
98
                pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
99
                                        region.end);
100
        }
101
 
102
        pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
103
        if (bus->resource[1]->flags & IORESOURCE_IO) {
104
                printk("  IO window: %08lx-%08lx\n",
105
                        region.start, region.end);
106
                pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
107
                                        region.start);
108
                pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
109
                                        region.end);
110
        }
111
 
112
        pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
113
        if (bus->resource[2]->flags & IORESOURCE_MEM) {
114
                printk("  PREFETCH window: %08lx-%08lx\n",
115
                        region.start, region.end);
116
                pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
117
                                        region.start);
118
                pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
119
                                        region.end);
120
        }
121
 
122
        pcibios_resource_to_bus(bridge, &region, bus->resource[3]);
123
        if (bus->resource[3]->flags & IORESOURCE_MEM) {
124
                printk("  MEM window: %08lx-%08lx\n",
125
                        region.start, region.end);
126
                pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
127
                                        region.start);
128
                pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
129
                                        region.end);
130
        }
131
}
132
 
133
/* Initialize bridges with base/limit values we have collected.
134
   PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
135
   requires that if there is no I/O ports or memory behind the
136
   bridge, corresponding range must be turned off by writing base
137
   value greater than limit to the bridge's base/limit registers.
138
 
139
   Note: care must be taken when updating I/O base/limit registers
140
   of bridges which support 32-bit I/O. This update requires two
141
   config space writes, so it's quite possible that an I/O window of
142
   the bridge will have some undesirable address (e.g. 0) after the
143
   first write. Ditto 64-bit prefetchable MMIO.  */
144
static void __devinit
145
pci_setup_bridge(struct pci_bus *bus)
146
{
147
        struct pci_dev *bridge = bus->self;
148
        struct pci_bus_region region;
149
        u32 l, io_upper16;
150
 
151
        DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n",
152
                        bus->number, pci_name(bridge)));
153
 
154
        /* Set up the top and bottom of the PCI I/O segment for this bus. */
155
        pcibios_resource_to_bus(bridge, &region, bus->resource[0]);
156
        if (bus->resource[0]->flags & IORESOURCE_IO) {
157
                pci_read_config_dword(bridge, PCI_IO_BASE, &l);
158
                l &= 0xffff0000;
159
                l |= (region.start >> 8) & 0x00f0;
160
                l |= region.end & 0xf000;
161
                /* Set up upper 16 bits of I/O base/limit. */
162
                io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
163
                DBGC((KERN_INFO "  IO window: %04lx-%04lx\n",
164
                                region.start, region.end));
165
        }
166
        else {
167
                /* Clear upper 16 bits of I/O base/limit. */
168
                io_upper16 = 0;
169
                l = 0x00f0;
170
                DBGC((KERN_INFO "  IO window: disabled.\n"));
171
        }
172
        /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
173
        pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
174
        /* Update lower 16 bits of I/O base/limit. */
175
        pci_write_config_dword(bridge, PCI_IO_BASE, l);
176
        /* Update upper 16 bits of I/O base/limit. */
177
        pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
178
 
179
        /* Set up the top and bottom of the PCI Memory segment
180
           for this bus. */
181
        pcibios_resource_to_bus(bridge, &region, bus->resource[1]);
182
        if (bus->resource[1]->flags & IORESOURCE_MEM) {
183
                l = (region.start >> 16) & 0xfff0;
184
                l |= region.end & 0xfff00000;
185
                DBGC((KERN_INFO "  MEM window: %08lx-%08lx\n",
186
                                region.start, region.end));
187
        }
188
        else {
189
                l = 0x0000fff0;
190
                DBGC((KERN_INFO "  MEM window: disabled.\n"));
191
        }
192
        pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
193
 
194
        /* Clear out the upper 32 bits of PREF limit.
195
           If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
196
           disables PREF range, which is ok. */
197
        pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
198
 
199
        /* Set up PREF base/limit. */
200
        pcibios_resource_to_bus(bridge, &region, bus->resource[2]);
201
        if (bus->resource[2]->flags & IORESOURCE_PREFETCH) {
202
                l = (region.start >> 16) & 0xfff0;
203
                l |= region.end & 0xfff00000;
204
                DBGC((KERN_INFO "  PREFETCH window: %08lx-%08lx\n",
205
                                region.start, region.end));
206
        }
207
        else {
208
                l = 0x0000fff0;
209
                DBGC((KERN_INFO "  PREFETCH window: disabled.\n"));
210
        }
211
        pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
212
 
213
        /* Clear out the upper 32 bits of PREF base. */
214
        pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0);
215
 
216
        /* Check if we have VGA behind the bridge.
217
           Enable ISA in either case (FIXME!). */
218
        l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04;
219
        pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l);
220
}
221
 
222
/* Check whether the bridge supports optional I/O and
223
   prefetchable memory ranges. If not, the respective
224
   base/limit registers must be read-only and read as 0. */
225
static void __devinit
226
pci_bridge_check_ranges(struct pci_bus *bus)
227
{
228
        u16 io;
229
        u32 pmem;
230
        struct pci_dev *bridge = bus->self;
231
        struct resource *b_res;
232
 
233
        b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
234
        b_res[1].flags |= IORESOURCE_MEM;
235
 
236
        pci_read_config_word(bridge, PCI_IO_BASE, &io);
237
        if (!io) {
238
                pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0);
239
                pci_read_config_word(bridge, PCI_IO_BASE, &io);
240
                pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
241
        }
242
        if (io)
243
                b_res[0].flags |= IORESOURCE_IO;
244
        /*  DECchip 21050 pass 2 errata: the bridge may miss an address
245
            disconnect boundary by one PCI data phase.
246
            Workaround: do not use prefetching on this device. */
247
        if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
248
                return;
249
        pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
250
        if (!pmem) {
251
                pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
252
                                               0xfff0fff0);
253
                pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
254
                pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
255
        }
256
        if (pmem)
257
                b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
258
}
259
 
260
/* Helper function for sizing routines: find first available
261
   bus resource of a given type. Note: we intentionally skip
262
   the bus resources which have already been assigned (that is,
263
   have non-NULL parent resource). */
264
static struct resource * __devinit
265
find_free_bus_resource(struct pci_bus *bus, unsigned long type)
266
{
267
        int i;
268
        struct resource *r;
269
        unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
270
                                  IORESOURCE_PREFETCH;
271
 
272
        for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) {
273
                r = bus->resource[i];
274
                if (r && (r->flags & type_mask) == type && !r->parent)
275
                        return r;
276
        }
277
        return NULL;
278
}
279
 
280
/* Sizing the IO windows of the PCI-PCI bridge is trivial,
281
   since these windows have 4K granularity and the IO ranges
282
   of non-bridge PCI devices are limited to 256 bytes.
283
   We must be careful with the ISA aliasing though. */
284
static void __devinit
285
pbus_size_io(struct pci_bus *bus)
286
{
287
        struct pci_dev *dev;
288
        struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO);
289
        unsigned long size = 0, size1 = 0;
290
 
291
        if (!b_res)
292
                return;
293
 
294
        list_for_each_entry(dev, &bus->devices, bus_list) {
295
                int i;
296
 
297
                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
298
                        struct resource *r = &dev->resource[i];
299
                        unsigned long r_size;
300
 
301
                        if (r->parent || !(r->flags & IORESOURCE_IO))
302
                                continue;
303
                        r_size = r->end - r->start + 1;
304
 
305
                        if (r_size < 0x400)
306
                                /* Might be re-aligned for ISA */
307
                                size += r_size;
308
                        else
309
                                size1 += r_size;
310
                }
311
        }
312
/* To be fixed in 2.5: we should have sort of HAVE_ISA
313
   flag in the struct pci_bus. */
314
#if defined(CONFIG_ISA) || defined(CONFIG_EISA)
315
        size = (size & 0xff) + ((size & ~0xffUL) << 2);
316
#endif
317
        size = ROUND_UP(size + size1, 4096);
318
        if (!size) {
319
                b_res->flags = 0;
320
                return;
321
        }
322
        /* Alignment of the IO window is always 4K */
323
        b_res->start = 4096;
324
        b_res->end = b_res->start + size - 1;
325
}
326
 
327
/* Calculate the size of the bus and minimal alignment which
328
   guarantees that all child resources fit in this size. */
329
static int __devinit
330
pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type)
331
{
332
        struct pci_dev *dev;
333
        unsigned long min_align, align, size;
334
        unsigned long aligns[12];       /* Alignments from 1Mb to 2Gb */
335
        int order, max_order;
336
        struct resource *b_res = find_free_bus_resource(bus, type);
337
 
338
        if (!b_res)
339
                return 0;
340
 
341
        memset(aligns, 0, sizeof(aligns));
342
        max_order = 0;
343
        size = 0;
344
 
345
        list_for_each_entry(dev, &bus->devices, bus_list) {
346
                int i;
347
 
348
                for (i = 0; i < PCI_NUM_RESOURCES; i++) {
349
                        struct resource *r = &dev->resource[i];
350
                        unsigned long r_size;
351
 
352
                        if (r->parent || (r->flags & mask) != type)
353
                                continue;
354
                        r_size = r->end - r->start + 1;
355
                        /* For bridges size != alignment */
356
                        align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start;
357
                        order = __ffs(align) - 20;
358
                        if (order > 11) {
359
                                printk(KERN_WARNING "PCI: region %s/%d "
360
                                       "too large: %lx-%lx\n",
361
                                       pci_name(dev), i, r->start, r->end);
362
                                r->flags = 0;
363
                                continue;
364
                        }
365
                        size += r_size;
366
                        if (order < 0)
367
                                order = 0;
368
                        /* Exclude ranges with size > align from
369
                           calculation of the alignment. */
370
                        if (r_size == align)
371
                                aligns[order] += align;
372
                        if (order > max_order)
373
                                max_order = order;
374
                }
375
        }
376
 
377
        align = 0;
378
        min_align = 0;
379
        for (order = 0; order <= max_order; order++) {
380
                unsigned long align1 = 1UL << (order + 20);
381
 
382
                if (!align)
383
                        min_align = align1;
384
                else if (ROUND_UP(align + min_align, min_align) < align1)
385
                        min_align = align1 >> 1;
386
                align += aligns[order];
387
        }
388
        size = ROUND_UP(size, min_align);
389
        if (!size) {
390
                b_res->flags = 0;
391
                return 1;
392
        }
393
        b_res->start = min_align;
394
        b_res->end = size + min_align - 1;
395
        return 1;
396
}
397
 
398
static void __devinit
399
pci_bus_size_cardbus(struct pci_bus *bus)
400
{
401
        struct pci_dev *bridge = bus->self;
402
        struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
403
        u16 ctrl;
404
 
405
        /*
406
         * Reserve some resources for CardBus.  We reserve
407
         * a fixed amount of bus space for CardBus bridges.
408
         */
409
        b_res[0].start = CARDBUS_IO_SIZE;
410
        b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1;
411
        b_res[0].flags |= IORESOURCE_IO;
412
 
413
        b_res[1].start = CARDBUS_IO_SIZE;
414
        b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1;
415
        b_res[1].flags |= IORESOURCE_IO;
416
 
417
        /*
418
         * Check whether prefetchable memory is supported
419
         * by this bridge.
420
         */
421
        pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
422
        if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
423
                ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
424
                pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
425
                pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
426
        }
427
 
428
        /*
429
         * If we have prefetchable memory support, allocate
430
         * two regions.  Otherwise, allocate one region of
431
         * twice the size.
432
         */
433
        if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
434
                b_res[2].start = CARDBUS_MEM_SIZE;
435
                b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1;
436
                b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
437
 
438
                b_res[3].start = CARDBUS_MEM_SIZE;
439
                b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1;
440
                b_res[3].flags |= IORESOURCE_MEM;
441
        } else {
442
                b_res[3].start = CARDBUS_MEM_SIZE * 2;
443
                b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1;
444
                b_res[3].flags |= IORESOURCE_MEM;
445
        }
446
}
447
 
448
void __devinit
449
pci_bus_size_bridges(struct pci_bus *bus)
450
{
451
        struct pci_dev *dev;
452
        unsigned long mask, prefmask;
453
 
454
        list_for_each_entry(dev, &bus->devices, bus_list) {
455
                struct pci_bus *b = dev->subordinate;
456
                if (!b)
457
                        continue;
458
 
459
                switch (dev->class >> 8) {
460
                case PCI_CLASS_BRIDGE_CARDBUS:
461
                        pci_bus_size_cardbus(b);
462
                        break;
463
 
464
                case PCI_CLASS_BRIDGE_PCI:
465
                default:
466
                        pci_bus_size_bridges(b);
467
                        break;
468
                }
469
        }
470
 
471
        /* The root bus? */
472
        if (!bus->self)
473
                return;
474
 
475
        switch (bus->self->class >> 8) {
476
        case PCI_CLASS_BRIDGE_CARDBUS:
477
                /* don't size cardbuses yet. */
478
                break;
479
 
480
        case PCI_CLASS_BRIDGE_PCI:
481
                pci_bridge_check_ranges(bus);
482
        default:
483
                pbus_size_io(bus);
484
                /* If the bridge supports prefetchable range, size it
485
                   separately. If it doesn't, or its prefetchable window
486
                   has already been allocated by arch code, try
487
                   non-prefetchable range for both types of PCI memory
488
                   resources. */
489
                mask = IORESOURCE_MEM;
490
                prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
491
                if (pbus_size_mem(bus, prefmask, prefmask))
492
                        mask = prefmask; /* Success, size non-prefetch only. */
493
                pbus_size_mem(bus, mask, IORESOURCE_MEM);
494
                break;
495
        }
496
}
497
EXPORT_SYMBOL(pci_bus_size_bridges);
498
 
499
void __devinit
500
pci_bus_assign_resources(struct pci_bus *bus)
501
{
502
        struct pci_bus *b;
503
        int found_vga = pbus_assign_resources_sorted(bus);
504
        struct pci_dev *dev;
505
 
506
        if (found_vga) {
507
                /* Propagate presence of the VGA to upstream bridges */
508
                for (b = bus; b->parent; b = b->parent) {
509
                        b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA;
510
                }
511
        }
512
        list_for_each_entry(dev, &bus->devices, bus_list) {
513
                b = dev->subordinate;
514
                if (!b)
515
                        continue;
516
 
517
                pci_bus_assign_resources(b);
518
 
519
                switch (dev->class >> 8) {
520
                case PCI_CLASS_BRIDGE_PCI:
521
                        pci_setup_bridge(b);
522
                        break;
523
 
524
                case PCI_CLASS_BRIDGE_CARDBUS:
525
                        pci_setup_cardbus(b);
526
                        break;
527
 
528
                default:
529
                        printk(KERN_INFO "PCI: not setting up bridge %s "
530
                               "for bus %d\n", pci_name(dev), b->number);
531
                        break;
532
                }
533
        }
534
}
535
EXPORT_SYMBOL(pci_bus_assign_resources);
536
 
537
void __init
538
pci_assign_unassigned_resources(void)
539
{
540
        struct list_head *ln;
541
 
542
        /* Depth first, calculate sizes and alignments of all
543
           subordinate buses. */
544
        for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next)
545
                pci_bus_size_bridges(pci_bus_b(ln));
546
        /* Depth last, allocate resources and update the hardware. */
547
        for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) {
548
                pci_bus_assign_resources(pci_bus_b(ln));
549
                pci_enable_bridges(pci_bus_b(ln));
550
        }
551
}