WebSVN - shark - Blame - Rev 1618 - /shark/branches/xen/drivers/pcl833/pcl833.c

Rev	Author	Line No.	Line
658	giacomo	1	/* File name ......... : pcl833.c
		2	* Object ............ : Port per SHARK dei driver del encoder PCL833 della Advantech
		3	* scaricati per DOS al sito della Advantech www.advantech.com
		4	* Author ............ : Cerri Pietro, Fracassi Matteo
		5	* Language .......... : C
		6	* Operative system .. : SHARK
		7	* Creation data ..... : 26/06/2001
		8	* Last modify ....... : 29/06/2001
		9	*/
		10
		11	#include <ll/ll.h>
		12	#include "drivers/pcl833.h"
		13
		14	//Output Registers and Input Registers
		15
		16	int OutReg[16];
		17	int InReg[16];
		18	int Base;
		19
		20	//All fuctions are called through pcl833()
		21
		22	int pcl833(int func, int option);
		23
		24	//Functions
		25
		26	int vCh_SetInputMode(int ChannelNo, int option);
		27	int vCh_SetInputMode(int ChannelNo, int option);
		28	int vCh_SetInputMode(int ChannelNo, int option);
		29	int vCh_DefineResetValue(int ChannelNo, int option);
		30	int vCh_DefineResetValue(int ChannelNo, int option);
		31	int vCh_DefineResetValue(int ChannelNo, int option);
		32	int vCh_SetLatchSource(int ChannelNo, int option);
		33	int vCh_SetLatchSource(int ChannelNo, int option);
		34	int vCh_SetLatchSource(int ChannelNo, int option);
		35	int vCh_IfResetOnLatch(int ChannelNo, int option);
		36	int vCh_IfResetOnLatch(int ChannelNo, int option);
		37	int vCh_IfResetOnLatch(int ChannelNo, int option);
		38	int vLatchWhenOverflow(int option);
		39	int vCounterReset(int option);
		40	int vChooseSysClock(int option);
		41	int vSetCascadeMode(int option);
		42	int vSet16C54TimeBase(int option);
		43	int vSetDI1orTimerInt(int option);
		44	int vSet16C54Divider(int option);
		45	int vCh_Read(int option);
		46	int vStatus_Read(void);
		47	int vOverflow_Read(void);
		48	int vInitialize833(int option);
		49
		50	//::::::::::::::::::::::::::::::::::::::::::::::::::::::::
		51	//: :
		52	//: All fuctions are called through pcl833() :
		53	//: :
		54	//::::::::::::::::::::::::::::::::::::::::::::::::::::::::
		55
		56	int pcl833(int func, int option) {
		57
		58	switch(func) {
		59	case Ch1_SetInputMode : return(vCh_SetInputMode(ch1, option));
		60	case Ch2_SetInputMode : return(vCh_SetInputMode(ch2, option));
		61	case Ch3_SetInputMode : return(vCh_SetInputMode(ch3, option));
		62	case Ch1_DefineResetValue : return(vCh_DefineResetValue(ch1, option));
		63	case Ch2_DefineResetValue : return(vCh_DefineResetValue(ch2, option));
		64	case Ch3_DefineResetValue : return(vCh_DefineResetValue(ch3, option));
		65	case Ch1_SetLatchSource : return(vCh_SetLatchSource(ch1, option));
		66	case Ch2_SetLatchSource : return(vCh_SetLatchSource(ch2, option));
		67	case Ch3_SetLatchSource : return(vCh_SetLatchSource(ch3, option));
		68	case Ch1_IfResetOnLatch : return(vCh_IfResetOnLatch(ch1, option));
		69	case Ch2_IfResetOnLatch : return(vCh_IfResetOnLatch(ch2, option));
		70	case Ch3_IfResetOnLatch : return(vCh_IfResetOnLatch(ch3, option));
		71	case LatchWhenOverflow : return(vLatchWhenOverflow(option));
		72	case CounterReset : return(vCounterReset(option));
		73	case ChooseSysClock : return(vChooseSysClock(option));
		74	case SetCascadeMode : return(vSetCascadeMode(option));
		75	case Set16C54TimeBase : return(vSet16C54TimeBase(option));
		76	case SetDI1orTimerInt : return(vSetDI1orTimerInt(option));
		77	case Set16C54Divider : return(vSet16C54Divider(option));
		78	case Ch_Read : return(vCh_Read(option));
		79	case Status_Read : return(vStatus_Read());
		80	case Overflow_Read : return(vOverflow_Read());
		81	case Initialize833 : return(vInitialize833(option));
		82	default : return(FUNCTION_NUM_ERR);
		83	}
		84	}
		85
		86	//:::::::::::::::::::::::::::::::::::::::::::::::::
		87	//:
		88	//:::::::::::::::::::::::::::::::::::::::::::::::::
		89
		90	int vInitialize833(int option) {
		91
		92	register int i;
		93
		94	Base = option;
		95
		96	for(i = 0; i < 16; i++)
		97	OutReg[i] = InReg[i] = 0;
		98
		99	vCh_SetInputMode(ch1, PclDisable);
		100	vCh_SetInputMode(ch2, PclDisable);
		101	vCh_SetInputMode(ch3, PclDisable);
		102	vCh_DefineResetValue(ch1, start);
		103	vCh_DefineResetValue(ch2, start);
		104	vCh_DefineResetValue(ch3, start);
		105	vCh_SetLatchSource(ch1, SwReadLatch);
		106	vCh_SetLatchSource(ch2, SwReadLatch);
		107	vCh_SetLatchSource(ch3, SwReadLatch);
		108	vCh_IfResetOnLatch(ch1, ResetNo);
		109	vCh_IfResetOnLatch(ch2, ResetNo);
		110	vCh_IfResetOnLatch(ch3, ResetNo);
		111	vLatchWhenOverflow(Latch_Ch1);
		112	vLatchWhenOverflow(Latch_Ch2);
		113	vLatchWhenOverflow(Latch_Ch3);
		114	vCounterReset(Reset_Ch1);
		115	vCounterReset(Reset_Ch2);
		116	vCounterReset(Reset_Ch3);
		117	vChooseSysClock(Sys8MHZ);
		118	vSetCascadeMode(c24bits); //no cascade
		119	vSet16C54TimeBase(tPoint1ms);
		120	vSetDI1orTimerInt(TimerInt);
		121	vSet16C54Divider(0); // 0-255 divider
		122
		123	return(OK);
		124	}
		125
		126	//:::::::::::::::::::::::::::::::::::::::::::::::::
		127	//:
		128	//:::::::::::::::::::::::::::::::::::::::::::::::::
		129
		130	int vCh_SetInputMode(int ChannelNo, int option) {
		131
		132	int OutputReg, PortAddress, RegIndex;
		133
		134	switch(ChannelNo) {
		135	case ch1: PortAddress = Base + 0; RegIndex = 0; break;
		136	case ch2: PortAddress = Base + 1; RegIndex = 1; break;
		137	case ch3: PortAddress = Base + 2; RegIndex = 2; break;
		138	default: return(CHANNEL_NUM_ERR);
		139	}
		140
		141	OutputReg = OutReg[RegIndex] & 0x08;
		142
		143	switch(option) {
		144	case x1:
		145	case x2:
		146	case x4:
		147	case PclDisable:
		148	case TwoPulseIn:
		149	case OnePulseIn: outp(PortAddress, OutputReg \| option); break;
		150	default: return(PARAMETER_ERR);
		151	}
		152
		153	OutReg[RegIndex] = OutputReg \| option;
		154
		155	return(OK);
		156	}
		157
		158	//:::::::::::::::::::::::::::::::::::::::::::::::::
		159	//:
		160	//:::::::::::::::::::::::::::::::::::::::::::::::::
		161
		162	int vCh_DefineResetValue(int ChannelNo, int option) {
		163
		164	int OutputReg, PortAddress, RegIndex;
		165
		166	switch(ChannelNo) {
		167	case ch1: PortAddress = Base + 0; RegIndex = 0; break;
		168	case ch2: PortAddress = Base + 1; RegIndex = 1; break;
		169	case ch3: PortAddress = Base + 2; RegIndex = 2; break;
		170	default: return(CHANNEL_NUM_ERR);
		171	}
		172
		173	OutputReg = OutReg[RegIndex] & 0x07;
		174
		175	switch(option) {
		176	case start:
		177	case middle: outp(PortAddress, OutputReg \| option); break;
		178	default: return(PARAMETER_ERR);
		179	}
		180
		181	OutReg[RegIndex] = OutputReg \| option;
		182
		183	return(OK);
		184	}
		185
		186	//:::::::::::::::::::::::::::::::::::::::::::::::::
		187	//:
		188	//:::::::::::::::::::::::::::::::::::::::::::::::::
		189
		190	int vCh_SetLatchSource(int ChannelNo, int option) {
		191
		192	int OutputReg, PortAddress, RegIndex;
		193
		194	switch(ChannelNo) {
		195	case ch1: PortAddress = Base + 3; RegIndex = 3; break;
		196	case ch2: PortAddress = Base + 4; RegIndex = 4; break;
		197	case ch3: PortAddress = Base + 5; RegIndex = 5; break;
		198	default: return(CHANNEL_NUM_ERR);
		199	}
		200
		201	OutputReg = OutReg[RegIndex] & 0x08;
		202
		203	switch(option) {
		204	case SwReadLatch:
		205	case IndexInLatch:
		206	case DI0Latch:
		207	case DI1Latch:
		208	case TimerLatch: outp(PortAddress, OutputReg \| option); break;
		209	default: return(PARAMETER_ERR);
		210	}
		211
		212	OutReg[RegIndex] = OutputReg \| option;
		213
		214	return(OK);
		215	}
		216
		217	//:::::::::::::::::::::::::::::::::::::::::::::::::
		218	//:
		219	//:::::::::::::::::::::::::::::::::::::::::::::::::
		220
		221	int vCh_IfResetOnLatch(int ChannelNo, int option) {
		222
		223	int OutputReg, PortAddress, RegIndex;
		224
		225	switch(ChannelNo) {
		226	case ch1: PortAddress= Base + 3; RegIndex = 3; break;
		227	case ch2: PortAddress= Base + 4; RegIndex = 4; break;
		228	case ch3: PortAddress= Base + 5; RegIndex = 5; break;
		229	default: return(CHANNEL_NUM_ERR);
		230	}
		231
		232	OutputReg = OutReg[RegIndex] & 0x07;
		233
		234	switch(option) {
		235	case ResetNo:
		236	case ResetYes: outp(PortAddress, OutputReg \| option); break;
		237	default: return(PARAMETER_ERR);
		238	}
		239
		240	OutReg[RegIndex] = OutputReg \| option;
		241
		242	return(OK);
		243	}
		244
		245	//:::::::::::::::::::::::::::::::::::::::::::::::::
		246	//:
		247	//:::::::::::::::::::::::::::::::::::::::::::::::::
		248
		249	int vLatchWhenOverflow(int option) {
		250
		251	switch(option){
		252	case Latch_Ch1: OutReg[6] &= 0x06; break;
		253	case Latch_Ch2: OutReg[6] &= 0x05; break;
		254	case Latch_Ch3: OutReg[6] &= 0x03; break;
		255	case FreeAll: OutReg[6] = 0x07; break;
		256	default: return(PARAMETER_ERR);
		257	}
		258
		259	outp(Base + 6, OutReg[6]);
		260
		261	return(OK);
		262	}
		263
		264
		265	//:::::::::::::::::::::::::::::::::::::::::::::::::
		266	//:
		267	//:::::::::::::::::::::::::::::::::::::::::::::::::
		268
		269	int vCounterReset(int option) {
		270
		271	switch(option) {
		272	case Reset_Ch1: OutReg[7] &= 0x06;
		273	OutReg[7] \|= 0x01;
		274	break;
		275	case Reset_Ch2: OutReg[7] &= 0x05;
		276	OutReg[7] \|= 0x02;
		277	break;
		278	case Reset_Ch3: OutReg[7] &= 0x03;
		279	OutReg[7] \|= 0x04;
		280	break;
		281	case NoneReset: OutReg[7] = 0;
		282	break;
		283	default: return(PARAMETER_ERR);
		284	}
		285
		286	outp(Base + 7, OutReg[7]);
		287
		288	return(OK);
		289	}
		290
		291	//:::::::::::::::::::::::::::::::::::::::::::::::::
		292	//:
		293	//:::::::::::::::::::::::::::::::::::::::::::::::::
		294
		295	int vChooseSysClock(option) {
		296
		297	int OutputReg;
		298
		299	OutputReg = OutReg[8] & 0x0c;
		300
		301	switch(option) {
		302	case Sys8MHZ:
		303	case Sys4MHZ:
		304	case Sys2MHZ: outp(Base + 8, OutputReg \| option); break;
		305	default: return(PARAMETER_ERR);
		306	}
		307
		308	OutReg[8] = OutputReg \| option;
		309
		310	return(OK);
		311	}
		312
		313	//:::::::::::::::::::::::::::::::::::::::::::::::::
		314	//:
		315	//:::::::::::::::::::::::::::::::::::::::::::::::::
		316
		317	int vSetCascadeMode(option) {
		318
		319	int OutputReg;
		320
		321	OutputReg = OutReg[8] & 0x03;
		322
		323	switch(option) {
		324	case c24bits: // no cascade
		325	outp(Base + 8, OutputReg \| option);
		326	break;
		327
		328	case c48bits: // ch1 ch2 cascade
		329	OutReg[1] \|= 0x07; // set ch2 cascade mode
		330	OutReg[0] &= 0x07; // set ch1 reset value '000000'
		331	outp(Base + 1, OutReg[1]);
		332	outp(Base, OutReg[0]);
		333	outp(Base + 8, OutputReg \| option);
		334	vCh_SetInputMode(ch2, cascade);
		335	break;
		336
		337	default:
		338	return(PARAMETER_ERR);
		339	}
		340
		341	OutReg[8] = OutputReg \| option;
		342
		343	return(OK);
		344	}
		345
		346
		347	//:::::::::::::::::::::::::::::::::::::::::::::::::
		348	//:
		349	//:::::::::::::::::::::::::::::::::::::::::::::::::
		350
		351	int vSet16C54TimeBase(option) {
		352
		353	int OutputReg;
		354
		355	OutputReg = OutReg[9] & 0x08;
		356
		357	switch(option) {
		358	case tPoint1ms:
		359	case t1ms:
		360	case t10ms:
		361	case t100ms:
		362	case t1s: outp(Base + 9, OutputReg \| option); break;
		363	default: return(PARAMETER_ERR);
		364	}
		365
		366	OutReg[9] = OutputReg \| option;
		367
		368	return(OK);
		369	}
		370
		371	//:::::::::::::::::::::::::::::::::::::::::::::::::
		372	//:
		373	//:::::::::::::::::::::::::::::::::::::::::::::::::
		374
		375	int vSetDI1orTimerInt(option) {
		376
		377	int OutputReg;
		378
		379	OutputReg = OutReg[9] & 0x07;
		380	switch(option) {
		381	case DI1Int :
		382	case TimerInt : outp(Base + 9, OutputReg \| option); break;
		383	default: return(PARAMETER_ERR);
		384	}
		385
		386	OutReg[9] = OutputReg \| option;
		387
		388	return(OK);
		389	}
		390
		391	//:::::::::::::::::::::::::::::::::::::::::::::::::
		392	//:
		393	//:::::::::::::::::::::::::::::::::::::::::::::::::
		394
		395	int vSet16C54Divider(option) {
		396
		397	outp(Base + 10, option);
		398	OutReg[10] = option;
		399
		400	return(OK);
		401	}
		402
		403
		404	//:::::::::::::::::::::::::::::::::::::::::::::::::
		405	//: READ FUNCTION
		406	//:::::::::::::::::::::::::::::::::::::::::::::::::
		407
		408	int vCh_Read(int ChannelNo) {
		409
		410	switch(ChannelNo) {
		411
		412	case ch1:
		413	InReg[2] = inp(Base + 2);
		414	InReg[0] = inp(Base);
		415	InReg[1] = inp(Base + 1);
		416	break;
		417
		418	case ch2:
		419	InReg[6] = inp(Base + 6);
		420	InReg[4] = inp(Base + 4);
		421	InReg[5] = inp(Base + 5);
		422	break;
		423
		424	case ch3:
		425	InReg[10] = inp(Base + 10);
		426	InReg[8] = inp(Base + 8);
		427	InReg[9] = inp(Base + 9);
		428	break;
		429
		430	default:
		431	return(CHANNEL_NUM_ERR);
		432	}
		433
		434	return(OK);
		435	}
		436
		437
		438	//:::::::::::::::::::::::::::::::::::::::::::::::::
		439	//:
		440	//:::::::::::::::::::::::::::::::::::::::::::::::::
		441
		442	int vOverflow_Read(void) {
		443
		444	InReg[3] = inp(Base + 3);
		445	InReg[7] = inp(Base + 7);
		446	InReg[11] = inp(Base + 11);
		447
		448	return(OK);
		449	}
		450
		451	//:::::::::::::::::::::::::::::::::::::::::::::::::
		452	//:
		453	//:::::::::::::::::::::::::::::::::::::::::::::::::
		454
		455	int vStatus_Read(void) {
		456
		457	InReg[14] = inp(Base + 14);
		458
		459	return(OK);
		460	}

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