Rev 846 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 846 | giacomo | 1 | /* |
| 2 | * OHCI HCD (Host Controller Driver) for USB. |
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| 3 | * |
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| 4 | * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at> |
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| 5 | * (C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net> |
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| 6 | * |
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| 7 | * This file is licenced under the GPL. |
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| 8 | */ |
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| 9 | |||
| 10 | /* |
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| 11 | * OHCI Endpoint Descriptor (ED) ... holds TD queue |
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| 12 | * See OHCI spec, section 4.2 |
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| 13 | * |
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| 14 | * This is a "Queue Head" for those transfers, which is why |
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| 15 | * both EHCI and UHCI call similar structures a "QH". |
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| 16 | */ |
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| 17 | struct ed { |
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| 18 | /* first fields are hardware-specified, le32 */ |
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| 19 | __u32 hwINFO; /* endpoint config bitmap */ |
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| 20 | /* info bits defined by hcd */ |
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| 21 | #define ED_DEQUEUE __constant_cpu_to_le32(1 << 27) |
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| 22 | /* info bits defined by the hardware */ |
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| 23 | #define ED_ISO __constant_cpu_to_le32(1 << 15) |
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| 24 | #define ED_SKIP __constant_cpu_to_le32(1 << 14) |
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| 25 | #define ED_LOWSPEED __constant_cpu_to_le32(1 << 13) |
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| 26 | #define ED_OUT __constant_cpu_to_le32(0x01 << 11) |
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| 27 | #define ED_IN __constant_cpu_to_le32(0x02 << 11) |
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| 28 | __u32 hwTailP; /* tail of TD list */ |
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| 29 | __u32 hwHeadP; /* head of TD list (hc r/w) */ |
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| 30 | #define ED_C __constant_cpu_to_le32(0x02) /* toggle carry */ |
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| 31 | #define ED_H __constant_cpu_to_le32(0x01) /* halted */ |
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| 32 | __u32 hwNextED; /* next ED in list */ |
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| 33 | |||
| 34 | /* rest are purely for the driver's use */ |
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| 35 | dma_addr_t dma; /* addr of ED */ |
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| 36 | struct td *dummy; /* next TD to activate */ |
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| 37 | |||
| 38 | /* host's view of schedule */ |
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| 39 | struct ed *ed_next; /* on schedule or rm_list */ |
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| 40 | struct ed *ed_prev; /* for non-interrupt EDs */ |
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| 41 | struct list_head td_list; /* "shadow list" of our TDs */ |
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| 42 | |||
| 43 | /* create --> IDLE --> OPER --> ... --> IDLE --> destroy |
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| 44 | * usually: OPER --> UNLINK --> (IDLE | OPER) --> ... |
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| 45 | * some special cases : OPER --> IDLE ... |
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| 46 | */ |
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| 47 | u8 state; /* ED_{IDLE,UNLINK,OPER} */ |
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| 48 | #define ED_IDLE 0x00 /* NOT linked to HC */ |
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| 49 | #define ED_UNLINK 0x01 /* being unlinked from hc */ |
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| 50 | #define ED_OPER 0x02 /* IS linked to hc */ |
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| 51 | |||
| 52 | u8 type; /* PIPE_{BULK,...} */ |
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| 53 | |||
| 54 | /* periodic scheduling params (for intr and iso) */ |
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| 55 | u8 branch; |
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| 56 | u16 interval; |
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| 57 | u16 load; |
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| 58 | u16 last_iso; /* iso only */ |
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| 59 | |||
| 60 | /* HC may see EDs on rm_list until next frame (frame_no == tick) */ |
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| 61 | u16 tick; |
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| 62 | } __attribute__ ((aligned(16))); |
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| 63 | |||
| 64 | #define ED_MASK ((u32)~0x0f) /* strip hw status in low addr bits */ |
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| 65 | |||
| 66 | |||
| 67 | /* |
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| 68 | * OHCI Transfer Descriptor (TD) ... one per transfer segment |
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| 69 | * See OHCI spec, sections 4.3.1 (general = control/bulk/interrupt) |
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| 70 | * and 4.3.2 (iso) |
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| 71 | */ |
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| 72 | struct td { |
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| 73 | /* first fields are hardware-specified, le32 */ |
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| 74 | __u32 hwINFO; /* transfer info bitmask */ |
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| 75 | |||
| 76 | /* hwINFO bits for both general and iso tds: */ |
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| 77 | #define TD_CC 0xf0000000 /* condition code */ |
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| 78 | #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f) |
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| 79 | //#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28) |
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| 80 | #define TD_DI 0x00E00000 /* frames before interrupt */ |
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| 81 | #define TD_DI_SET(X) (((X) & 0x07)<< 21) |
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| 82 | /* these two bits are available for definition/use by HCDs in both |
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| 83 | * general and iso tds ... others are available for only one type |
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| 84 | */ |
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| 85 | #define TD_DONE 0x00020000 /* retired to donelist */ |
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| 86 | #define TD_ISO 0x00010000 /* copy of ED_ISO */ |
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| 87 | |||
| 88 | /* hwINFO bits for general tds: */ |
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| 89 | #define TD_EC 0x0C000000 /* error count */ |
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| 90 | #define TD_T 0x03000000 /* data toggle state */ |
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| 91 | #define TD_T_DATA0 0x02000000 /* DATA0 */ |
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| 92 | #define TD_T_DATA1 0x03000000 /* DATA1 */ |
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| 93 | #define TD_T_TOGGLE 0x00000000 /* uses ED_C */ |
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| 94 | #define TD_DP 0x00180000 /* direction/pid */ |
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| 95 | #define TD_DP_SETUP 0x00000000 /* SETUP pid */ |
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| 96 | #define TD_DP_IN 0x00100000 /* IN pid */ |
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| 97 | #define TD_DP_OUT 0x00080000 /* OUT pid */ |
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| 98 | /* 0x00180000 rsvd */ |
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| 99 | #define TD_R 0x00040000 /* round: short packets OK? */ |
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| 100 | |||
| 101 | /* (no hwINFO #defines yet for iso tds) */ |
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| 102 | |||
| 103 | __u32 hwCBP; /* Current Buffer Pointer (or 0) */ |
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| 104 | __u32 hwNextTD; /* Next TD Pointer */ |
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| 105 | __u32 hwBE; /* Memory Buffer End Pointer */ |
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| 106 | |||
| 107 | /* PSW is only for ISO */ |
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| 108 | #define MAXPSW 1 /* hardware allows 8 */ |
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| 109 | __u16 hwPSW [MAXPSW]; |
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| 110 | |||
| 111 | /* rest are purely for the driver's use */ |
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| 112 | __u8 index; |
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| 113 | struct ed *ed; |
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| 114 | struct td *td_hash; /* dma-->td hashtable */ |
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| 115 | struct td *next_dl_td; |
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| 116 | struct urb *urb; |
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| 117 | |||
| 118 | dma_addr_t td_dma; /* addr of this TD */ |
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| 119 | dma_addr_t data_dma; /* addr of data it points to */ |
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| 120 | |||
| 121 | struct list_head td_list; /* "shadow list", TDs on same ED */ |
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| 122 | } __attribute__ ((aligned(32))); /* c/b/i need 16; only iso needs 32 */ |
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| 123 | |||
| 124 | #define TD_MASK ((u32)~0x1f) /* strip hw status in low addr bits */ |
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| 125 | |||
| 126 | /* |
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| 127 | * Hardware transfer status codes -- CC from td->hwINFO or td->hwPSW |
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| 128 | */ |
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| 129 | #define TD_CC_NOERROR 0x00 |
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| 130 | #define TD_CC_CRC 0x01 |
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| 131 | #define TD_CC_BITSTUFFING 0x02 |
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| 132 | #define TD_CC_DATATOGGLEM 0x03 |
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| 133 | #define TD_CC_STALL 0x04 |
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| 134 | #define TD_DEVNOTRESP 0x05 |
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| 135 | #define TD_PIDCHECKFAIL 0x06 |
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| 136 | #define TD_UNEXPECTEDPID 0x07 |
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| 137 | #define TD_DATAOVERRUN 0x08 |
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| 138 | #define TD_DATAUNDERRUN 0x09 |
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| 139 | /* 0x0A, 0x0B reserved for hardware */ |
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| 140 | #define TD_BUFFEROVERRUN 0x0C |
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| 141 | #define TD_BUFFERUNDERRUN 0x0D |
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| 142 | /* 0x0E, 0x0F reserved for HCD */ |
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| 143 | #define TD_NOTACCESSED 0x0F |
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| 144 | |||
| 145 | |||
| 146 | /* map OHCI TD status codes (CC) to errno values */ |
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| 147 | static const int cc_to_error [16] = { |
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| 148 | /* No Error */ 0, |
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| 149 | /* CRC Error */ -EILSEQ, |
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| 150 | /* Bit Stuff */ -EPROTO, |
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| 151 | /* Data Togg */ -EILSEQ, |
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| 152 | /* Stall */ -EPIPE, |
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| 153 | /* DevNotResp */ -ETIMEDOUT, |
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| 154 | /* PIDCheck */ -EPROTO, |
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| 155 | /* UnExpPID */ -EPROTO, |
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| 156 | /* DataOver */ -EOVERFLOW, |
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| 157 | /* DataUnder */ -EREMOTEIO, |
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| 158 | /* (for hw) */ -EIO, |
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| 159 | /* (for hw) */ -EIO, |
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| 160 | /* BufferOver */ -ECOMM, |
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| 161 | /* BuffUnder */ -ENOSR, |
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| 162 | /* (for HCD) */ -EALREADY, |
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| 163 | /* (for HCD) */ -EALREADY |
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| 164 | }; |
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| 165 | |||
| 166 | |||
| 167 | /* |
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| 168 | * The HCCA (Host Controller Communications Area) is a 256 byte |
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| 169 | * structure defined section 4.4.1 of the OHCI spec. The HC is |
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| 170 | * told the base address of it. It must be 256-byte aligned. |
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| 171 | */ |
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| 172 | struct ohci_hcca { |
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| 173 | #define NUM_INTS 32 |
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| 174 | __u32 int_table [NUM_INTS]; /* periodic schedule */ |
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| 175 | __u16 frame_no; /* current frame number */ |
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| 176 | __u16 pad1; /* set to 0 on each frame_no change */ |
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| 177 | __u32 done_head; /* info returned for an interrupt */ |
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| 178 | u8 reserved_for_hc [116]; |
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| 179 | u8 what [4]; /* spec only identifies 252 bytes :) */ |
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| 180 | } __attribute__ ((aligned(256))); |
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| 181 | |||
| 182 | |||
| 183 | /* |
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| 184 | * This is the structure of the OHCI controller's memory mapped I/O region. |
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| 185 | * You must use readl() and writel() (in <asm/io.h>) to access these fields!! |
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| 186 | * Layout is in section 7 (and appendix B) of the spec. |
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| 187 | */ |
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| 188 | struct ohci_regs { |
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| 189 | /* control and status registers (section 7.1) */ |
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| 190 | __u32 revision; |
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| 191 | __u32 control; |
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| 192 | __u32 cmdstatus; |
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| 193 | __u32 intrstatus; |
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| 194 | __u32 intrenable; |
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| 195 | __u32 intrdisable; |
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| 196 | |||
| 197 | /* memory pointers (section 7.2) */ |
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| 198 | __u32 hcca; |
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| 199 | __u32 ed_periodcurrent; |
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| 200 | __u32 ed_controlhead; |
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| 201 | __u32 ed_controlcurrent; |
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| 202 | __u32 ed_bulkhead; |
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| 203 | __u32 ed_bulkcurrent; |
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| 204 | __u32 donehead; |
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| 205 | |||
| 206 | /* frame counters (section 7.3) */ |
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| 207 | __u32 fminterval; |
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| 208 | __u32 fmremaining; |
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| 209 | __u32 fmnumber; |
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| 210 | __u32 periodicstart; |
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| 211 | __u32 lsthresh; |
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| 212 | |||
| 213 | /* Root hub ports (section 7.4) */ |
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| 214 | struct ohci_roothub_regs { |
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| 215 | __u32 a; |
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| 216 | __u32 b; |
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| 217 | __u32 status; |
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| 218 | #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports (RH_A_NDP) */ |
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| 219 | __u32 portstatus [MAX_ROOT_PORTS]; |
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| 220 | } roothub; |
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| 221 | |||
| 222 | /* and optional "legacy support" registers (appendix B) at 0x0100 */ |
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| 223 | |||
| 224 | } __attribute__ ((aligned(32))); |
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| 225 | |||
| 226 | |||
| 227 | /* OHCI CONTROL AND STATUS REGISTER MASKS */ |
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| 228 | |||
| 229 | /* |
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| 230 | * HcControl (control) register masks |
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| 231 | */ |
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| 232 | #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */ |
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| 233 | #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */ |
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| 234 | #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */ |
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| 235 | #define OHCI_CTRL_CLE (1 << 4) /* control list enable */ |
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| 236 | #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */ |
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| 237 | #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */ |
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| 238 | #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */ |
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| 239 | #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */ |
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| 240 | #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */ |
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| 241 | |||
| 242 | /* pre-shifted values for HCFS */ |
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| 243 | # define OHCI_USB_RESET (0 << 6) |
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| 244 | # define OHCI_USB_RESUME (1 << 6) |
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| 245 | # define OHCI_USB_OPER (2 << 6) |
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| 246 | # define OHCI_USB_SUSPEND (3 << 6) |
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| 247 | |||
| 248 | /* |
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| 249 | * HcCommandStatus (cmdstatus) register masks |
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| 250 | */ |
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| 251 | #define OHCI_HCR (1 << 0) /* host controller reset */ |
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| 252 | #define OHCI_CLF (1 << 1) /* control list filled */ |
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| 253 | #define OHCI_BLF (1 << 2) /* bulk list filled */ |
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| 254 | #define OHCI_OCR (1 << 3) /* ownership change request */ |
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| 255 | #define OHCI_SOC (3 << 16) /* scheduling overrun count */ |
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| 256 | |||
| 257 | /* |
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| 258 | * masks used with interrupt registers: |
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| 259 | * HcInterruptStatus (intrstatus) |
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| 260 | * HcInterruptEnable (intrenable) |
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| 261 | * HcInterruptDisable (intrdisable) |
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| 262 | */ |
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| 263 | #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */ |
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| 264 | #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */ |
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| 265 | #define OHCI_INTR_SF (1 << 2) /* start frame */ |
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| 266 | #define OHCI_INTR_RD (1 << 3) /* resume detect */ |
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| 267 | #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */ |
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| 268 | #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */ |
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| 269 | #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */ |
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| 270 | #define OHCI_INTR_OC (1 << 30) /* ownership change */ |
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| 271 | #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */ |
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| 272 | |||
| 273 | |||
| 274 | /* OHCI ROOT HUB REGISTER MASKS */ |
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| 275 | |||
| 276 | /* roothub.portstatus [i] bits */ |
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| 277 | #define RH_PS_CCS 0x00000001 /* current connect status */ |
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| 278 | #define RH_PS_PES 0x00000002 /* port enable status*/ |
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| 279 | #define RH_PS_PSS 0x00000004 /* port suspend status */ |
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| 280 | #define RH_PS_POCI 0x00000008 /* port over current indicator */ |
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| 281 | #define RH_PS_PRS 0x00000010 /* port reset status */ |
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| 282 | #define RH_PS_PPS 0x00000100 /* port power status */ |
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| 283 | #define RH_PS_LSDA 0x00000200 /* low speed device attached */ |
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| 284 | #define RH_PS_CSC 0x00010000 /* connect status change */ |
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| 285 | #define RH_PS_PESC 0x00020000 /* port enable status change */ |
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| 286 | #define RH_PS_PSSC 0x00040000 /* port suspend status change */ |
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| 287 | #define RH_PS_OCIC 0x00080000 /* over current indicator change */ |
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| 288 | #define RH_PS_PRSC 0x00100000 /* port reset status change */ |
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| 289 | |||
| 290 | /* roothub.status bits */ |
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| 291 | #define RH_HS_LPS 0x00000001 /* local power status */ |
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| 292 | #define RH_HS_OCI 0x00000002 /* over current indicator */ |
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| 293 | #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */ |
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| 294 | #define RH_HS_LPSC 0x00010000 /* local power status change */ |
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| 295 | #define RH_HS_OCIC 0x00020000 /* over current indicator change */ |
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| 296 | #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */ |
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| 297 | |||
| 298 | /* roothub.b masks */ |
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| 299 | #define RH_B_DR 0x0000ffff /* device removable flags */ |
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| 300 | #define RH_B_PPCM 0xffff0000 /* port power control mask */ |
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| 301 | |||
| 302 | /* roothub.a masks */ |
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| 303 | #define RH_A_NDP (0xff << 0) /* number of downstream ports */ |
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| 304 | #define RH_A_PSM (1 << 8) /* power switching mode */ |
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| 305 | #define RH_A_NPS (1 << 9) /* no power switching */ |
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| 306 | #define RH_A_DT (1 << 10) /* device type (mbz) */ |
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| 307 | #define RH_A_OCPM (1 << 11) /* over current protection mode */ |
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| 308 | #define RH_A_NOCP (1 << 12) /* no over current protection */ |
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| 309 | #define RH_A_POTPGT (0xff << 24) /* power on to power good time */ |
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| 310 | |||
| 311 | |||
| 312 | /* hcd-private per-urb state */ |
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| 313 | typedef struct urb_priv { |
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| 314 | struct ed *ed; |
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| 315 | __u16 length; // # tds in this request |
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| 316 | __u16 td_cnt; // tds already serviced |
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| 317 | struct td *td [0]; // all TDs in this request |
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| 318 | |||
| 319 | } urb_priv_t; |
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| 320 | |||
| 321 | #define TD_HASH_SIZE 64 /* power'o'two */ |
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| 322 | // sizeof (struct td) ~= 64 == 2^6 ... |
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| 323 | #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 6)) % TD_HASH_SIZE) |
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| 324 | |||
| 325 | |||
| 326 | /* |
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| 327 | * This is the full ohci controller description |
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| 328 | * |
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| 329 | * Note how the "proper" USB information is just |
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| 330 | * a subset of what the full implementation needs. (Linus) |
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| 331 | */ |
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| 332 | |||
| 333 | struct ohci_hcd { |
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| 334 | spinlock_t lock; |
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| 335 | |||
| 336 | /* |
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| 337 | * I/O memory used to communicate with the HC (dma-consistent) |
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| 338 | */ |
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| 339 | struct ohci_regs *regs; |
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| 340 | |||
| 341 | /* |
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| 342 | * main memory used to communicate with the HC (dma-consistent). |
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| 343 | * hcd adds to schedule for a live hc any time, but removals finish |
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| 344 | * only at the start of the next frame. |
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| 345 | */ |
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| 346 | struct ohci_hcca *hcca; |
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| 347 | dma_addr_t hcca_dma; |
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| 348 | |||
| 349 | struct ed *ed_rm_list; /* to be removed */ |
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| 350 | |||
| 351 | struct ed *ed_bulktail; /* last in bulk list */ |
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| 352 | struct ed *ed_controltail; /* last in ctrl list */ |
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| 353 | struct ed *periodic [NUM_INTS]; /* shadow int_table */ |
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| 354 | |||
| 355 | /* |
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| 356 | * memory management for queue data structures |
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| 357 | */ |
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| 358 | struct pci_pool *td_cache; |
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| 359 | struct pci_pool *ed_cache; |
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| 360 | struct td *td_hash [TD_HASH_SIZE]; |
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| 361 | |||
| 362 | /* |
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| 363 | * driver state |
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| 364 | */ |
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| 365 | int load [NUM_INTS]; |
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| 366 | u32 hc_control; /* copy of hc control reg */ |
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| 367 | |||
| 368 | unsigned long flags; /* for HC bugs */ |
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| 369 | #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */ |
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| 370 | #define OHCI_QUIRK_SUPERIO 0x02 /* natsemi */ |
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| 371 | // there are also chip quirks/bugs in init logic |
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| 372 | |||
| 373 | /* |
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| 374 | * framework state |
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| 375 | */ |
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| 376 | struct usb_hcd hcd; |
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| 377 | }; |
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| 378 | |||
| 379 | #define hcd_to_ohci(hcd_ptr) container_of(hcd_ptr, struct ohci_hcd, hcd) |
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| 380 | |||
| 381 | /*-------------------------------------------------------------------------*/ |
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| 382 | |||
| 383 | #ifndef DEBUG |
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| 384 | #define STUB_DEBUG_FILES |
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| 385 | #endif /* DEBUG */ |
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| 386 | |||
| 387 | #define ohci_dbg(ohci, fmt, args...) \ |
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| 388 | dev_dbg ((ohci)->hcd.controller , fmt , ## args ) |
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| 389 | #define ohci_err(ohci, fmt, args...) \ |
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| 390 | dev_err ((ohci)->hcd.controller , fmt , ## args ) |
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| 391 | #define ohci_info(ohci, fmt, args...) \ |
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| 392 | dev_info ((ohci)->hcd.controller , fmt , ## args ) |
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| 393 | #define ohci_warn(ohci, fmt, args...) \ |
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| 394 | dev_warn ((ohci)->hcd.controller , fmt , ## args ) |
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| 395 | |||
| 396 | #ifdef OHCI_VERBOSE_DEBUG |
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| 397 | # define ohci_vdbg ohci_dbg |
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| 398 | #else |
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| 399 | # define ohci_vdbg(ohci, fmt, args...) do { } while (0) |
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| 400 | #endif |
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| 401 |