Rev 489 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
489 | giacomo | 1 | /* |
2 | * |
||
3 | * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200, G400 and G450 |
||
4 | * |
||
5 | * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz> |
||
6 | * |
||
7 | */ |
||
8 | #ifndef __MATROXFB_H__ |
||
9 | #define __MATROXFB_H__ |
||
10 | |||
11 | /* general, but fairly heavy, debugging */ |
||
12 | #undef MATROXFB_DEBUG |
||
13 | |||
14 | /* heavy debugging: */ |
||
15 | /* -- logs putc[s], so everytime a char is displayed, it's logged */ |
||
16 | #undef MATROXFB_DEBUG_HEAVY |
||
17 | |||
18 | /* This one _could_ cause infinite loops */ |
||
19 | /* It _does_ cause lots and lots of messages during idle loops */ |
||
20 | #undef MATROXFB_DEBUG_LOOP |
||
21 | |||
22 | /* Debug register calls, too? */ |
||
23 | #undef MATROXFB_DEBUG_REG |
||
24 | |||
25 | /* Guard accelerator accesses with spin_lock_irqsave... */ |
||
26 | #undef MATROXFB_USE_SPINLOCKS |
||
27 | |||
28 | #include <linux/config.h> |
||
29 | #include <linux/module.h> |
||
30 | #include <linux/kernel.h> |
||
31 | #include <linux/errno.h> |
||
32 | #include <linux/string.h> |
||
33 | #include <linux/mm.h> |
||
34 | #include <linux/tty.h> |
||
35 | #include <linux/slab.h> |
||
36 | #include <linux/delay.h> |
||
37 | #include <linux/fb.h> |
||
38 | #include <linux/selection.h> |
||
39 | #include <linux/ioport.h> |
||
40 | #include <linux/init.h> |
||
41 | #include <linux/timer.h> |
||
42 | #include <linux/pci.h> |
||
43 | #include <linux/spinlock.h> |
||
44 | #include <linux/kd.h> |
||
45 | |||
46 | #include <asm/io.h> |
||
47 | #include <asm/unaligned.h> |
||
48 | #ifdef CONFIG_MTRR |
||
49 | #include <asm/mtrr.h> |
||
50 | #endif |
||
51 | |||
52 | #if defined(CONFIG_PPC_PMAC) |
||
53 | #include <asm/prom.h> |
||
54 | #include <asm/pci-bridge.h> |
||
55 | #include "../macmodes.h" |
||
56 | #endif |
||
57 | |||
58 | /* always compile support for 32MB... It cost almost nothing */ |
||
59 | #define CONFIG_FB_MATROX_32MB |
||
60 | |||
61 | #ifdef MATROXFB_DEBUG |
||
62 | |||
63 | #define DEBUG |
||
64 | #define DBG(x) printk(KERN_DEBUG "matroxfb: %s\n", (x)); |
||
65 | |||
66 | #ifdef MATROXFB_DEBUG_HEAVY |
||
67 | #define DBG_HEAVY(x) DBG(x) |
||
68 | #else /* MATROXFB_DEBUG_HEAVY */ |
||
69 | #define DBG_HEAVY(x) /* DBG_HEAVY */ |
||
70 | #endif /* MATROXFB_DEBUG_HEAVY */ |
||
71 | |||
72 | #ifdef MATROXFB_DEBUG_LOOP |
||
73 | #define DBG_LOOP(x) DBG(x) |
||
74 | #else /* MATROXFB_DEBUG_LOOP */ |
||
75 | #define DBG_LOOP(x) /* DBG_LOOP */ |
||
76 | #endif /* MATROXFB_DEBUG_LOOP */ |
||
77 | |||
78 | #ifdef MATROXFB_DEBUG_REG |
||
79 | #define DBG_REG(x) DBG(x) |
||
80 | #else /* MATROXFB_DEBUG_REG */ |
||
81 | #define DBG_REG(x) /* DBG_REG */ |
||
82 | #endif /* MATROXFB_DEBUG_REG */ |
||
83 | |||
84 | #else /* MATROXFB_DEBUG */ |
||
85 | |||
86 | #define DBG(x) /* DBG */ |
||
87 | #define DBG_HEAVY(x) /* DBG_HEAVY */ |
||
88 | #define DBG_REG(x) /* DBG_REG */ |
||
89 | #define DBG_LOOP(x) /* DBG_LOOP */ |
||
90 | |||
91 | #endif /* MATROXFB_DEBUG */ |
||
92 | |||
93 | #if !defined(__i386__) && !defined(__x86_64__) |
||
94 | #ifndef ioremap_nocache |
||
95 | #define ioremap_nocache(X,Y) ioremap(X,Y) |
||
96 | #endif |
||
97 | #endif |
||
98 | |||
99 | #if defined(__alpha__) || defined(__mc68000__) |
||
100 | #define READx_WORKS |
||
101 | #define MEMCPYTOIO_WORKS |
||
102 | #else |
||
103 | #define READx_FAILS |
||
104 | /* recheck __ppc__, maybe that __ppc__ needs MEMCPYTOIO_WRITEL */ |
||
105 | /* I benchmarked PII/350MHz with G200... MEMCPY, MEMCPYTOIO and WRITEL are on same speed ( <2% diff) */ |
||
106 | /* so that means that G200 speed (or AGP speed?) is our limit... I do not have benchmark to test, how */ |
||
107 | /* much of PCI bandwidth is used during transfers... */ |
||
108 | #if defined(__i386__) || defined(__x86_64__) |
||
109 | #define MEMCPYTOIO_MEMCPY |
||
110 | #else |
||
111 | #define MEMCPYTOIO_WRITEL |
||
112 | #endif |
||
113 | #endif |
||
114 | |||
115 | #if defined(__mc68000__) |
||
116 | #define MAP_BUSTOVIRT |
||
117 | #else |
||
118 | #define MAP_IOREMAP |
||
119 | #endif |
||
120 | |||
121 | #ifdef DEBUG |
||
122 | #define dprintk(X...) printk(X) |
||
123 | #else |
||
124 | #define dprintk(X...) |
||
125 | #endif |
||
126 | |||
127 | #ifndef PCI_SS_VENDOR_ID_SIEMENS_NIXDORF |
||
128 | #define PCI_SS_VENDOR_ID_SIEMENS_NIXDORF 0x110A |
||
129 | #endif |
||
130 | #ifndef PCI_SS_VENDOR_ID_MATROX |
||
131 | #define PCI_SS_VENDOR_ID_MATROX PCI_VENDOR_ID_MATROX |
||
132 | #endif |
||
133 | |||
134 | #ifndef PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP |
||
135 | #define PCI_SS_ID_MATROX_GENERIC 0xFF00 |
||
136 | #define PCI_SS_ID_MATROX_PRODUCTIVA_G100_AGP 0xFF01 |
||
137 | #define PCI_SS_ID_MATROX_MYSTIQUE_G200_AGP 0xFF02 |
||
138 | #define PCI_SS_ID_MATROX_MILLENIUM_G200_AGP 0xFF03 |
||
139 | #define PCI_SS_ID_MATROX_MARVEL_G200_AGP 0xFF04 |
||
140 | #define PCI_SS_ID_MATROX_MGA_G100_PCI 0xFF05 |
||
141 | #define PCI_SS_ID_MATROX_MGA_G100_AGP 0x1001 |
||
142 | #define PCI_SS_ID_MATROX_MILLENNIUM_G400_MAX_AGP 0x2179 |
||
143 | #define PCI_SS_ID_SIEMENS_MGA_G100_AGP 0x001E /* 30 */ |
||
144 | #define PCI_SS_ID_SIEMENS_MGA_G200_AGP 0x0032 /* 50 */ |
||
145 | #endif |
||
146 | |||
147 | #define MX_VISUAL_TRUECOLOR FB_VISUAL_DIRECTCOLOR |
||
148 | #define MX_VISUAL_DIRECTCOLOR FB_VISUAL_TRUECOLOR |
||
149 | #define MX_VISUAL_PSEUDOCOLOR FB_VISUAL_PSEUDOCOLOR |
||
150 | |||
151 | #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16) |
||
152 | |||
153 | /* G-series and Mystique have (almost) same DAC */ |
||
154 | #undef NEED_DAC1064 |
||
155 | #if defined(CONFIG_FB_MATROX_MYSTIQUE) || defined(CONFIG_FB_MATROX_G100) |
||
156 | #define NEED_DAC1064 1 |
||
157 | #endif |
||
158 | |||
159 | typedef struct { |
||
160 | u_int8_t* vaddr; |
||
161 | } vaddr_t; |
||
162 | |||
163 | #ifdef READx_WORKS |
||
164 | static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { |
||
165 | return readb(va.vaddr + offs); |
||
166 | } |
||
167 | |||
168 | static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) { |
||
169 | return readw(va.vaddr + offs); |
||
170 | } |
||
171 | |||
172 | static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { |
||
173 | return readl(va.vaddr + offs); |
||
174 | } |
||
175 | |||
176 | static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { |
||
177 | writeb(value, va.vaddr + offs); |
||
178 | } |
||
179 | |||
180 | static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { |
||
181 | writew(value, va.vaddr + offs); |
||
182 | } |
||
183 | |||
184 | static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { |
||
185 | writel(value, va.vaddr + offs); |
||
186 | } |
||
187 | #else |
||
188 | static inline unsigned int mga_readb(vaddr_t va, unsigned int offs) { |
||
189 | return *(volatile u_int8_t*)(va.vaddr + offs); |
||
190 | } |
||
191 | |||
192 | static inline unsigned int mga_readw(vaddr_t va, unsigned int offs) { |
||
193 | return *(volatile u_int16_t*)(va.vaddr + offs); |
||
194 | } |
||
195 | |||
196 | static inline u_int32_t mga_readl(vaddr_t va, unsigned int offs) { |
||
197 | return *(volatile u_int32_t*)(va.vaddr + offs); |
||
198 | } |
||
199 | |||
200 | static inline void mga_writeb(vaddr_t va, unsigned int offs, u_int8_t value) { |
||
201 | *(volatile u_int8_t*)(va.vaddr + offs) = value; |
||
202 | } |
||
203 | |||
204 | static inline void mga_writew(vaddr_t va, unsigned int offs, u_int16_t value) { |
||
205 | *(volatile u_int16_t*)(va.vaddr + offs) = value; |
||
206 | } |
||
207 | |||
208 | static inline void mga_writel(vaddr_t va, unsigned int offs, u_int32_t value) { |
||
209 | *(volatile u_int32_t*)(va.vaddr + offs) = value; |
||
210 | } |
||
211 | #endif |
||
212 | |||
213 | static inline void mga_memcpy_toio(vaddr_t va, unsigned int offs, const void* src, int len) { |
||
214 | #ifdef MEMCPYTOIO_WORKS |
||
215 | memcpy_toio(va.vaddr + offs, src, len); |
||
216 | #elif defined(MEMCPYTOIO_WRITEL) |
||
217 | #define srcd ((const u_int32_t*)src) |
||
218 | if (offs & 3) { |
||
219 | while (len >= 4) { |
||
220 | mga_writel(va, offs, get_unaligned(srcd++)); |
||
221 | offs += 4; |
||
222 | len -= 4; |
||
223 | } |
||
224 | } else { |
||
225 | while (len >= 4) { |
||
226 | mga_writel(va, offs, *srcd++); |
||
227 | offs += 4; |
||
228 | len -= 4; |
||
229 | } |
||
230 | } |
||
231 | #undef srcd |
||
232 | if (len) { |
||
233 | u_int32_t tmp; |
||
234 | |||
235 | memcpy(&tmp, src, len); |
||
236 | mga_writel(va, offs, tmp); |
||
237 | } |
||
238 | #elif defined(MEMCPYTOIO_MEMCPY) |
||
239 | memcpy(va.vaddr + offs, src, len); |
||
240 | #else |
||
241 | #error "Sorry, do not know how to write block of data to device" |
||
242 | #endif |
||
243 | } |
||
244 | |||
245 | static inline void vaddr_add(vaddr_t* va, unsigned long offs) { |
||
246 | va->vaddr += offs; |
||
247 | } |
||
248 | |||
249 | static inline void* vaddr_va(vaddr_t va) { |
||
250 | return va.vaddr; |
||
251 | } |
||
252 | |||
253 | #define MGA_IOREMAP_NORMAL 0 |
||
254 | #define MGA_IOREMAP_NOCACHE 1 |
||
255 | |||
256 | #define MGA_IOREMAP_FB MGA_IOREMAP_NOCACHE |
||
257 | #define MGA_IOREMAP_MMIO MGA_IOREMAP_NOCACHE |
||
258 | static inline int mga_ioremap(unsigned long phys, unsigned long size, int flags, vaddr_t* virt) { |
||
259 | #ifdef MAP_IOREMAP |
||
260 | if (flags & MGA_IOREMAP_NOCACHE) |
||
261 | virt->vaddr = ioremap(phys, size); |
||
262 | else |
||
263 | virt->vaddr = ioremap(phys, size); |
||
264 | #else |
||
265 | #ifdef MAP_BUSTOVIRT |
||
266 | virt->vaddr = bus_to_virt(phys); |
||
267 | #else |
||
268 | #error "Your architecture does not have neither ioremap nor bus_to_virt... Giving up" |
||
269 | #endif |
||
270 | #endif |
||
271 | return (virt->vaddr == 0); /* 0, !0... 0, error_code in future */ |
||
272 | } |
||
273 | |||
274 | static inline void mga_iounmap(vaddr_t va) { |
||
275 | #ifdef MAP_IOREMAP |
||
276 | iounmap(va.vaddr); |
||
277 | #endif |
||
278 | } |
||
279 | |||
280 | struct my_timming { |
||
281 | unsigned int pixclock; |
||
282 | int mnp; |
||
283 | unsigned int crtc; |
||
284 | unsigned int HDisplay; |
||
285 | unsigned int HSyncStart; |
||
286 | unsigned int HSyncEnd; |
||
287 | unsigned int HTotal; |
||
288 | unsigned int VDisplay; |
||
289 | unsigned int VSyncStart; |
||
290 | unsigned int VSyncEnd; |
||
291 | unsigned int VTotal; |
||
292 | unsigned int sync; |
||
293 | int dblscan; |
||
294 | int interlaced; |
||
295 | unsigned int delay; /* CRTC delay */ |
||
296 | }; |
||
297 | |||
298 | enum { M_SYSTEM_PLL, M_PIXEL_PLL_A, M_PIXEL_PLL_B, M_PIXEL_PLL_C, M_VIDEO_PLL }; |
||
299 | |||
300 | struct matrox_pll_cache { |
||
301 | unsigned int valid; |
||
302 | struct { |
||
303 | unsigned int mnp_key; |
||
304 | unsigned int mnp_value; |
||
305 | } data[4]; |
||
306 | }; |
||
307 | |||
308 | struct matrox_pll_limits { |
||
309 | unsigned int vcomin; |
||
310 | unsigned int vcomax; |
||
311 | }; |
||
312 | |||
313 | struct matrox_pll_features { |
||
314 | unsigned int vco_freq_min; |
||
315 | unsigned int ref_freq; |
||
316 | unsigned int feed_div_min; |
||
317 | unsigned int feed_div_max; |
||
318 | unsigned int in_div_min; |
||
319 | unsigned int in_div_max; |
||
320 | unsigned int post_shift_max; |
||
321 | }; |
||
322 | |||
323 | struct matroxfb_par |
||
324 | { |
||
325 | unsigned int final_bppShift; |
||
326 | unsigned int cmap_len; |
||
327 | struct { |
||
328 | unsigned int bytes; |
||
329 | unsigned int pixels; |
||
330 | unsigned int chunks; |
||
331 | } ydstorg; |
||
332 | }; |
||
333 | |||
334 | struct matrox_fb_info; |
||
335 | |||
336 | struct matrox_DAC1064_features { |
||
337 | u_int8_t xvrefctrl; |
||
338 | u_int8_t xmiscctrl; |
||
339 | }; |
||
340 | |||
341 | struct matrox_accel_features { |
||
342 | int has_cacheflush; |
||
343 | }; |
||
344 | |||
345 | /* current hardware status */ |
||
346 | struct mavenregs { |
||
347 | u_int8_t regs[256]; |
||
348 | int mode; |
||
349 | int vlines; |
||
350 | int xtal; |
||
351 | int fv; |
||
352 | |||
353 | u_int16_t htotal; |
||
354 | u_int16_t hcorr; |
||
355 | }; |
||
356 | |||
357 | struct matrox_crtc2 { |
||
358 | u_int32_t ctl; |
||
359 | }; |
||
360 | |||
361 | struct matrox_hw_state { |
||
362 | u_int32_t MXoptionReg; |
||
363 | unsigned char DACclk[6]; |
||
364 | unsigned char DACreg[80]; |
||
365 | unsigned char MiscOutReg; |
||
366 | unsigned char DACpal[768]; |
||
367 | unsigned char CRTC[25]; |
||
368 | unsigned char CRTCEXT[9]; |
||
369 | unsigned char SEQ[5]; |
||
370 | /* unused for MGA mode, but who knows... */ |
||
371 | unsigned char GCTL[9]; |
||
372 | /* unused for MGA mode, but who knows... */ |
||
373 | unsigned char ATTR[21]; |
||
374 | |||
375 | /* TVOut only */ |
||
376 | struct mavenregs maven; |
||
377 | |||
378 | struct matrox_crtc2 crtc2; |
||
379 | }; |
||
380 | |||
381 | struct matrox_accel_data { |
||
382 | #ifdef CONFIG_FB_MATROX_MILLENIUM |
||
383 | unsigned char ramdac_rev; |
||
384 | #endif |
||
385 | u_int32_t m_dwg_rect; |
||
386 | u_int32_t m_opmode; |
||
387 | }; |
||
388 | |||
389 | struct v4l2_queryctrl; |
||
390 | struct v4l2_control; |
||
391 | |||
392 | struct matrox_altout { |
||
393 | const char *name; |
||
394 | int (*compute)(void* altout_dev, struct my_timming* input); |
||
395 | int (*program)(void* altout_dev); |
||
396 | int (*start)(void* altout_dev); |
||
397 | int (*verifymode)(void* altout_dev, u_int32_t mode); |
||
398 | int (*getqueryctrl)(void* altout_dev, |
||
399 | struct v4l2_queryctrl* ctrl); |
||
400 | int (*getctrl)(void* altout_dev, |
||
401 | struct v4l2_control* ctrl); |
||
402 | int (*setctrl)(void* altout_dev, |
||
403 | struct v4l2_control* ctrl); |
||
404 | }; |
||
405 | |||
406 | #define MATROXFB_SRC_NONE 0 |
||
407 | #define MATROXFB_SRC_CRTC1 1 |
||
408 | #define MATROXFB_SRC_CRTC2 2 |
||
409 | |||
410 | enum mga_chip { MGA_2064, MGA_2164, MGA_1064, MGA_1164, MGA_G100, MGA_G200, MGA_G400, MGA_G450, MGA_G550 }; |
||
411 | |||
412 | struct matrox_bios { |
||
413 | unsigned int bios_valid : 1; |
||
414 | unsigned int pins_len; |
||
415 | unsigned char pins[128]; |
||
416 | struct { |
||
417 | unsigned char vMaj, vMin, vRev; |
||
418 | } version; |
||
419 | struct { |
||
420 | unsigned char state, tvout; |
||
421 | } output; |
||
422 | }; |
||
423 | |||
424 | extern struct display fb_display[]; |
||
425 | |||
426 | struct matrox_switch; |
||
427 | struct matroxfb_driver; |
||
428 | struct matroxfb_dh_fb_info; |
||
429 | |||
430 | struct matrox_vsync { |
||
431 | wait_queue_head_t wait; |
||
432 | unsigned int cnt; |
||
433 | }; |
||
434 | |||
435 | struct matrox_fb_info { |
||
436 | struct fb_info fbcon; |
||
437 | |||
438 | struct list_head next_fb; |
||
439 | |||
440 | int dead; |
||
441 | unsigned int usecount; |
||
442 | |||
443 | unsigned int userusecount; |
||
444 | unsigned long irq_flags; |
||
445 | |||
446 | struct matroxfb_par curr; |
||
447 | struct matrox_hw_state hw; |
||
448 | |||
449 | struct matrox_accel_data accel; |
||
450 | |||
451 | struct pci_dev* pcidev; |
||
452 | |||
453 | struct { |
||
454 | struct matrox_vsync vsync; |
||
455 | unsigned int pixclock; |
||
456 | int mnp; |
||
457 | int panpos; |
||
458 | } crtc1; |
||
459 | struct { |
||
460 | struct matrox_vsync vsync; |
||
461 | unsigned int pixclock; |
||
462 | int mnp; |
||
463 | struct matroxfb_dh_fb_info* info; |
||
464 | struct rw_semaphore lock; |
||
465 | } crtc2; |
||
466 | struct { |
||
467 | struct rw_semaphore lock; |
||
468 | struct { |
||
469 | int brightness, contrast, saturation, hue, gamma; |
||
470 | int testout, deflicker; |
||
471 | } tvo_params; |
||
472 | } altout; |
||
473 | #define MATROXFB_MAX_OUTPUTS 3 |
||
474 | struct { |
||
475 | unsigned int src; |
||
476 | struct matrox_altout* output; |
||
477 | void* data; |
||
478 | unsigned int mode; |
||
479 | } outputs[MATROXFB_MAX_OUTPUTS]; |
||
480 | |||
481 | #define MATROXFB_MAX_FB_DRIVERS 5 |
||
482 | struct matroxfb_driver* (drivers[MATROXFB_MAX_FB_DRIVERS]); |
||
483 | void* (drivers_data[MATROXFB_MAX_FB_DRIVERS]); |
||
484 | unsigned int drivers_count; |
||
485 | |||
486 | struct { |
||
487 | unsigned long base; /* physical */ |
||
488 | vaddr_t vbase; /* CPU view */ |
||
489 | unsigned int len; |
||
490 | unsigned int len_usable; |
||
491 | unsigned int len_maximum; |
||
492 | } video; |
||
493 | |||
494 | struct { |
||
495 | unsigned long base; /* physical */ |
||
496 | vaddr_t vbase; /* CPU view */ |
||
497 | unsigned int len; |
||
498 | } mmio; |
||
499 | |||
500 | unsigned int max_pixel_clock; |
||
501 | |||
502 | struct matrox_switch* hw_switch; |
||
503 | |||
504 | struct { |
||
505 | struct matrox_pll_features pll; |
||
506 | struct matrox_DAC1064_features DAC1064; |
||
507 | struct matrox_accel_features accel; |
||
508 | } features; |
||
509 | struct { |
||
510 | spinlock_t DAC; |
||
511 | spinlock_t accel; |
||
512 | } lock; |
||
513 | |||
514 | enum mga_chip chip; |
||
515 | |||
516 | int interleave; |
||
517 | int millenium; |
||
518 | int milleniumII; |
||
519 | struct { |
||
520 | int cfb4; |
||
521 | const int* vxres; |
||
522 | int cross4MB; |
||
523 | int text; |
||
524 | int plnwt; |
||
525 | int srcorg; |
||
526 | } capable; |
||
527 | #ifdef CONFIG_MTRR |
||
528 | struct { |
||
529 | int vram; |
||
530 | int vram_valid; |
||
531 | } mtrr; |
||
532 | #endif |
||
533 | struct { |
||
534 | int precise_width; |
||
535 | int mga_24bpp_fix; |
||
536 | int novga; |
||
537 | int nobios; |
||
538 | int nopciretry; |
||
539 | int noinit; |
||
540 | int sgram; |
||
541 | #ifdef CONFIG_FB_MATROX_32MB |
||
542 | int support32MB; |
||
543 | #endif |
||
544 | |||
545 | int accelerator; |
||
546 | int text_type_aux; |
||
547 | int video64bits; |
||
548 | int crtc2; |
||
549 | int maven_capable; |
||
550 | unsigned int vgastep; |
||
551 | unsigned int textmode; |
||
552 | unsigned int textstep; |
||
553 | unsigned int textvram; /* character cells */ |
||
554 | unsigned int ydstorg; /* offset in bytes from video start to usable memory */ |
||
555 | /* 0 except for 6MB Millenium */ |
||
556 | int memtype; |
||
557 | int g450dac; |
||
558 | int dfp_type; |
||
559 | int panellink; /* G400 DFP possible (not G450/G550) */ |
||
560 | int dualhead; |
||
561 | unsigned int fbResource; |
||
562 | } devflags; |
||
563 | struct fb_ops fbops; |
||
564 | struct matrox_bios bios; |
||
565 | struct { |
||
566 | struct matrox_pll_limits pixel; |
||
567 | struct matrox_pll_limits system; |
||
568 | struct matrox_pll_limits video; |
||
569 | } limits; |
||
570 | struct { |
||
571 | struct matrox_pll_cache pixel; |
||
572 | struct matrox_pll_cache system; |
||
573 | struct matrox_pll_cache video; |
||
574 | } cache; |
||
575 | struct { |
||
576 | struct { |
||
577 | unsigned int video; |
||
578 | unsigned int system; |
||
579 | } pll; |
||
580 | struct { |
||
581 | u_int32_t opt; |
||
582 | u_int32_t opt2; |
||
583 | u_int32_t opt3; |
||
584 | u_int32_t mctlwtst; |
||
585 | u_int32_t mctlwtst_core; |
||
586 | u_int32_t memmisc; |
||
587 | u_int32_t memrdbk; |
||
588 | u_int32_t maccess; |
||
589 | } reg; |
||
590 | struct { |
||
591 | unsigned int ddr:1, |
||
592 | emrswen:1, |
||
593 | dll:1; |
||
594 | } memory; |
||
595 | } values; |
||
596 | u_int32_t cmap[17]; |
||
597 | }; |
||
598 | |||
599 | #define info2minfo(info) container_of(info, struct matrox_fb_info, fbcon) |
||
600 | |||
601 | #ifdef CONFIG_FB_MATROX_MULTIHEAD |
||
602 | #define ACCESS_FBINFO2(info, x) (info->x) |
||
603 | #define ACCESS_FBINFO(x) ACCESS_FBINFO2(minfo,x) |
||
604 | |||
605 | #define MINFO minfo |
||
606 | |||
607 | #define WPMINFO2 struct matrox_fb_info* minfo |
||
608 | #define WPMINFO WPMINFO2 , |
||
609 | #define CPMINFO2 const struct matrox_fb_info* minfo |
||
610 | #define CPMINFO CPMINFO2 , |
||
611 | #define PMINFO2 minfo |
||
612 | #define PMINFO PMINFO2 , |
||
613 | |||
614 | #define MINFO_FROM(x) struct matrox_fb_info* minfo = x |
||
615 | #else |
||
616 | |||
617 | extern struct matrox_fb_info matroxfb_global_mxinfo; |
||
618 | |||
619 | #define ACCESS_FBINFO(x) (matroxfb_global_mxinfo.x) |
||
620 | #define ACCESS_FBINFO2(info, x) (matroxfb_global_mxinfo.x) |
||
621 | |||
622 | #define MINFO (&matroxfb_global_mxinfo) |
||
623 | |||
624 | #define WPMINFO2 void |
||
625 | #define WPMINFO |
||
626 | #define CPMINFO2 void |
||
627 | #define CPMINFO |
||
628 | #define PMINFO2 |
||
629 | #define PMINFO |
||
630 | |||
631 | #define MINFO_FROM(x) |
||
632 | |||
633 | #endif |
||
634 | |||
635 | #define MINFO_FROM_INFO(x) MINFO_FROM(info2minfo(x)) |
||
636 | |||
637 | struct matrox_switch { |
||
638 | int (*preinit)(WPMINFO2); |
||
639 | void (*reset)(WPMINFO2); |
||
640 | int (*init)(WPMINFO struct my_timming*); |
||
641 | void (*restore)(WPMINFO2); |
||
642 | }; |
||
643 | |||
644 | struct matroxfb_driver { |
||
645 | struct list_head node; |
||
646 | char* name; |
||
647 | void* (*probe)(struct matrox_fb_info* info); |
||
648 | void (*remove)(struct matrox_fb_info* info, void* data); |
||
649 | }; |
||
650 | |||
651 | int matroxfb_register_driver(struct matroxfb_driver* drv); |
||
652 | void matroxfb_unregister_driver(struct matroxfb_driver* drv); |
||
653 | |||
654 | #define PCI_OPTION_REG 0x40 |
||
655 | #define PCI_OPTION_ENABLE_ROM 0x40000000 |
||
656 | |||
657 | #define PCI_MGA_INDEX 0x44 |
||
658 | #define PCI_MGA_DATA 0x48 |
||
659 | #define PCI_OPTION2_REG 0x50 |
||
660 | #define PCI_OPTION3_REG 0x54 |
||
661 | #define PCI_MEMMISC_REG 0x58 |
||
662 | |||
663 | #define M_DWGCTL 0x1C00 |
||
664 | #define M_MACCESS 0x1C04 |
||
665 | #define M_CTLWTST 0x1C08 |
||
666 | |||
667 | #define M_PLNWT 0x1C1C |
||
668 | |||
669 | #define M_BCOL 0x1C20 |
||
670 | #define M_FCOL 0x1C24 |
||
671 | |||
672 | #define M_SGN 0x1C58 |
||
673 | #define M_LEN 0x1C5C |
||
674 | #define M_AR0 0x1C60 |
||
675 | #define M_AR1 0x1C64 |
||
676 | #define M_AR2 0x1C68 |
||
677 | #define M_AR3 0x1C6C |
||
678 | #define M_AR4 0x1C70 |
||
679 | #define M_AR5 0x1C74 |
||
680 | #define M_AR6 0x1C78 |
||
681 | |||
682 | #define M_CXBNDRY 0x1C80 |
||
683 | #define M_FXBNDRY 0x1C84 |
||
684 | #define M_YDSTLEN 0x1C88 |
||
685 | #define M_PITCH 0x1C8C |
||
686 | #define M_YDST 0x1C90 |
||
687 | #define M_YDSTORG 0x1C94 |
||
688 | #define M_YTOP 0x1C98 |
||
689 | #define M_YBOT 0x1C9C |
||
690 | |||
691 | /* mystique only */ |
||
692 | #define M_CACHEFLUSH 0x1FFF |
||
693 | |||
694 | #define M_EXEC 0x0100 |
||
695 | |||
696 | #define M_DWG_TRAP 0x04 |
||
697 | #define M_DWG_BITBLT 0x08 |
||
698 | #define M_DWG_ILOAD 0x09 |
||
699 | |||
700 | #define M_DWG_LINEAR 0x0080 |
||
701 | #define M_DWG_SOLID 0x0800 |
||
702 | #define M_DWG_ARZERO 0x1000 |
||
703 | #define M_DWG_SGNZERO 0x2000 |
||
704 | #define M_DWG_SHIFTZERO 0x4000 |
||
705 | |||
706 | #define M_DWG_REPLACE 0x000C0000 |
||
707 | #define M_DWG_REPLACE2 (M_DWG_REPLACE | 0x40) |
||
708 | #define M_DWG_XOR 0x00060010 |
||
709 | |||
710 | #define M_DWG_BFCOL 0x04000000 |
||
711 | #define M_DWG_BMONOWF 0x08000000 |
||
712 | |||
713 | #define M_DWG_TRANSC 0x40000000 |
||
714 | |||
715 | #define M_FIFOSTATUS 0x1E10 |
||
716 | #define M_STATUS 0x1E14 |
||
717 | #define M_ICLEAR 0x1E18 |
||
718 | #define M_IEN 0x1E1C |
||
719 | |||
720 | #define M_VCOUNT 0x1E20 |
||
721 | |||
722 | #define M_RESET 0x1E40 |
||
723 | #define M_MEMRDBK 0x1E44 |
||
724 | |||
725 | #define M_AGP2PLL 0x1E4C |
||
726 | |||
727 | #define M_OPMODE 0x1E54 |
||
728 | #define M_OPMODE_DMA_GEN_WRITE 0x00 |
||
729 | #define M_OPMODE_DMA_BLIT 0x04 |
||
730 | #define M_OPMODE_DMA_VECTOR_WRITE 0x08 |
||
731 | #define M_OPMODE_DMA_LE 0x0000 /* little endian - no transformation */ |
||
732 | #define M_OPMODE_DMA_BE_8BPP 0x0000 |
||
733 | #define M_OPMODE_DMA_BE_16BPP 0x0100 |
||
734 | #define M_OPMODE_DMA_BE_32BPP 0x0200 |
||
735 | #define M_OPMODE_DIR_LE 0x000000 /* little endian - no transformation */ |
||
736 | #define M_OPMODE_DIR_BE_8BPP 0x000000 |
||
737 | #define M_OPMODE_DIR_BE_16BPP 0x010000 |
||
738 | #define M_OPMODE_DIR_BE_32BPP 0x020000 |
||
739 | |||
740 | #define M_ATTR_INDEX 0x1FC0 |
||
741 | #define M_ATTR_DATA 0x1FC1 |
||
742 | |||
743 | #define M_MISC_REG 0x1FC2 |
||
744 | #define M_3C2_RD 0x1FC2 |
||
745 | |||
746 | #define M_SEQ_INDEX 0x1FC4 |
||
747 | #define M_SEQ_DATA 0x1FC5 |
||
748 | |||
749 | #define M_MISC_REG_READ 0x1FCC |
||
750 | |||
751 | #define M_GRAPHICS_INDEX 0x1FCE |
||
752 | #define M_GRAPHICS_DATA 0x1FCF |
||
753 | |||
754 | #define M_CRTC_INDEX 0x1FD4 |
||
755 | |||
756 | #define M_ATTR_RESET 0x1FDA |
||
757 | #define M_3DA_WR 0x1FDA |
||
758 | #define M_INSTS1 0x1FDA |
||
759 | |||
760 | #define M_EXTVGA_INDEX 0x1FDE |
||
761 | #define M_EXTVGA_DATA 0x1FDF |
||
762 | |||
763 | /* G200 only */ |
||
764 | #define M_SRCORG 0x2CB4 |
||
765 | #define M_DSTORG 0x2CB8 |
||
766 | |||
767 | #define M_RAMDAC_BASE 0x3C00 |
||
768 | |||
769 | /* fortunately, same on TVP3026 and MGA1064 */ |
||
770 | #define M_DAC_REG (M_RAMDAC_BASE+0) |
||
771 | #define M_DAC_VAL (M_RAMDAC_BASE+1) |
||
772 | #define M_PALETTE_MASK (M_RAMDAC_BASE+2) |
||
773 | |||
774 | #define M_X_INDEX 0x00 |
||
775 | #define M_X_DATAREG 0x0A |
||
776 | |||
777 | #define DAC_XGENIOCTRL 0x2A |
||
778 | #define DAC_XGENIODATA 0x2B |
||
779 | |||
780 | #define M_C2CTL 0x3E10 |
||
781 | |||
782 | #ifdef __LITTLE_ENDIAN |
||
783 | #define MX_OPTION_BSWAP 0x00000000 |
||
784 | |||
785 | #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
786 | #define M_OPMODE_8BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
787 | #define M_OPMODE_16BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
788 | #define M_OPMODE_24BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
789 | #define M_OPMODE_32BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) |
||
790 | #else |
||
791 | #ifdef __BIG_ENDIAN |
||
792 | #define MX_OPTION_BSWAP 0x80000000 |
||
793 | |||
794 | #define M_OPMODE_4BPP (M_OPMODE_DMA_LE | M_OPMODE_DIR_LE | M_OPMODE_DMA_BLIT) /* TODO */ |
||
795 | #define M_OPMODE_8BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) |
||
796 | #define M_OPMODE_16BPP (M_OPMODE_DMA_BE_16BPP | M_OPMODE_DIR_BE_16BPP | M_OPMODE_DMA_BLIT) |
||
797 | #define M_OPMODE_24BPP (M_OPMODE_DMA_BE_8BPP | M_OPMODE_DIR_BE_8BPP | M_OPMODE_DMA_BLIT) /* TODO, ?32 */ |
||
798 | #define M_OPMODE_32BPP (M_OPMODE_DMA_BE_32BPP | M_OPMODE_DIR_BE_32BPP | M_OPMODE_DMA_BLIT) |
||
799 | #else |
||
800 | #error "Byte ordering have to be defined. Cannot continue." |
||
801 | #endif |
||
802 | #endif |
||
803 | |||
804 | #define mga_inb(addr) mga_readb(ACCESS_FBINFO(mmio.vbase), (addr)) |
||
805 | #define mga_inl(addr) mga_readl(ACCESS_FBINFO(mmio.vbase), (addr)) |
||
806 | #define mga_outb(addr,val) mga_writeb(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
807 | #define mga_outw(addr,val) mga_writew(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
808 | #define mga_outl(addr,val) mga_writel(ACCESS_FBINFO(mmio.vbase), (addr), (val)) |
||
809 | #define mga_readr(port,idx) (mga_outb((port),(idx)), mga_inb((port)+1)) |
||
810 | #ifdef __LITTLE_ENDIAN |
||
811 | #define mga_setr(addr,port,val) mga_outw(addr, ((val)<<8) | (port)) |
||
812 | #else |
||
813 | #define mga_setr(addr,port,val) do { mga_outb(addr, port); mga_outb((addr)+1, val); } while (0) |
||
814 | #endif |
||
815 | |||
816 | #define mga_fifo(n) do {} while ((mga_inl(M_FIFOSTATUS) & 0xFF) < (n)) |
||
817 | |||
818 | #define WaitTillIdle() do {} while (mga_inl(M_STATUS) & 0x10000) |
||
819 | |||
820 | /* code speedup */ |
||
821 | #ifdef CONFIG_FB_MATROX_MILLENIUM |
||
822 | #define isInterleave(x) (x->interleave) |
||
823 | #define isMillenium(x) (x->millenium) |
||
824 | #define isMilleniumII(x) (x->milleniumII) |
||
825 | #else |
||
826 | #define isInterleave(x) (0) |
||
827 | #define isMillenium(x) (0) |
||
828 | #define isMilleniumII(x) (0) |
||
829 | #endif |
||
830 | |||
831 | #define matroxfb_DAC_lock() spin_lock(&ACCESS_FBINFO(lock.DAC)) |
||
832 | #define matroxfb_DAC_unlock() spin_unlock(&ACCESS_FBINFO(lock.DAC)) |
||
833 | #define matroxfb_DAC_lock_irqsave(flags) spin_lock_irqsave(&ACCESS_FBINFO(lock.DAC),flags) |
||
834 | #define matroxfb_DAC_unlock_irqrestore(flags) spin_unlock_irqrestore(&ACCESS_FBINFO(lock.DAC),flags) |
||
835 | extern void matroxfb_DAC_out(CPMINFO int reg, int val); |
||
836 | extern int matroxfb_DAC_in(CPMINFO int reg); |
||
837 | extern struct list_head matroxfb_list; |
||
838 | extern void matroxfb_var2my(struct fb_var_screeninfo* fvsi, struct my_timming* mt); |
||
839 | extern int matroxfb_wait_for_sync(WPMINFO u_int32_t crtc); |
||
840 | extern int matroxfb_enable_irq(WPMINFO int reenable); |
||
841 | |||
842 | #ifdef MATROXFB_USE_SPINLOCKS |
||
843 | #define CRITBEGIN spin_lock_irqsave(&ACCESS_FBINFO(lock.accel), critflags); |
||
844 | #define CRITEND spin_unlock_irqrestore(&ACCESS_FBINFO(lock.accel), critflags); |
||
845 | #define CRITFLAGS unsigned long critflags; |
||
846 | #else |
||
847 | #define CRITBEGIN |
||
848 | #define CRITEND |
||
849 | #define CRITFLAGS |
||
850 | #endif |
||
851 | |||
852 | #endif /* __MATROXFB_H__ */ |