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#ifndef _I386_DEBUGREG_H
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#define _I386_DEBUGREG_H
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/* Indicate the register numbers for a number of the specific
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   debug registers.  Registers 0-3 contain the addresses we wish to trap on */
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#define DR_FIRSTADDR 0        /* u_debugreg[DR_FIRSTADDR] */
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#define DR_LASTADDR 3         /* u_debugreg[DR_LASTADDR]  */
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#define DR_STATUS 6           /* u_debugreg[DR_STATUS]     */
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#define DR_CONTROL 7          /* u_debugreg[DR_CONTROL] */
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/* Define a few things for the status register.  We can use this to determine
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   which debugging register was responsible for the trap.  The other bits
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   are either reserved or not of interest to us. */
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#define DR_TRAP0        (0x1)           /* db0 */
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#define DR_TRAP1        (0x2)           /* db1 */
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#define DR_TRAP2        (0x4)           /* db2 */
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#define DR_TRAP3        (0x8)           /* db3 */
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#define DR_STEP         (0x4000)        /* single-step */
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#define DR_SWITCH       (0x8000)        /* task switch */
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/* Now define a bunch of things for manipulating the control register.
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   The top two bytes of the control register consist of 4 fields of 4
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   bits - each field corresponds to one of the four debug registers,
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   and indicates what types of access we trap on, and how large the data
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   field is that we are looking at */
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#define DR_CONTROL_SHIFT 16 /* Skip this many bits in ctl register */
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#define DR_CONTROL_SIZE 4   /* 4 control bits per register */
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#define DR_RW_EXECUTE (0x0)   /* Settings for the access types to trap on */
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#define DR_RW_WRITE (0x1)
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#define DR_RW_READ (0x3)
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#define DR_LEN_1 (0x0) /* Settings for data length to trap on */
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#define DR_LEN_2 (0x4)
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#define DR_LEN_4 (0xC)
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/* The low byte to the control register determine which registers are
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   enabled.  There are 4 fields of two bits.  One bit is "local", meaning
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   that the processor will reset the bit after a task switch and the other
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   is global meaning that we have to explicitly reset the bit.  With linux,
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   you can use either one, since we explicitly zero the register when we enter
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   kernel mode. */
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#define DR_LOCAL_ENABLE_SHIFT 0    /* Extra shift to the local enable bit */
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#define DR_GLOBAL_ENABLE_SHIFT 1   /* Extra shift to the global enable bit */
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#define DR_ENABLE_SIZE 2           /* 2 enable bits per register */
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#define DR_LOCAL_ENABLE_MASK (0x55)  /* Set  local bits for all 4 regs */
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#define DR_GLOBAL_ENABLE_MASK (0xAA) /* Set global bits for all 4 regs */
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/* The second byte to the control register has a few special things.
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   We can slow the instruction pipeline for instructions coming via the
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   gdt or the ldt if we want to.  I am not sure why this is an advantage */
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#define DR_CONTROL_RESERVED (0xFC00) /* Reserved by Intel */
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#define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
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#define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
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#endif