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846 giacomo 1
/*
2
 * Copyright (c) 2001-2002 by David Brownell
3
 *
4
 * This program is free software; you can redistribute it and/or modify it
5
 * under the terms of the GNU General Public License as published by the
6
 * Free Software Foundation; either version 2 of the License, or (at your
7
 * option) any later version.
8
 *
9
 * This program is distributed in the hope that it will be useful, but
10
 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
11
 * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
12
 * for more details.
13
 *
14
 * You should have received a copy of the GNU General Public License
15
 * along with this program; if not, write to the Free Software Foundation,
16
 * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17
 */
18
 
19
#ifndef __LINUX_EHCI_HCD_H
20
#define __LINUX_EHCI_HCD_H
21
 
22
/* definitions used for the EHCI driver */
23
 
24
/* statistics can be kept for for tuning/monitoring */
25
struct ehci_stats {
26
        /* irq usage */
27
        unsigned long           normal;
28
        unsigned long           error;
29
        unsigned long           reclaim;
30
        unsigned long           lost_iaa;
31
 
32
        /* termination of urbs from core */
33
        unsigned long           complete;
34
        unsigned long           unlink;
35
};
36
 
37
/* ehci_hcd->lock guards shared data against other CPUs:
38
 *   ehci_hcd:  async, reclaim, periodic (and shadow), ...
39
 *   hcd_dev:   ep[]
40
 *   ehci_qh:   qh_next, qtd_list
41
 *   ehci_qtd:  qtd_list
42
 *
43
 * Also, hold this lock when talking to HC registers or
44
 * when updating hw_* fields in shared qh/qtd/... structures.
45
 */
46
 
47
#define EHCI_MAX_ROOT_PORTS     15              /* see HCS_N_PORTS */
48
 
49
struct ehci_hcd {                       /* one per controller */
50
        spinlock_t              lock;
51
 
52
        /* async schedule support */
53
        struct ehci_qh          *async;
54
        struct ehci_qh          *reclaim;
55
        int                     reclaim_ready : 1;
56
 
57
        /* periodic schedule support */
58
#define DEFAULT_I_TDPS          1024            /* some HCs can do less */
59
        unsigned                periodic_size;
60
        u32                     *periodic;      /* hw periodic table */
61
        dma_addr_t              periodic_dma;
62
        unsigned                i_thresh;       /* uframes HC might cache */
63
 
64
        union ehci_shadow       *pshadow;       /* mirror hw periodic table */
65
        int                     next_uframe;    /* scan periodic, start here */
66
        unsigned                periodic_sched; /* periodic activity count */
67
 
68
        /* per root hub port */
69
        unsigned long           reset_done [EHCI_MAX_ROOT_PORTS];
70
 
71
        /* glue to PCI and HCD framework */
72
        struct usb_hcd          hcd;
73
        struct ehci_caps        *caps;
74
        struct ehci_regs        *regs;
75
        u32                     hcs_params;     /* cached register copy */
76
 
77
        /* per-HC memory pools (could be per-PCI-bus, but ...) */
78
        struct pci_pool         *qh_pool;       /* qh per active urb */
79
        struct pci_pool         *qtd_pool;      /* one or more per qh */
80
        struct pci_pool         *itd_pool;      /* itd per iso urb */
81
        struct pci_pool         *sitd_pool;     /* sitd per split iso urb */
82
 
83
        struct timer_list       watchdog;
84
        struct notifier_block   reboot_notifier;
85
        unsigned long           actions;
86
        unsigned                stamp;
87
 
88
        /* irq statistics */
89
#ifdef EHCI_STATS
90
        struct ehci_stats       stats;
91
#       define COUNT(x) do { (x)++; } while (0)
92
#else
93
#       define COUNT(x) do {} while (0)
94
#endif
95
};
96
 
97
/* unwrap an HCD pointer to get an EHCI_HCD pointer */
98
#define hcd_to_ehci(hcd_ptr) container_of(hcd_ptr, struct ehci_hcd, hcd)
99
 
100
/* NOTE:  urb->transfer_flags expected to not use this bit !!! */
101
#define EHCI_STATE_UNLINK       0x8000          /* urb being unlinked */
102
 
103
enum ehci_timer_action {
104
        TIMER_IO_WATCHDOG,
105
        TIMER_IAA_WATCHDOG,
106
        TIMER_ASYNC_SHRINK,
107
        TIMER_ASYNC_OFF,
108
};
109
 
110
static inline void
111
timer_action_done (struct ehci_hcd *ehci, enum ehci_timer_action action)
112
{
113
        clear_bit (action, &ehci->actions);
114
}
115
 
116
static inline void
117
timer_action (struct ehci_hcd *ehci, enum ehci_timer_action action)
118
{
119
        if (!test_and_set_bit (action, &ehci->actions)) {
120
                unsigned long t;
121
 
122
                switch (action) {
123
                case TIMER_IAA_WATCHDOG:
124
                        t = EHCI_IAA_JIFFIES;
125
                        break;
126
                case TIMER_IO_WATCHDOG:
127
                        t = EHCI_IO_JIFFIES;
128
                        break;
129
                case TIMER_ASYNC_OFF:
130
                        t = EHCI_ASYNC_JIFFIES;
131
                        break;
132
                // case TIMER_ASYNC_SHRINK:
133
                default:
134
                        t = EHCI_SHRINK_JIFFIES;
135
                        break;
136
                }
1049 mauro 137
                t += jiffies26;
846 giacomo 138
                // all timings except IAA watchdog can be overridden.
139
                // async queue SHRINK often precedes IAA.  while it's ready
140
                // to go OFF neither can matter, and afterwards the IO
141
                // watchdog stops unless there's still periodic traffic.
142
                if (action != TIMER_IAA_WATCHDOG
143
                                && t > ehci->watchdog.expires
144
                                && timer_pending (&ehci->watchdog))
145
                        return;
146
                mod_timer (&ehci->watchdog, t);
147
        }
148
}
149
 
150
/*-------------------------------------------------------------------------*/
151
 
152
/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
153
 
154
/* Section 2.2 Host Controller Capability Registers */
155
struct ehci_caps {
156
        u8              length;         /* CAPLENGTH - size of this struct */
157
        u8              reserved;       /* offset 0x1 */
158
        u16             hci_version;    /* HCIVERSION - offset 0x2 */
159
        u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
160
#define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
161
#define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
162
#define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
163
#define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
164
#define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */ 
165
#define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */ 
166
#define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
167
 
168
        u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
169
#define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
170
#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
171
#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
172
#define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
173
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
174
#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
175
        u8              portroute [8];   /* nibbles for routing - offset 0xC */
176
} __attribute__ ((packed));
177
 
178
 
179
/* Section 2.3 Host Controller Operational Registers */
180
struct ehci_regs {
181
 
182
        /* USBCMD: offset 0x00 */
183
        u32             command;
184
/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
185
#define CMD_PARK        (1<<11)         /* enable "park" on async qh */
186
#define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
187
#define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
188
#define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
189
#define CMD_ASE         (1<<5)          /* async schedule enable */
190
#define CMD_PSE         (1<<4)          /* periodic schedule enable */
191
/* 3:2 is periodic frame list size */
192
#define CMD_RESET       (1<<1)          /* reset HC not bus */
193
#define CMD_RUN         (1<<0)          /* start/stop HC */
194
 
195
        /* USBSTS: offset 0x04 */
196
        u32             status;
197
#define STS_ASS         (1<<15)         /* Async Schedule Status */
198
#define STS_PSS         (1<<14)         /* Periodic Schedule Status */
199
#define STS_RECL        (1<<13)         /* Reclamation */
200
#define STS_HALT        (1<<12)         /* Not running (any reason) */
201
/* some bits reserved */
202
        /* these STS_* flags are also intr_enable bits (USBINTR) */
203
#define STS_IAA         (1<<5)          /* Interrupted on async advance */
204
#define STS_FATAL       (1<<4)          /* such as some PCI access errors */
205
#define STS_FLR         (1<<3)          /* frame list rolled over */
206
#define STS_PCD         (1<<2)          /* port change detect */
207
#define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
208
#define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
209
 
210
        /* USBINTR: offset 0x08 */
211
        u32             intr_enable;
212
 
213
        /* FRINDEX: offset 0x0C */
214
        u32             frame_index;    /* current microframe number */
215
        /* CTRLDSSEGMENT: offset 0x10 */
216
        u32             segment;        /* address bits 63:32 if needed */
217
        /* PERIODICLISTBASE: offset 0x14 */
218
        u32             frame_list;     /* points to periodic list */
219
        /* ASYNCICLISTADDR: offset 0x18 */
220
        u32             async_next;     /* address of next async queue head */
221
 
222
        u32             reserved [9];
223
 
224
        /* CONFIGFLAG: offset 0x40 */
225
        u32             configured_flag;
226
#define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
227
 
228
        /* PORTSC: offset 0x44 */
229
        u32             port_status [0];        /* up to N_PORTS */
230
/* 31:23 reserved */
231
#define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
232
#define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
233
#define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
234
/* 19:16 for port testing */
235
/* 15:14 for using port indicator leds (if HCS_INDICATOR allows) */
236
#define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
237
#define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
238
#define PORT_USB11(x) (((x)&(3<<10))==(1<<10))  /* USB 1.1 device */
239
/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
240
/* 9 reserved */
241
#define PORT_RESET      (1<<8)          /* reset port */
242
#define PORT_SUSPEND    (1<<7)          /* suspend port */
243
#define PORT_RESUME     (1<<6)          /* resume it */
244
#define PORT_OCC        (1<<5)          /* over current change */
245
#define PORT_OC         (1<<4)          /* over current active */
246
#define PORT_PEC        (1<<3)          /* port enable change */
247
#define PORT_PE         (1<<2)          /* port enable */
248
#define PORT_CSC        (1<<1)          /* connect status change */
249
#define PORT_CONNECT    (1<<0)          /* device connected */
250
} __attribute__ ((packed));
251
 
252
 
253
/*-------------------------------------------------------------------------*/
254
 
255
#define QTD_NEXT(dma)   cpu_to_le32((u32)dma)
256
 
257
/*
258
 * EHCI Specification 0.95 Section 3.5
259
 * QTD: describe data transfer components (buffer, direction, ...)
260
 * See Fig 3-6 "Queue Element Transfer Descriptor Block Diagram".
261
 *
262
 * These are associated only with "QH" (Queue Head) structures,
263
 * used with control, bulk, and interrupt transfers.
264
 */
265
struct ehci_qtd {
266
        /* first part defined by EHCI spec */
267
        u32                     hw_next;          /* see EHCI 3.5.1 */
268
        u32                     hw_alt_next;      /* see EHCI 3.5.2 */
269
        u32                     hw_token;         /* see EHCI 3.5.3 */      
270
#define QTD_TOGGLE      (1 << 31)       /* data toggle */
271
#define QTD_LENGTH(tok) (((tok)>>16) & 0x7fff)
272
#define QTD_IOC         (1 << 15)       /* interrupt on complete */
273
#define QTD_CERR(tok)   (((tok)>>10) & 0x3)
274
#define QTD_PID(tok)    (((tok)>>8) & 0x3)
275
#define QTD_STS_ACTIVE  (1 << 7)        /* HC may execute this */
276
#define QTD_STS_HALT    (1 << 6)        /* halted on error */
277
#define QTD_STS_DBE     (1 << 5)        /* data buffer error (in HC) */
278
#define QTD_STS_BABBLE  (1 << 4)        /* device was babbling (qtd halted) */
279
#define QTD_STS_XACT    (1 << 3)        /* device gave illegal response */
280
#define QTD_STS_MMF     (1 << 2)        /* incomplete split transaction */
281
#define QTD_STS_STS     (1 << 1)        /* split transaction state */
282
#define QTD_STS_PING    (1 << 0)        /* issue PING? */
283
        u32                     hw_buf [5];        /* see EHCI 3.5.4 */
284
        u32                     hw_buf_hi [5];        /* Appendix B */
285
 
286
        /* the rest is HCD-private */
287
        dma_addr_t              qtd_dma;                /* qtd address */
288
        struct list_head        qtd_list;               /* sw qtd list */
289
        struct urb              *urb;                   /* qtd's urb */
290
        size_t                  length;                 /* length of buffer */
291
} __attribute__ ((aligned (32)));
292
 
293
/* mask NakCnt+T in qh->hw_alt_next */
294
#define QTD_MASK __constant_cpu_to_le32 (~0x1f)
295
 
296
#define IS_SHORT_READ(token) (QTD_LENGTH (token) != 0 && QTD_PID (token) == 1)
297
 
298
/*-------------------------------------------------------------------------*/
299
 
300
/* type tag from {qh,itd,sitd,fstn}->hw_next */
301
#define Q_NEXT_TYPE(dma) ((dma) & __constant_cpu_to_le32 (3 << 1))
302
 
303
/* values for that type tag */
304
#define Q_TYPE_ITD      __constant_cpu_to_le32 (0 << 1)
305
#define Q_TYPE_QH       __constant_cpu_to_le32 (1 << 1)
306
#define Q_TYPE_SITD     __constant_cpu_to_le32 (2 << 1)
307
#define Q_TYPE_FSTN     __constant_cpu_to_le32 (3 << 1)
308
 
309
/* next async queue entry, or pointer to interrupt/periodic QH */
310
#define QH_NEXT(dma)    (cpu_to_le32(((u32)dma)&~0x01f)|Q_TYPE_QH)
311
 
312
/* for periodic/async schedules and qtd lists, mark end of list */
313
#define EHCI_LIST_END   __constant_cpu_to_le32(1) /* "null pointer" to hw */
314
 
315
/*
316
 * Entries in periodic shadow table are pointers to one of four kinds
317
 * of data structure.  That's dictated by the hardware; a type tag is
318
 * encoded in the low bits of the hardware's periodic schedule.  Use
319
 * Q_NEXT_TYPE to get the tag.
320
 *
321
 * For entries in the async schedule, the type tag always says "qh".
322
 */
323
union ehci_shadow {
324
        struct ehci_qh          *qh;            /* Q_TYPE_QH */
325
        struct ehci_itd         *itd;           /* Q_TYPE_ITD */
326
        struct ehci_sitd        *sitd;          /* Q_TYPE_SITD */
327
        struct ehci_fstn        *fstn;          /* Q_TYPE_FSTN */
328
        u32                     *hw_next;       /* (all types) */
329
        void                    *ptr;
330
};
331
 
332
/*-------------------------------------------------------------------------*/
333
 
334
/*
335
 * EHCI Specification 0.95 Section 3.6
336
 * QH: describes control/bulk/interrupt endpoints
337
 * See Fig 3-7 "Queue Head Structure Layout".
338
 *
339
 * These appear in both the async and (for interrupt) periodic schedules.
340
 */
341
 
342
struct ehci_qh {
343
        /* first part defined by EHCI spec */
344
        u32                     hw_next;         /* see EHCI 3.6.1 */
345
        u32                     hw_info1;        /* see EHCI 3.6.2 */
346
#define QH_HEAD         0x00008000
347
        u32                     hw_info2;        /* see EHCI 3.6.2 */
348
        u32                     hw_current;      /* qtd list - see EHCI 3.6.4 */
349
 
350
        /* qtd overlay (hardware parts of a struct ehci_qtd) */
351
        u32                     hw_qtd_next;
352
        u32                     hw_alt_next;
353
        u32                     hw_token;
354
        u32                     hw_buf [5];
355
        u32                     hw_buf_hi [5];
356
 
357
        /* the rest is HCD-private */
358
        dma_addr_t              qh_dma;         /* address of qh */
359
        union ehci_shadow       qh_next;        /* ptr to qh; or periodic */
360
        struct list_head        qtd_list;       /* sw qtd list */
361
        struct ehci_qtd         *dummy;
362
        struct ehci_qh          *reclaim;       /* next to reclaim */
363
 
364
        atomic_t                refcount;
365
        unsigned                stamp;
366
 
367
        u8                      qh_state;
368
#define QH_STATE_LINKED         1               /* HC sees this */
369
#define QH_STATE_UNLINK         2               /* HC may still see this */
370
#define QH_STATE_IDLE           3               /* HC doesn't see this */
371
#define QH_STATE_UNLINK_WAIT    4               /* LINKED and on reclaim q */
372
#define QH_STATE_COMPLETING     5               /* don't touch token.HALT */
373
 
374
        /* periodic schedule info */
375
        u8                      usecs;          /* intr bandwidth */
376
        u8                      gap_uf;         /* uframes split/csplit gap */
377
        u8                      c_usecs;        /* ... split completion bw */
378
        unsigned short          period;         /* polling interval */
379
        unsigned short          start;          /* where polling starts */
380
#define NO_FRAME ((unsigned short)~0)                   /* pick new start */
381
 
382
} __attribute__ ((aligned (32)));
383
 
384
/*-------------------------------------------------------------------------*/
385
 
386
/*
387
 * EHCI Specification 0.95 Section 3.3
388
 * Fig 3-4 "Isochronous Transaction Descriptor (iTD)"
389
 *
390
 * Schedule records for high speed iso xfers
391
 */
392
struct ehci_itd {
393
        /* first part defined by EHCI spec */
394
        u32                     hw_next;           /* see EHCI 3.3.1 */
395
        u32                     hw_transaction [8]; /* see EHCI 3.3.2 */
396
#define EHCI_ISOC_ACTIVE        (1<<31)        /* activate transfer this slot */
397
#define EHCI_ISOC_BUF_ERR       (1<<30)        /* Data buffer error */
398
#define EHCI_ISOC_BABBLE        (1<<29)        /* babble detected */
399
#define EHCI_ISOC_XACTERR       (1<<28)        /* XactErr - transaction error */
400
#define EHCI_ITD_LENGTH(tok)    (((tok)>>16) & 0x7fff)
401
#define EHCI_ITD_IOC            (1 << 15)       /* interrupt on complete */
402
 
403
        u32                     hw_bufp [7];    /* see EHCI 3.3.3 */
404
        u32                     hw_bufp_hi [7]; /* Appendix B */
405
 
406
        /* the rest is HCD-private */
407
        dma_addr_t              itd_dma;        /* for this itd */
408
        union ehci_shadow       itd_next;       /* ptr to periodic q entry */
409
 
410
        struct urb              *urb;
411
        struct list_head        itd_list;       /* list of urb frames' itds */
412
        dma_addr_t              buf_dma;        /* frame's buffer address */
413
 
414
        /* for now, only one hw_transaction per itd */
415
        u32                     transaction;
416
        u16                     index;          /* in urb->iso_frame_desc */
417
        u16                     uframe;         /* in periodic schedule */
418
        u16                     usecs;
419
} __attribute__ ((aligned (32)));
420
 
421
/*-------------------------------------------------------------------------*/
422
 
423
/*
424
 * EHCI Specification 0.95 Section 3.4
425
 * siTD, aka split-transaction isochronous Transfer Descriptor
426
 *       ... describe low/full speed iso xfers through TT in hubs
427
 * see Figure 3-5 "Split-transaction Isochronous Transaction Descriptor (siTD)
428
 */
429
struct ehci_sitd {
430
        /* first part defined by EHCI spec */
431
        u32                     hw_next;
432
/* uses bit field macros above - see EHCI 0.95 Table 3-8 */
433
        u32                     hw_fullspeed_ep;  /* see EHCI table 3-9 */
434
        u32                     hw_uframe;        /* see EHCI table 3-10 */
435
        u32                     hw_tx_results1;   /* see EHCI table 3-11 */
436
        u32                     hw_tx_results2;   /* see EHCI table 3-12 */
437
        u32                     hw_tx_results3;   /* see EHCI table 3-12 */
438
        u32                     hw_backpointer;   /* see EHCI table 3-13 */
439
        u32                     hw_buf_hi [2];    /* Appendix B */
440
 
441
        /* the rest is HCD-private */
442
        dma_addr_t              sitd_dma;
443
        union ehci_shadow       sitd_next;      /* ptr to periodic q entry */
444
        struct urb              *urb;
445
        dma_addr_t              buf_dma;        /* buffer address */
446
 
447
        unsigned short          usecs;          /* start bandwidth */
448
        unsigned short          c_usecs;        /* completion bandwidth */
449
} __attribute__ ((aligned (32)));
450
 
451
/*-------------------------------------------------------------------------*/
452
 
453
/*
454
 * EHCI Specification 0.96 Section 3.7
455
 * Periodic Frame Span Traversal Node (FSTN)
456
 *
457
 * Manages split interrupt transactions (using TT) that span frame boundaries
458
 * into uframes 0/1; see 4.12.2.2.  In those uframes, a "save place" FSTN
459
 * makes the HC jump (back) to a QH to scan for fs/ls QH completions until
460
 * it hits a "restore" FSTN; then it returns to finish other uframe 0/1 work.
461
 */
462
struct ehci_fstn {
463
        u32                     hw_next;        /* any periodic q entry */
464
        u32                     hw_prev;        /* qh or EHCI_LIST_END */
465
 
466
        /* the rest is HCD-private */
467
        dma_addr_t              fstn_dma;
468
        union ehci_shadow       fstn_next;      /* ptr to periodic q entry */
469
} __attribute__ ((aligned (32)));
470
 
471
/*-------------------------------------------------------------------------*/
472
 
473
#define SUBMIT_URB(urb,mem_flags) usb_submit_urb(urb,mem_flags)
474
 
475
#ifndef DEBUG
476
#define STUB_DEBUG_FILES
477
#endif  /* DEBUG */
478
 
479
/*-------------------------------------------------------------------------*/
480
 
481
#endif /* __LINUX_EHCI_HCD_H */