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#ifndef _ASM_I386_DMA_MAPPING_H
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#define _ASM_I386_DMA_MAPPING_H
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#include <asm/cache.h>
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#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
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#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
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void *dma_alloc_coherent(struct device *dev, size_t size,
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                         dma_addr_t *dma_handle, int flag);
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void *dma_alloc_coherent_usb(struct device *dev, size_t size,
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                             dma_addr_t *dma_handle, int flag);
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void dma_free_coherent(struct device *dev, size_t size,
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                         void *vaddr, dma_addr_t dma_handle);
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static inline dma_addr_t
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dma_map_single(struct device *dev, void *ptr, size_t size,
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               enum dma_data_direction direction)
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{
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        BUG_ON(direction == DMA_NONE);
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        flush_write_buffers();
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        return virt_to_phys(ptr);
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}
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static inline void
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dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
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                 enum dma_data_direction direction)
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{
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        BUG_ON(direction == DMA_NONE);
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}
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static inline int
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dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
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           enum dma_data_direction direction)
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{
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        int i;
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        BUG_ON(direction == DMA_NONE);
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        for (i = 0; i < nents; i++ ) {
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                BUG_ON(!sg[i].page);
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                sg[i].dma_address = page_to_phys(sg[i].page) + sg[i].offset;
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        }
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        flush_write_buffers();
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        return nents;
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}
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static inline dma_addr_t
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dma_map_page(struct device *dev, struct page *page, unsigned long offset,
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             size_t size, enum dma_data_direction direction)
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{
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        BUG_ON(direction == DMA_NONE);
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        return (dma_addr_t)(page_to_pfn(page)) * PAGE_SIZE + offset;
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}
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static inline void
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dma_unmap_page(struct device *dev, dma_addr_t dma_address, size_t size,
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               enum dma_data_direction direction)
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{
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        BUG_ON(direction == DMA_NONE);
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}
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static inline void
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dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nhwentries,
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             enum dma_data_direction direction)
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{
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        BUG_ON(direction == DMA_NONE);
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}
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static inline void
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dma_sync_single(struct device *dev, dma_addr_t dma_handle, size_t size,
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                enum dma_data_direction direction)
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{
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        flush_write_buffers();
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}
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static inline void
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dma_sync_single_range(struct device *dev, dma_addr_t dma_handle,
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                      unsigned long offset, size_t size,
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                      enum dma_data_direction direction)
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{
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        flush_write_buffers();
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}
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static inline void
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dma_sync_sg(struct device *dev, struct scatterlist *sg, int nelems,
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                 enum dma_data_direction direction)
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{
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        flush_write_buffers();
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}
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static inline int
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dma_supported(struct device *dev, u64 mask)
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{
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        /*
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         * we fall back to GFP_DMA when the mask isn't all 1s,
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         * so we can't guarantee allocations that must be
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         * within a tighter range than GFP_DMA..
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         */
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        if(mask < 0x00ffffff)
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                return 0;
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        return 1;
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}
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static inline int
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dma_set_mask(struct device *dev, u64 mask)
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{
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        if(!dev->dma_mask || !dma_supported(dev, mask))
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                return -EIO;
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        *dev->dma_mask = mask;
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        return 0;
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}
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static inline int
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dma_get_cache_alignment(void)
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{
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        /* no easy way to get cache size on all x86, so return the
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         * maximum possible, to be safe */
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        return (1 << L1_CACHE_SHIFT_MAX);
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}
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#define dma_is_consistent(d)    (1)
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static inline void
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dma_cache_sync(void *vaddr, size_t size,
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               enum dma_data_direction direction)
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{
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        flush_write_buffers();
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}
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#endif