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422 giacomo 1
#ifndef _I386_PGTABLE_H
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#define _I386_PGTABLE_H
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#include <linux/config.h>
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/*
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 * The Linux memory management assumes a three-level page table setup. On
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 * the i386, we use that, but "fold" the mid level into the top-level page
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 * table, so that we physically have the same two-level page table as the
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 * i386 mmu expects.
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 *
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 * This file contains the functions and defines necessary to modify and use
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 * the i386 page table tree.
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 */
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#ifndef __ASSEMBLY__
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#include <asm/processor.h>
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#include <asm/fixmap.h>
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#include <linux/threads.h>
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#ifndef _I386_BITOPS_H
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#include <asm/bitops.h>
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#endif
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#include <linux/slab.h>
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#include <linux/list.h>
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#include <linux/spinlock.h>
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/*
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 * ZERO_PAGE is a global shared page that is always zero: used
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 * for zero-mapped memory areas etc..
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 */
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#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
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extern unsigned long empty_zero_page[1024];
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extern pgd_t swapper_pg_dir[1024];
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extern kmem_cache_t *pgd_cache;
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extern kmem_cache_t *pmd_cache;
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extern spinlock_t pgd_lock;
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extern struct list_head pgd_list;
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void pmd_ctor(void *, kmem_cache_t *, unsigned long);
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void pgd_ctor(void *, kmem_cache_t *, unsigned long);
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void pgd_dtor(void *, kmem_cache_t *, unsigned long);
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void pgtable_cache_init(void);
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void paging_init(void);
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46
#endif /* !__ASSEMBLY__ */
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48
/*
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 * The Linux x86 paging architecture is 'compile-time dual-mode', it
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 * implements both the traditional 2-level x86 page tables and the
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 * newer 3-level PAE-mode page tables.
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 */
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#ifndef __ASSEMBLY__
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#ifdef CONFIG_X86_PAE
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# include <asm/pgtable-3level.h>
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#else
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# include <asm/pgtable-2level.h>
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#endif
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#endif
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#define PMD_SIZE        (1UL << PMD_SHIFT)
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#define PMD_MASK        (~(PMD_SIZE-1))
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#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
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#define PGDIR_MASK      (~(PGDIR_SIZE-1))
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#define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
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#define FIRST_USER_PGD_NR       0
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#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
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#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
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#define TWOLEVEL_PGDIR_SHIFT    22
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#define BOOT_USER_PGD_PTRS (__PAGE_OFFSET >> TWOLEVEL_PGDIR_SHIFT)
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#define BOOT_KERNEL_PGD_PTRS (1024-BOOT_USER_PGD_PTRS)
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77
#ifndef __ASSEMBLY__
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/* Just any arbitrary offset to the start of the vmalloc VM area: the
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 * current 8MB value just means that there will be a 8MB "hole" after the
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 * physical memory until the kernel virtual memory starts.  That means that
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 * any out-of-bounds memory accesses will hopefully be caught.
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 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
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 * area for the same reason. ;)
84
 */
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#define VMALLOC_OFFSET  (8*1024*1024)
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#define VMALLOC_START   (((unsigned long) high_memory + 2*VMALLOC_OFFSET-1) & \
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                                                ~(VMALLOC_OFFSET-1))
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#ifdef CONFIG_HIGHMEM
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# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
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#else
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# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
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#endif
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/*
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 * The 4MB page is guessing..  Detailed in the infamous "Chapter H"
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 * of the Pentium details, but assuming intel did the straightforward
97
 * thing, this bit set in the page directory entry just means that
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 * the page directory entry points directly to a 4MB-aligned block of
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 * memory.
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 */
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#define _PAGE_BIT_PRESENT       0
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#define _PAGE_BIT_RW            1
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#define _PAGE_BIT_USER          2
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#define _PAGE_BIT_PWT           3
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#define _PAGE_BIT_PCD           4
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#define _PAGE_BIT_ACCESSED      5
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#define _PAGE_BIT_DIRTY         6
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#define _PAGE_BIT_PSE           7       /* 4 MB (or 2MB) page, Pentium+, if present.. */
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#define _PAGE_BIT_GLOBAL        8       /* Global TLB entry PPro+ */
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#define _PAGE_PRESENT   0x001
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#define _PAGE_RW        0x002
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#define _PAGE_USER      0x004
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#define _PAGE_PWT       0x008
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#define _PAGE_PCD       0x010
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#define _PAGE_ACCESSED  0x020
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#define _PAGE_DIRTY     0x040
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#define _PAGE_PSE       0x080   /* 4 MB (or 2MB) page, Pentium+, if present.. */
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#define _PAGE_GLOBAL    0x100   /* Global TLB entry PPro+ */
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#define _PAGE_FILE      0x040   /* set:pagecache unset:swap */
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#define _PAGE_PROTNONE  0x080   /* If not present */
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#define _PAGE_TABLE     (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _KERNPG_TABLE   (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define _PAGE_CHG_MASK  (PTE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
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#define PAGE_NONE       __pgprot(_PAGE_PROTNONE | _PAGE_ACCESSED)
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#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_RW | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
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#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_ACCESSED)
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133
#define _PAGE_KERNEL \
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        (_PAGE_PRESENT | _PAGE_RW | _PAGE_DIRTY | _PAGE_ACCESSED)
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136
extern unsigned long __PAGE_KERNEL;
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#define __PAGE_KERNEL_RO        (__PAGE_KERNEL & ~_PAGE_RW)
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#define __PAGE_KERNEL_NOCACHE   (__PAGE_KERNEL | _PAGE_PCD)
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#define __PAGE_KERNEL_LARGE     (__PAGE_KERNEL | _PAGE_PSE)
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#define PAGE_KERNEL             __pgprot(__PAGE_KERNEL)
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#define PAGE_KERNEL_RO          __pgprot(__PAGE_KERNEL_RO)
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#define PAGE_KERNEL_NOCACHE     __pgprot(__PAGE_KERNEL_NOCACHE)
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#define PAGE_KERNEL_LARGE       __pgprot(__PAGE_KERNEL_LARGE)
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146
/*
147
 * The i386 can't do page protection for execute, and considers that
148
 * the same are read. Also, write permissions imply read permissions.
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 * This is the closest we can get..
150
 */
151
#define __P000  PAGE_NONE
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#define __P001  PAGE_READONLY
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#define __P010  PAGE_COPY
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#define __P011  PAGE_COPY
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#define __P100  PAGE_READONLY
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#define __P101  PAGE_READONLY
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#define __P110  PAGE_COPY
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#define __P111  PAGE_COPY
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160
#define __S000  PAGE_NONE
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#define __S001  PAGE_READONLY
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#define __S010  PAGE_SHARED
163
#define __S011  PAGE_SHARED
164
#define __S100  PAGE_READONLY
165
#define __S101  PAGE_READONLY
166
#define __S110  PAGE_SHARED
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#define __S111  PAGE_SHARED
168
 
169
/*
170
 * Define this if things work differently on an i386 and an i486:
171
 * it will (on an i486) warn about kernel memory accesses that are
172
 * done without a 'verify_area(VERIFY_WRITE,..)'
173
 */
174
#undef TEST_VERIFY_AREA
175
 
176
/* page table for 0-4MB for everybody */
177
extern unsigned long pg0[1024];
178
 
179
#define pte_present(x)  ((x).pte_low & (_PAGE_PRESENT | _PAGE_PROTNONE))
180
#define pte_clear(xp)   do { set_pte(xp, __pte(0)); } while (0)
181
 
182
#define pmd_none(x)     (!pmd_val(x))
183
#define pmd_present(x)  (pmd_val(x) & _PAGE_PRESENT)
184
#define pmd_clear(xp)   do { set_pmd(xp, __pmd(0)); } while (0)
185
#define pmd_bad(x)      ((pmd_val(x) & (~PAGE_MASK & ~_PAGE_USER)) != _KERNPG_TABLE)
186
 
187
 
188
#define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
189
 
190
/*
191
 * The following only work if pte_present() is true.
192
 * Undefined behaviour if not..
193
 */
194
static inline int pte_user(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
195
static inline int pte_read(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
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static inline int pte_exec(pte_t pte)           { return (pte).pte_low & _PAGE_USER; }
197
static inline int pte_dirty(pte_t pte)          { return (pte).pte_low & _PAGE_DIRTY; }
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static inline int pte_young(pte_t pte)          { return (pte).pte_low & _PAGE_ACCESSED; }
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static inline int pte_write(pte_t pte)          { return (pte).pte_low & _PAGE_RW; }
200
 
201
/*
202
 * The following only works if pte_present() is not true.
203
 */
204
static inline int pte_file(pte_t pte)           { return (pte).pte_low & _PAGE_FILE; }
205
 
206
static inline pte_t pte_rdprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_USER; return pte; }
207
static inline pte_t pte_exprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_USER; return pte; }
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static inline pte_t pte_mkclean(pte_t pte)      { (pte).pte_low &= ~_PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkold(pte_t pte)        { (pte).pte_low &= ~_PAGE_ACCESSED; return pte; }
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static inline pte_t pte_wrprotect(pte_t pte)    { (pte).pte_low &= ~_PAGE_RW; return pte; }
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static inline pte_t pte_mkread(pte_t pte)       { (pte).pte_low |= _PAGE_USER; return pte; }
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static inline pte_t pte_mkexec(pte_t pte)       { (pte).pte_low |= _PAGE_USER; return pte; }
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static inline pte_t pte_mkdirty(pte_t pte)      { (pte).pte_low |= _PAGE_DIRTY; return pte; }
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static inline pte_t pte_mkyoung(pte_t pte)      { (pte).pte_low |= _PAGE_ACCESSED; return pte; }
215
static inline pte_t pte_mkwrite(pte_t pte)      { (pte).pte_low |= _PAGE_RW; return pte; }
216
 
217
static inline  int ptep_test_and_clear_dirty(pte_t *ptep)       { return test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
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static inline  int ptep_test_and_clear_young(pte_t *ptep)       { return test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); }
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static inline void ptep_set_wrprotect(pte_t *ptep)              { clear_bit(_PAGE_BIT_RW, &ptep->pte_low); }
220
static inline void ptep_mkdirty(pte_t *ptep)                    { set_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); }
221
 
222
/*
223
 * Macro to mark a page protection value as "uncacheable".  On processors which do not support
224
 * it, this is a no-op.
225
 */
226
#define pgprot_noncached(prot)  ((boot_cpu_data.x86 > 3)                                          \
227
                                 ? (__pgprot(pgprot_val(prot) | _PAGE_PCD | _PAGE_PWT)) : (prot))
228
 
229
/*
230
 * Conversion functions: convert a page and protection to a page entry,
231
 * and a page entry and page directory to the page they refer to.
232
 */
233
 
234
#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
235
#define mk_pte_huge(entry) ((entry).pte_low |= _PAGE_PRESENT | _PAGE_PSE)
236
 
237
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
238
{
239
        pte.pte_low &= _PAGE_CHG_MASK;
240
        pte.pte_low |= pgprot_val(newprot);
241
        return pte;
242
}
243
 
244
#define page_pte(page) page_pte_prot(page, __pgprot(0))
245
 
246
#define pmd_page_kernel(pmd) \
247
((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
248
 
249
#ifndef CONFIG_DISCONTIGMEM
250
#define pmd_page(pmd) (pfn_to_page(pmd_val(pmd) >> PAGE_SHIFT))
251
#endif /* !CONFIG_DISCONTIGMEM */
252
 
253
#define pmd_large(pmd) \
254
        ((pmd_val(pmd) & (_PAGE_PSE|_PAGE_PRESENT)) == (_PAGE_PSE|_PAGE_PRESENT))
255
 
256
/*
257
 * the pgd page can be thought of an array like this: pgd_t[PTRS_PER_PGD]
258
 *
259
 * this macro returns the index of the entry in the pgd page which would
260
 * control the given virtual address
261
 */
262
#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
263
 
264
/*
265
 * pgd_offset() returns a (pgd_t *)
266
 * pgd_index() is used get the offset into the pgd page's array of pgd_t's;
267
 */
268
#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
269
 
270
/*
271
 * a shortcut which implies the use of the kernel's pgd, instead
272
 * of a process's
273
 */
274
#define pgd_offset_k(address) pgd_offset(&init_mm, address)
275
 
276
/*
277
 * the pmd page can be thought of an array like this: pmd_t[PTRS_PER_PMD]
278
 *
279
 * this macro returns the index of the entry in the pmd page which would
280
 * control the given virtual address
281
 */
282
#define pmd_index(address) \
283
                (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
284
 
285
/*
286
 * the pte page can be thought of an array like this: pte_t[PTRS_PER_PTE]
287
 *
288
 * this macro returns the index of the entry in the pte page which would
289
 * control the given virtual address
290
 */
291
#define pte_index(address) \
292
                (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
293
#define pte_offset_kernel(dir, address) \
294
        ((pte_t *) pmd_page_kernel(*(dir)) +  pte_index(address))
295
 
296
#if defined(CONFIG_HIGHPTE)
297
#define pte_offset_map(dir, address) \
298
        ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE0) + pte_index(address))
299
#define pte_offset_map_nested(dir, address) \
300
        ((pte_t *)kmap_atomic(pmd_page(*(dir)),KM_PTE1) + pte_index(address))
301
#define pte_unmap(pte) kunmap_atomic(pte, KM_PTE0)
302
#define pte_unmap_nested(pte) kunmap_atomic(pte, KM_PTE1)
303
#else
304
#define pte_offset_map(dir, address) \
305
        ((pte_t *)page_address(pmd_page(*(dir))) + pte_index(address))
306
#define pte_offset_map_nested(dir, address) pte_offset_map(dir, address)
307
#define pte_unmap(pte) do { } while (0)
308
#define pte_unmap_nested(pte) do { } while (0)
309
#endif
310
 
311
#if defined(CONFIG_HIGHPTE) && defined(CONFIG_HIGHMEM4G)
312
typedef u32 pte_addr_t;
313
#endif
314
 
315
#if defined(CONFIG_HIGHPTE) && defined(CONFIG_HIGHMEM64G)
316
typedef u64 pte_addr_t;
317
#endif
318
 
319
#if !defined(CONFIG_HIGHPTE)
320
typedef pte_t *pte_addr_t;
321
#endif
322
 
323
/*
324
 * The i386 doesn't have any external MMU info: the kernel page
325
 * tables contain all the necessary information.
326
 */
327
#define update_mmu_cache(vma,address,pte) do { } while (0)
328
 
329
/* Encode and de-code a swap entry */
330
#define __swp_type(x)                   (((x).val >> 1) & 0x1f)
331
#define __swp_offset(x)                 ((x).val >> 8)
332
#define __swp_entry(type, offset)       ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
333
#define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_low })
334
#define __swp_entry_to_pte(x)           ((pte_t) { (x).val })
335
 
336
#endif /* !__ASSEMBLY__ */
337
 
338
#ifndef CONFIG_DISCONTIGMEM
339
#define kern_addr_valid(addr)   (1)
340
#endif /* !CONFIG_DISCONTIGMEM */
341
 
342
#define io_remap_page_range remap_page_range
343
 
344
#endif /* _I386_PGTABLE_H */