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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 2 | pj | 1 | /* Project: OSLib |
| 2 | * Description: The OS Construction Kit |
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| 3 | * Date: 1.6.2000 |
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| 4 | * Idea by: Luca Abeni & Gerardo Lamastra |
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| 5 | * |
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| 6 | * OSLib is an SO project aimed at developing a common, easy-to-use |
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| 7 | * low-level infrastructure for developing OS kernels and Embedded |
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| 8 | * Applications; it partially derives from the HARTIK project but it |
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| 9 | * currently is independently developed. |
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| 10 | * |
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| 11 | * OSLib is distributed under GPL License, and some of its code has |
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| 12 | * been derived from the Linux kernel source; also some important |
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| 13 | * ideas come from studying the DJGPP go32 extender. |
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| 14 | * |
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| 15 | * We acknowledge the Linux Community, Free Software Foundation, |
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| 16 | * D.J. Delorie and all the other developers who believe in the |
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| 17 | * freedom of software and ideas. |
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| 18 | * |
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| 19 | * For legalese, check out the included GPL license. |
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| 20 | */ |
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| 21 | |||
| 22 | /* Xlib initialization code */ |
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| 23 | |||
| 24 | #include <ll/i386/mem.h> |
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| 25 | #include <ll/i386/cons.h> |
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| 26 | #include <ll/i386/mb-info.h> |
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| 27 | #include <ll/i386/error.h> |
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| 28 | #include <ll/i386/pit.h> |
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| 29 | #include <ll/i386/pic.h> |
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| 30 | |||
| 31 | #include <ll/i386/tss-ctx.h> |
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| 32 | #include <ll/i386/hw-arch.h> |
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| 33 | |||
| 40 | pj | 34 | FILE(X-Init); |
| 2 | pj | 35 | |
| 40 | pj | 36 | extern DWORD ll_irq_table[256]; |
| 2 | pj | 37 | |
| 38 | #ifdef __VIRCSW__ |
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| 39 | int activeInt = 0; |
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| 40 | #endif |
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| 41 | |||
| 42 | /* Assembly external routines! */ |
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| 43 | /* Setup the TR register of the 80386, to initialize context switch */ |
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| 44 | |||
| 45 | extern void init_TR(WORD v); |
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| 40 | pj | 46 | TSS main_tss; |
| 2 | pj | 47 | |
| 40 | pj | 48 | /* Architecture definition */ |
| 49 | LL_ARCH ll_arch; |
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| 2 | pj | 50 | |
| 40 | pj | 51 | /* The following stuff is in llCxA.Asm/S */ |
| 2 | pj | 52 | |
| 53 | static void dummyfun(int i) |
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| 54 | { |
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| 40 | pj | 55 | #if 0 |
| 56 | if (i < 32) { |
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| 57 | cputs("Unhandled Exc occured!!!\n"); |
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| 58 | } else { |
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| 59 | cputs("Unhandled Int occured!!!\n"); |
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| 60 | } |
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| 61 | #else |
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| 2 | pj | 62 | message("Unhandled Exc or Int %d occured!!!\n", i); |
| 40 | pj | 63 | #endif |
| 64 | halt(); |
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| 2 | pj | 65 | } |
| 66 | |||
| 40 | pj | 67 | void l1_int_bind(int i, void *f) |
| 2 | pj | 68 | { |
| 40 | pj | 69 | ll_irq_table[i] = (DWORD)f; |
| 2 | pj | 70 | } |
| 71 | |||
| 72 | void *l1_init(void) |
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| 73 | { |
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| 40 | pj | 74 | register int i; |
| 75 | struct ll_cpuInfo cpuInfo; |
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| 648 | mauro | 76 | extern unsigned char X86_apic; |
| 77 | extern unsigned char X86_tsc; |
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| 40 | pj | 78 | extern BYTE X86_fpu; |
| 619 | mauro | 79 | LIN_ADDR b; |
| 40 | pj | 80 | |
| 81 | for(i = 0; i < 256; i++) { |
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| 82 | ll_irq_table[i] = (DWORD)dummyfun; |
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| 83 | } |
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| 84 | |||
| 85 | X86_get_CPU(&cpuInfo); |
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| 86 | X86_get_FPU(); |
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| 87 | ll_arch.x86.arch = __LL_ARCH__; |
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| 88 | ll_arch.x86.cpu = cpuInfo.X86_cpu; |
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| 89 | ll_arch.x86.fpu = X86_fpu; |
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| 90 | memcpy(&(ll_arch.x86.vendor), &(cpuInfo.X86_vendor_1), 12); |
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| 91 | |||
| 704 | giacomo | 92 | X86_apic = (cpuInfo.X86_StandardFeature>>9) & 1; |
| 93 | X86_tsc = (cpuInfo.X86_StandardFeature>>4) & 1; |
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| 619 | mauro | 94 | |
| 40 | pj | 95 | /* TODO! Need to map featuresXXX & Signature onto ll_arch! */ |
| 96 | /* TODO! Need to check for CPU bugs!! */ |
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| 97 | |||
| 2 | pj | 98 | #ifdef __LL_DEBUG__ |
| 40 | pj | 99 | message("LL Architecture: %s\n", __LL_ARCH__); |
| 100 | message("CPU : %u\nFPU : %u\n", cpuInfo.X86_cpu, X86_fpu); |
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| 101 | message("Signature : 0x%lx\nVendor: %s\n", cpuInfo.X86_signature, |
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| 102 | ll_arch.x86.vendor); |
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| 103 | message("Features #1: 0x%lx\n", cpuInfo.X86_IntelFeature_1); |
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| 104 | message("Features #2: 0x%lx\n", cpuInfo.X86_IntelFeature_2); |
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| 105 | message("Features #3: 0x%lx\n", cpuInfo.X86_StandardFeature); |
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| 619 | mauro | 106 | message("Has APIC: %s\n", X86_apic); |
| 107 | message("Has TSC: %s\n", X86_tsc); |
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| 40 | pj | 108 | #endif /* __LL_DEBUG__ */ |
| 619 | mauro | 109 | |
| 40 | pj | 110 | IDT_init(); |
| 2 | pj | 111 | |
| 40 | pj | 112 | /* Init coprocessor & assign it to main() */ |
| 113 | /* OK... Now I know the sense of all this... : |
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| 114 | We need a initial value for the FPU context (to be used for creating |
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| 115 | new FPU contexts, as init value)... |
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| 116 | ... And we get it in this strange way!!!! |
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| 117 | */ |
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| 118 | reset_fpu(); |
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| 119 | init_fpu(); |
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| 120 | |||
| 121 | /* Init PIC controllers & unmask timer */ |
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| 122 | PIC_init(); |
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| 123 | |||
| 124 | /* Set the TR initial value */ |
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| 125 | b = (LIN_ADDR)(&main_tss); |
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| 126 | GDT_place(MAIN_SEL, (DWORD)b, sizeof(TSS), FREE_TSS386, GRAN_16); |
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| 127 | init_TR(MAIN_SEL); |
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| 128 | |||
| 129 | return mbi_address(); |
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| 2 | pj | 130 | } |
| 131 | |||
| 132 | |||
| 133 | void l1_end(void) |
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| 134 | { |
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| 40 | pj | 135 | outp(0x21,0xFF); |
| 136 | outp(0xA1,0xFF); |
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| 137 | /* Back to DOS settings */ |
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| 138 | PIC_end(); |
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| 139 | /* Reset the timer chip according DOS specification */ |
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| 140 | /* Mode: Binary/Mode 3/16 bit Time_const/Counter 0 */ |
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| 2 | pj | 141 | #if 0 |
| 40 | pj | 142 | outp(0x43,0x36); |
| 143 | /* Time_const = 65536; write 0 in CTR */ |
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| 144 | outp(0x40,0); |
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| 145 | outp(0x40,0); |
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| 2 | pj | 146 | #endif |
| 40 | pj | 147 | pit_init(0, TMR_MD3, 0); /* Timer 0, Mode 3, Time constant 0 */ |
| 148 | if(ll_arch.x86.cpu > 4) { |
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| 149 | pit_init(1, TMR_MD2, 18); |
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| 150 | } else { |
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| 151 | pit_init(2, TMR_MD0, 0); |
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| 152 | outp(0x61, 0); /* Stop channel 2 */ |
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| 153 | } |
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| 2 | pj | 154 | } |