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Rev | Author | Line No. | Line |
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170 | giacomo | 1 | /* |
2 | bt848.h - Bt848 register offsets |
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3 | |||
4 | Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de) |
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5 | |||
6 | This program is free software; you can redistribute it and/or modify |
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7 | it under the terms of the GNU General Public License as published by |
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8 | the Free Software Foundation; either version 2 of the License, or |
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9 | (at your option) any later version. |
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10 | |||
11 | This program is distributed in the hope that it will be useful, |
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12 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | GNU General Public License for more details. |
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15 | |||
16 | You should have received a copy of the GNU General Public License |
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17 | along with this program; if not, write to the Free Software |
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18 | Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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19 | */ |
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20 | |||
21 | #ifndef _BT848_H_ |
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22 | #define _BT848_H_ |
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23 | |||
24 | #ifndef PCI_VENDOR_ID_BROOKTREE |
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25 | #define PCI_VENDOR_ID_BROOKTREE 0x109e |
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26 | #endif |
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27 | #ifndef PCI_DEVICE_ID_BT848 |
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28 | #define PCI_DEVICE_ID_BT848 0x350 |
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29 | #endif |
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30 | #ifndef PCI_DEVICE_ID_BT849 |
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31 | #define PCI_DEVICE_ID_BT849 0x351 |
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32 | #endif |
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33 | #ifndef PCI_DEVICE_ID_BT878 |
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34 | #define PCI_DEVICE_ID_BT878 0x36e |
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35 | #endif |
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36 | #ifndef PCI_DEVICE_ID_BT879 |
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37 | #define PCI_DEVICE_ID_BT879 0x36f |
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38 | #endif |
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39 | |||
40 | |||
41 | /* Brooktree 848 registers */ |
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42 | |||
43 | #define BT848_DSTATUS 0x000 |
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44 | #define BT848_DSTATUS_PRES (1<<7) |
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45 | #define BT848_DSTATUS_HLOC (1<<6) |
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46 | #define BT848_DSTATUS_FIELD (1<<5) |
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47 | #define BT848_DSTATUS_NUML (1<<4) |
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48 | #define BT848_DSTATUS_CSEL (1<<3) |
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49 | #define BT848_DSTATUS_PLOCK (1<<2) |
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50 | #define BT848_DSTATUS_LOF (1<<1) |
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51 | #define BT848_DSTATUS_COF (1<<0) |
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52 | |||
53 | #define BT848_IFORM 0x004 |
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54 | #define BT848_IFORM_HACTIVE (1<<7) |
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55 | #define BT848_IFORM_MUXSEL (3<<5) |
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56 | #define BT848_IFORM_MUX0 (2<<5) |
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57 | #define BT848_IFORM_MUX1 (3<<5) |
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58 | #define BT848_IFORM_MUX2 (1<<5) |
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59 | #define BT848_IFORM_XTSEL (3<<3) |
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60 | #define BT848_IFORM_XT0 (1<<3) |
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61 | #define BT848_IFORM_XT1 (2<<3) |
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62 | #define BT848_IFORM_XTAUTO (3<<3) |
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63 | #define BT848_IFORM_XTBOTH (3<<3) |
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64 | #define BT848_IFORM_NTSC 1 |
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65 | #define BT848_IFORM_NTSC_J 2 |
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66 | #define BT848_IFORM_PAL_BDGHI 3 |
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67 | #define BT848_IFORM_PAL_M 4 |
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68 | #define BT848_IFORM_PAL_N 5 |
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69 | #define BT848_IFORM_SECAM 6 |
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70 | #define BT848_IFORM_PAL_NC 7 |
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71 | #define BT848_IFORM_AUTO 0 |
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72 | #define BT848_IFORM_NORM 7 |
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73 | |||
74 | #define BT848_TDEC 0x008 |
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75 | #define BT848_TDEC_DEC_FIELD (1<<7) |
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76 | #define BT848_TDEC_FLDALIGN (1<<6) |
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77 | #define BT848_TDEC_DEC_RAT (0x1f) |
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78 | |||
79 | #define BT848_E_CROP 0x00C |
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80 | #define BT848_O_CROP 0x08C |
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81 | |||
82 | #define BT848_E_VDELAY_LO 0x010 |
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83 | #define BT848_O_VDELAY_LO 0x090 |
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84 | |||
85 | #define BT848_E_VACTIVE_LO 0x014 |
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86 | #define BT848_O_VACTIVE_LO 0x094 |
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87 | |||
88 | #define BT848_E_HDELAY_LO 0x018 |
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89 | #define BT848_O_HDELAY_LO 0x098 |
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90 | |||
91 | #define BT848_E_HACTIVE_LO 0x01C |
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92 | #define BT848_O_HACTIVE_LO 0x09C |
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93 | |||
94 | #define BT848_E_HSCALE_HI 0x020 |
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95 | #define BT848_O_HSCALE_HI 0x0A0 |
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96 | |||
97 | #define BT848_E_HSCALE_LO 0x024 |
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98 | #define BT848_O_HSCALE_LO 0x0A4 |
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99 | |||
100 | #define BT848_BRIGHT 0x028 |
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101 | |||
102 | #define BT848_E_CONTROL 0x02C |
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103 | #define BT848_O_CONTROL 0x0AC |
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104 | #define BT848_CONTROL_LNOTCH (1<<7) |
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105 | #define BT848_CONTROL_COMP (1<<6) |
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106 | #define BT848_CONTROL_LDEC (1<<5) |
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107 | #define BT848_CONTROL_CBSENSE (1<<4) |
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108 | #define BT848_CONTROL_CON_MSB (1<<2) |
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109 | #define BT848_CONTROL_SAT_U_MSB (1<<1) |
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110 | #define BT848_CONTROL_SAT_V_MSB (1<<0) |
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111 | |||
112 | #define BT848_CONTRAST_LO 0x030 |
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113 | #define BT848_SAT_U_LO 0x034 |
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114 | #define BT848_SAT_V_LO 0x038 |
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115 | #define BT848_HUE 0x03C |
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116 | |||
117 | #define BT848_E_SCLOOP 0x040 |
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118 | #define BT848_O_SCLOOP 0x0C0 |
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119 | #define BT848_SCLOOP_CAGC (1<<6) |
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120 | #define BT848_SCLOOP_CKILL (1<<5) |
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121 | #define BT848_SCLOOP_HFILT_AUTO (0<<3) |
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122 | #define BT848_SCLOOP_HFILT_CIF (1<<3) |
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123 | #define BT848_SCLOOP_HFILT_QCIF (2<<3) |
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124 | #define BT848_SCLOOP_HFILT_ICON (3<<3) |
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125 | |||
126 | #define BT848_SCLOOP_PEAK (1<<7) |
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127 | #define BT848_SCLOOP_HFILT_MINP (1<<3) |
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128 | #define BT848_SCLOOP_HFILT_MEDP (2<<3) |
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129 | #define BT848_SCLOOP_HFILT_MAXP (3<<3) |
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130 | |||
131 | |||
132 | #define BT848_OFORM 0x048 |
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133 | #define BT848_OFORM_RANGE (1<<7) |
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134 | #define BT848_OFORM_CORE0 (0<<5) |
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135 | #define BT848_OFORM_CORE8 (1<<5) |
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136 | #define BT848_OFORM_CORE16 (2<<5) |
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137 | #define BT848_OFORM_CORE32 (3<<5) |
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138 | |||
139 | #define BT848_E_VSCALE_HI 0x04C |
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140 | #define BT848_O_VSCALE_HI 0x0CC |
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141 | #define BT848_VSCALE_YCOMB (1<<7) |
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142 | #define BT848_VSCALE_COMB (1<<6) |
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143 | #define BT848_VSCALE_INT (1<<5) |
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144 | #define BT848_VSCALE_HI 15 |
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145 | |||
146 | #define BT848_E_VSCALE_LO 0x050 |
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147 | #define BT848_O_VSCALE_LO 0x0D0 |
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148 | #define BT848_TEST 0x054 |
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149 | #define BT848_ADELAY 0x060 |
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150 | #define BT848_BDELAY 0x064 |
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151 | |||
152 | #define BT848_ADC 0x068 |
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153 | #define BT848_ADC_RESERVED (2<<6) |
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154 | #define BT848_ADC_SYNC_T (1<<5) |
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155 | #define BT848_ADC_AGC_EN (1<<4) |
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156 | #define BT848_ADC_CLK_SLEEP (1<<3) |
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157 | #define BT848_ADC_Y_SLEEP (1<<2) |
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158 | #define BT848_ADC_C_SLEEP (1<<1) |
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159 | #define BT848_ADC_CRUSH (1<<0) |
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160 | |||
161 | #define BT848_E_VTC 0x06C |
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162 | #define BT848_O_VTC 0x0EC |
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163 | #define BT848_VTC_HSFMT (1<<7) |
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164 | #define BT848_VTC_VFILT_2TAP 0 |
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165 | #define BT848_VTC_VFILT_3TAP 1 |
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166 | #define BT848_VTC_VFILT_4TAP 2 |
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167 | #define BT848_VTC_VFILT_5TAP 3 |
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168 | |||
169 | #define BT848_SRESET 0x07C |
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170 | |||
171 | #define BT848_COLOR_FMT 0x0D4 |
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172 | #define BT848_COLOR_FMT_O_RGB32 (0<<4) |
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173 | #define BT848_COLOR_FMT_O_RGB24 (1<<4) |
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174 | #define BT848_COLOR_FMT_O_RGB16 (2<<4) |
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175 | #define BT848_COLOR_FMT_O_RGB15 (3<<4) |
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176 | #define BT848_COLOR_FMT_O_YUY2 (4<<4) |
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177 | #define BT848_COLOR_FMT_O_BtYUV (5<<4) |
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178 | #define BT848_COLOR_FMT_O_Y8 (6<<4) |
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179 | #define BT848_COLOR_FMT_O_RGB8 (7<<4) |
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180 | #define BT848_COLOR_FMT_O_YCrCb422 (8<<4) |
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181 | #define BT848_COLOR_FMT_O_YCrCb411 (9<<4) |
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182 | #define BT848_COLOR_FMT_O_RAW (14<<4) |
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183 | #define BT848_COLOR_FMT_E_RGB32 0 |
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184 | #define BT848_COLOR_FMT_E_RGB24 1 |
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185 | #define BT848_COLOR_FMT_E_RGB16 2 |
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186 | #define BT848_COLOR_FMT_E_RGB15 3 |
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187 | #define BT848_COLOR_FMT_E_YUY2 4 |
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188 | #define BT848_COLOR_FMT_E_BtYUV 5 |
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189 | #define BT848_COLOR_FMT_E_Y8 6 |
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190 | #define BT848_COLOR_FMT_E_RGB8 7 |
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191 | #define BT848_COLOR_FMT_E_YCrCb422 8 |
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192 | #define BT848_COLOR_FMT_E_YCrCb411 9 |
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193 | #define BT848_COLOR_FMT_E_RAW 14 |
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194 | |||
195 | #define BT848_COLOR_FMT_RGB32 0x00 |
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196 | #define BT848_COLOR_FMT_RGB24 0x11 |
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197 | #define BT848_COLOR_FMT_RGB16 0x22 |
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198 | #define BT848_COLOR_FMT_RGB15 0x33 |
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199 | #define BT848_COLOR_FMT_YUY2 0x44 |
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200 | #define BT848_COLOR_FMT_BtYUV 0x55 |
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201 | #define BT848_COLOR_FMT_Y8 0x66 |
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202 | #define BT848_COLOR_FMT_RGB8 0x77 |
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203 | #define BT848_COLOR_FMT_YCrCb422 0x88 |
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204 | #define BT848_COLOR_FMT_YCrCb411 0x99 |
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205 | #define BT848_COLOR_FMT_RAW 0xee |
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206 | |||
207 | #define BT848_COLOR_CTL 0x0D8 |
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208 | #define BT848_COLOR_CTL_EXT_FRMRATE (1<<7) |
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209 | #define BT848_COLOR_CTL_COLOR_BARS (1<<6) |
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210 | #define BT848_COLOR_CTL_RGB_DED (1<<5) |
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211 | #define BT848_COLOR_CTL_GAMMA (1<<4) |
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212 | #define BT848_COLOR_CTL_WSWAP_ODD (1<<3) |
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213 | #define BT848_COLOR_CTL_WSWAP_EVEN (1<<2) |
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214 | #define BT848_COLOR_CTL_BSWAP_ODD (1<<1) |
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215 | #define BT848_COLOR_CTL_BSWAP_EVEN (1<<0) |
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216 | |||
217 | #define BT848_CAP_CTL 0x0DC |
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218 | #define BT848_CAP_CTL_DITH_FRAME (1<<4) |
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219 | #define BT848_CAP_CTL_CAPTURE_VBI_ODD (1<<3) |
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220 | #define BT848_CAP_CTL_CAPTURE_VBI_EVEN (1<<2) |
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221 | #define BT848_CAP_CTL_CAPTURE_ODD (1<<1) |
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222 | #define BT848_CAP_CTL_CAPTURE_EVEN (1<<0) |
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223 | |||
224 | #define BT848_VBI_PACK_SIZE 0x0E0 |
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225 | |||
226 | #define BT848_VBI_PACK_DEL 0x0E4 |
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227 | #define BT848_VBI_PACK_DEL_VBI_HDELAY 0xfc |
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228 | #define BT848_VBI_PACK_DEL_EXT_FRAME 2 |
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229 | #define BT848_VBI_PACK_DEL_VBI_PKT_HI 1 |
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230 | |||
231 | |||
232 | #define BT848_INT_STAT 0x100 |
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233 | #define BT848_INT_MASK 0x104 |
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234 | |||
235 | #define BT848_INT_ETBF (1<<23) |
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236 | |||
237 | #define BT848_INT_RISCS (0xf<<28) |
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238 | #define BT848_INT_RISC_EN (1<<27) |
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239 | #define BT848_INT_RACK (1<<25) |
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240 | #define BT848_INT_FIELD (1<<24) |
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241 | #define BT848_INT_SCERR (1<<19) |
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242 | #define BT848_INT_OCERR (1<<18) |
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243 | #define BT848_INT_PABORT (1<<17) |
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244 | #define BT848_INT_RIPERR (1<<16) |
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245 | #define BT848_INT_PPERR (1<<15) |
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246 | #define BT848_INT_FDSR (1<<14) |
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247 | #define BT848_INT_FTRGT (1<<13) |
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248 | #define BT848_INT_FBUS (1<<12) |
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249 | #define BT848_INT_RISCI (1<<11) |
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250 | #define BT848_INT_GPINT (1<<9) |
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251 | #define BT848_INT_I2CDONE (1<<8) |
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252 | #define BT848_INT_VPRES (1<<5) |
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253 | #define BT848_INT_HLOCK (1<<4) |
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254 | #define BT848_INT_OFLOW (1<<3) |
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255 | #define BT848_INT_HSYNC (1<<2) |
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256 | #define BT848_INT_VSYNC (1<<1) |
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257 | #define BT848_INT_FMTCHG (1<<0) |
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258 | |||
259 | |||
260 | #define BT848_GPIO_DMA_CTL 0x10C |
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261 | #define BT848_GPIO_DMA_CTL_GPINTC (1<<15) |
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262 | #define BT848_GPIO_DMA_CTL_GPINTI (1<<14) |
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263 | #define BT848_GPIO_DMA_CTL_GPWEC (1<<13) |
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264 | #define BT848_GPIO_DMA_CTL_GPIOMODE (3<<11) |
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265 | #define BT848_GPIO_DMA_CTL_GPCLKMODE (1<<10) |
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266 | #define BT848_GPIO_DMA_CTL_PLTP23_4 (0<<6) |
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267 | #define BT848_GPIO_DMA_CTL_PLTP23_8 (1<<6) |
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268 | #define BT848_GPIO_DMA_CTL_PLTP23_16 (2<<6) |
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269 | #define BT848_GPIO_DMA_CTL_PLTP23_32 (3<<6) |
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270 | #define BT848_GPIO_DMA_CTL_PLTP1_4 (0<<4) |
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271 | #define BT848_GPIO_DMA_CTL_PLTP1_8 (1<<4) |
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272 | #define BT848_GPIO_DMA_CTL_PLTP1_16 (2<<4) |
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273 | #define BT848_GPIO_DMA_CTL_PLTP1_32 (3<<4) |
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274 | #define BT848_GPIO_DMA_CTL_PKTP_4 (0<<2) |
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275 | #define BT848_GPIO_DMA_CTL_PKTP_8 (1<<2) |
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276 | #define BT848_GPIO_DMA_CTL_PKTP_16 (2<<2) |
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277 | #define BT848_GPIO_DMA_CTL_PKTP_32 (3<<2) |
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278 | #define BT848_GPIO_DMA_CTL_RISC_ENABLE (1<<1) |
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279 | #define BT848_GPIO_DMA_CTL_FIFO_ENABLE (1<<0) |
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280 | |||
281 | #define BT848_I2C 0x110 |
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282 | #define BT848_I2C_DIV (0xf<<4) |
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283 | #define BT848_I2C_SYNC (1<<3) |
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284 | #define BT848_I2C_W3B (1<<2) |
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285 | #define BT848_I2C_SCL (1<<1) |
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286 | #define BT848_I2C_SDA (1<<0) |
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287 | |||
288 | |||
289 | #define BT848_RISC_STRT_ADD 0x114 |
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290 | #define BT848_GPIO_OUT_EN 0x118 |
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291 | #define BT848_GPIO_REG_INP 0x11C |
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292 | #define BT848_RISC_COUNT 0x120 |
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293 | #define BT848_GPIO_DATA 0x200 |
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294 | |||
295 | |||
296 | /* Bt848 RISC commands */ |
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297 | |||
298 | /* only for the SYNC RISC command */ |
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299 | #define BT848_FIFO_STATUS_FM1 0x06 |
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300 | #define BT848_FIFO_STATUS_FM3 0x0e |
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301 | #define BT848_FIFO_STATUS_SOL 0x02 |
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302 | #define BT848_FIFO_STATUS_EOL4 0x01 |
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303 | #define BT848_FIFO_STATUS_EOL3 0x0d |
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304 | #define BT848_FIFO_STATUS_EOL2 0x09 |
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305 | #define BT848_FIFO_STATUS_EOL1 0x05 |
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306 | #define BT848_FIFO_STATUS_VRE 0x04 |
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307 | #define BT848_FIFO_STATUS_VRO 0x0c |
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308 | #define BT848_FIFO_STATUS_PXV 0x00 |
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309 | |||
310 | #define BT848_RISC_RESYNC (1<<15) |
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311 | |||
312 | /* WRITE and SKIP */ |
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313 | /* disable which bytes of each DWORD */ |
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314 | #define BT848_RISC_BYTE0 (1<<12) |
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315 | #define BT848_RISC_BYTE1 (1<<13) |
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316 | #define BT848_RISC_BYTE2 (1<<14) |
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317 | #define BT848_RISC_BYTE3 (1<<15) |
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318 | #define BT848_RISC_BYTE_ALL (0x0f<<12) |
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319 | #define BT848_RISC_BYTE_NONE 0 |
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320 | /* cause RISCI */ |
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321 | #define BT848_RISC_IRQ (1<<24) |
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322 | /* RISC command is last one in this line */ |
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323 | #define BT848_RISC_EOL (1<<26) |
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324 | /* RISC command is first one in this line */ |
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325 | #define BT848_RISC_SOL (1<<27) |
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326 | |||
327 | #define BT848_RISC_WRITE (0x01<<28) |
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328 | #define BT848_RISC_SKIP (0x02<<28) |
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329 | #define BT848_RISC_WRITEC (0x05<<28) |
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330 | #define BT848_RISC_JUMP (0x07<<28) |
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331 | #define BT848_RISC_SYNC (0x08<<28) |
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332 | |||
333 | #define BT848_RISC_WRITE123 (0x09<<28) |
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334 | #define BT848_RISC_SKIP123 (0x0a<<28) |
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335 | #define BT848_RISC_WRITE1S23 (0x0b<<28) |
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336 | |||
337 | |||
338 | |||
339 | /* Bt848A and higher only !! */ |
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340 | #define BT848_TGLB 0x080 |
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341 | #define BT848_TGCTRL 0x084 |
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342 | #define BT848_FCAP 0x0E8 |
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343 | #define BT848_PLL_F_LO 0x0F0 |
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344 | #define BT848_PLL_F_HI 0x0F4 |
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345 | |||
346 | #define BT848_PLL_XCI 0x0F8 |
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347 | #define BT848_PLL_X (1<<7) |
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348 | #define BT848_PLL_C (1<<6) |
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349 | |||
350 | /* Bt878 register */ |
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351 | |||
352 | #define BT878_DEVCTRL 0x40 |
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353 | #define BT878_EN_TBFX 0x02 |
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354 | #define BT878_EN_VSFX 0x04 |
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355 | |||
356 | #endif |