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425 giacomo 1
#include <media/saa7146_vv.h>
2
 
3
#define my_min(type,x,y) \
4
        ({ type __x = (x), __y = (y); __x < __y ? __x: __y; })
5
#define my_max(type,x,y) \
6
        ({ type __x = (x), __y = (y); __x > __y ? __x: __y; })
7
 
8
static void calculate_output_format_register(struct saa7146_dev* saa, u32 palette, u32* clip_format)
9
{
10
        /* clear out the necessary bits */
11
        *clip_format &= 0x0000ffff;    
12
        /* set these bits new */
13
        *clip_format |=  (( ((palette&0xf00)>>8) << 30) | ((palette&0x00f) << 24) | (((palette&0x0f0)>>4) << 16));
14
}
15
 
16
static void calculate_bcs_ctrl_register(struct saa7146_dev *dev, int brightness, int contrast, int colour, u32 *bcs_ctrl)
17
{
18
        *bcs_ctrl = ((brightness << 24) | (contrast << 16) | (colour <<  0));
19
}
20
 
21
static void calculate_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync, u32* hps_ctrl)
22
{
23
        *hps_ctrl &= ~(MASK_30 | MASK_31 | MASK_28);
24
        *hps_ctrl |= (source << 30) | (sync << 28);
25
}
26
 
27
static void calculate_hxo_and_hyo(struct saa7146_vv *vv, u32* hps_h_scale, u32* hps_ctrl)
28
{
29
        int hyo = 0, hxo = 0;
30
 
31
        hyo = vv->standard->v_offset;
32
        hxo = vv->standard->h_offset;
33
 
34
        *hps_h_scale    &= ~(MASK_B0 | 0xf00);
35
        *hps_h_scale    |= (hxo <<  0);
36
 
37
        *hps_ctrl       &= ~(MASK_W0 | MASK_B2);
38
        *hps_ctrl       |= (hyo << 12);
39
}
40
 
41
/* helper functions for the calculation of the horizontal- and vertical
42
   scaling registers, clip-format-register etc ...
43
   these functions take pointers to the (most-likely read-out
44
   original-values) and manipulate them according to the requested
45
   changes.
46
*/
47
 
48
/* hps_coeff used for CXY and CXUV; scale 1/1 -> scale 1/64 */
49
static struct {
50
        u16 hps_coeff;
51
        u16 weight_sum;
52
} hps_h_coeff_tab [] = {
53
        {0x00,   2}, {0x02,   4}, {0x00,   4}, {0x06,   8}, {0x02,   8},
54
        {0x08,   8}, {0x00,   8}, {0x1E,  16}, {0x0E,   8}, {0x26,   8},
55
        {0x06,   8}, {0x42,   8}, {0x02,   8}, {0x80,   8}, {0x00,   8},
56
        {0xFE,  16}, {0xFE,   8}, {0x7E,   8}, {0x7E,   8}, {0x3E,   8},
57
        {0x3E,   8}, {0x1E,   8}, {0x1E,   8}, {0x0E,   8}, {0x0E,   8},
58
        {0x06,   8}, {0x06,   8}, {0x02,   8}, {0x02,   8}, {0x00,   8},
59
        {0x00,   8}, {0xFE,  16}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
60
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
61
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8},
62
        {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0xFE,   8}, {0x7E,   8},
63
        {0x7E,   8}, {0x3E,   8}, {0x3E,   8}, {0x1E,   8}, {0x1E,   8},
64
        {0x0E,   8}, {0x0E,   8}, {0x06,   8}, {0x06,   8}, {0x02,   8},
65
        {0x02,   8}, {0x00,   8}, {0x00,   8}, {0xFE,  16}
66
};
67
 
68
/* table of attenuation values for horizontal scaling */
69
u8 h_attenuation[] = { 1, 2, 4, 8, 2, 4, 8, 16, 0};
70
 
71
/* calculate horizontal scale registers */
72
static int calculate_h_scale_registers(struct saa7146_dev *dev,
73
        int in_x, int out_x, int flip_lr,
74
        u32* hps_ctrl, u32* hps_v_gain, u32* hps_h_prescale, u32* hps_h_scale)
75
{
76
        /* horizontal prescaler */
77
        u32 dcgx = 0, xpsc = 0, xacm = 0, cxy = 0, cxuv = 0;   
78
        /* horizontal scaler */
79
        u32 xim = 0, xp = 0, xsci =0;                          
80
        /* vertical scale & gain */
81
        u32 pfuv = 0;                                          
82
 
83
        /* helper variables */
84
        u32 h_atten = 0, i = 0;
85
 
86
        if ( 0 == out_x ) {
87
                return -EINVAL;
88
        }
89
 
90
        /* mask out vanity-bit */
91
        *hps_ctrl &= ~MASK_29;
92
 
93
        /* calculate prescale-(xspc)-value:     [n   .. 1/2) : 1
94
                                                [1/2 .. 1/3) : 2
95
                                                [1/3 .. 1/4) : 3
96
                                                ...             */
97
        if (in_x > out_x) {
98
                xpsc = in_x / out_x;
99
        }
100
        else {
101
                /* zooming */
102
                xpsc = 1;                                              
103
        }
104
 
105
        /* if flip_lr-bit is set, number of pixels after
106
           horizontal prescaling must be < 384 */
107
        if ( 0 != flip_lr ) {
108
 
109
                /* set vanity bit */
110
                *hps_ctrl |= MASK_29;
111
 
112
                while (in_x / xpsc >= 384 )
113
                        xpsc++;
114
        }
115
        /* if zooming is wanted, number of pixels after
116
           horizontal prescaling must be < 768 */
117
        else {
118
                while ( in_x / xpsc >= 768 )
119
                        xpsc++;
120
        }
121
 
122
        /* maximum prescale is 64 (p.69) */
123
        if ( xpsc > 64 )
124
                xpsc = 64;
125
 
126
        /* keep xacm clear*/
127
        xacm = 0;
128
 
129
        /* set horizontal filter parameters (CXY = CXUV) */
130
        cxy = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].hps_coeff;
131
        cxuv = cxy;
132
 
133
        /* calculate and set horizontal fine scale (xsci) */
134
 
135
        /* bypass the horizontal scaler ? */
136
        if ( (in_x == out_x) && ( 1 == xpsc ) )
137
                xsci = 0x400;
138
        else   
139
                xsci = ( (1024 * in_x) / (out_x * xpsc) ) + xpsc;
140
 
141
        /* set start phase for horizontal fine scale (xp) to 0 */      
142
        xp = 0;
143
 
144
        /* set xim, if we bypass the horizontal scaler */
145
        if ( 0x400 == xsci )
146
                xim = 1;
147
        else
148
                xim = 0;
149
 
150
        /* if the prescaler is bypassed, enable horizontal
151
           accumulation mode (xacm) and clear dcgx */
152
        if( 1 == xpsc ) {
153
                xacm = 1;
154
                dcgx = 0;
155
        } else {
156
                xacm = 0;
157
                /* get best match in the table of attenuations
158
                   for horizontal scaling */
159
                h_atten = hps_h_coeff_tab[( (xpsc - 1) < 63 ? (xpsc - 1) : 63 )].weight_sum;
160
 
161
                for (i = 0; h_attenuation[i] != 0; i++) {
162
                        if (h_attenuation[i] >= h_atten)
163
                                break;
164
                }
165
 
166
                dcgx = i;
167
        }
168
 
169
        /* the horizontal scaling increment controls the UV filter
170
           to reduce the bandwith to improve the display quality,
171
           so set it ... */
172
        if ( xsci == 0x400)
173
                pfuv = 0x00;
174
        else if ( xsci < 0x600)
175
                pfuv = 0x01;
176
        else if ( xsci < 0x680)
177
                pfuv = 0x11;
178
        else if ( xsci < 0x700)
179
                pfuv = 0x22;
180
        else
181
                pfuv = 0x33;
182
 
183
 
184
        *hps_v_gain  &= MASK_W0|MASK_B2;
185
        *hps_v_gain  |= (pfuv << 24);  
186
 
187
        *hps_h_scale    &= ~(MASK_W1 | 0xf000);
188
        *hps_h_scale    |= (xim << 31) | (xp << 24) | (xsci << 12);
189
 
190
        *hps_h_prescale |= (dcgx << 27) | ((xpsc-1) << 18) | (xacm << 17) | (cxy << 8) | (cxuv << 0);
191
 
192
        return 0;
193
}
194
 
195
static struct {
196
        u16 hps_coeff;
197
        u16 weight_sum;
198
} hps_v_coeff_tab [] = {
199
 {0x0100,   2},  {0x0102,   4},  {0x0300,   4},  {0x0106,   8},  {0x0502,   8},
200
 {0x0708,   8},  {0x0F00,   8},  {0x011E,  16},  {0x110E,  16},  {0x1926,  16},
201
 {0x3906,  16},  {0x3D42,  16},  {0x7D02,  16},  {0x7F80,  16},  {0xFF00,  16},
202
 {0x01FE,  32},  {0x01FE,  32},  {0x817E,  32},  {0x817E,  32},  {0xC13E,  32},
203
 {0xC13E,  32},  {0xE11E,  32},  {0xE11E,  32},  {0xF10E,  32},  {0xF10E,  32},
204
 {0xF906,  32},  {0xF906,  32},  {0xFD02,  32},  {0xFD02,  32},  {0xFF00,  32},
205
 {0xFF00,  32},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
206
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
207
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},
208
 {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x01FE,  64},  {0x817E,  64},
209
 {0x817E,  64},  {0xC13E,  64},  {0xC13E,  64},  {0xE11E,  64},  {0xE11E,  64},
210
 {0xF10E,  64},  {0xF10E,  64},  {0xF906,  64},  {0xF906,  64},  {0xFD02,  64},
211
 {0xFD02,  64},  {0xFF00,  64},  {0xFF00,  64},  {0x01FE, 128}
212
};
213
 
214
/* table of attenuation values for vertical scaling */
215
u16 v_attenuation[] = { 2, 4, 8, 16, 32, 64, 128, 256, 0};
216
 
217
/* calculate vertical scale registers */
218
static int calculate_v_scale_registers(struct saa7146_dev *dev, enum v4l2_field field,
219
        int in_y, int out_y, u32* hps_v_scale, u32* hps_v_gain)
220
{
221
        int lpi = 0;
222
 
223
        /* vertical scaling */
224
        u32 yacm = 0, ysci = 0, yacl = 0, ypo = 0, ype = 0;
225
        /* vertical scale & gain */
226
        u32 dcgy = 0, cya_cyb = 0;
227
 
228
        /* helper variables */
229
        u32 v_atten = 0, i = 0;
230
 
231
        /* error, if vertical zooming */
232
        if ( in_y < out_y ) {
233
                return -EINVAL;
234
        }
235
 
236
        /* linear phase interpolation may be used
237
           if scaling is between 1 and 1/2 (both fields used)
238
           or scaling is between 1/2 and 1/4 (if only one field is used) */
239
 
240
        if (V4L2_FIELD_HAS_BOTH(field)) {
241
                if( 2*out_y >= in_y) {
242
                        lpi = 1;
243
                }
244
        } else if (field == V4L2_FIELD_TOP
245
                || field == V4L2_FIELD_ALTERNATE
246
                || field == V4L2_FIELD_BOTTOM) {
247
                if( 4*out_y >= in_y ) {
248
                        lpi = 1;
249
                }
250
                out_y *= 2;
251
        }
252
        if( 0 != lpi ) {
253
 
254
                yacm = 0;
255
                yacl = 0;
256
                cya_cyb = 0x00ff;
257
 
258
                /* calculate scaling increment */
259
                if ( in_y > out_y )
260
                        ysci = ((1024 * in_y) / (out_y + 1)) - 1024;
261
                else
262
                        ysci = 0;
263
 
264
                dcgy = 0;
265
 
266
                /* calculate ype and ypo */
267
                ype = ysci / 16;
268
                ypo = ype + (ysci / 64);
269
 
270
        } else {
271
                yacm = 1;      
272
 
273
                /* calculate scaling increment */
274
                ysci = (((10 * 1024 * (in_y - out_y - 1)) / in_y) + 9) / 10;
275
 
276
                /* calculate ype and ypo */
277
                ypo = ype = ((ysci + 15) / 16);
278
 
279
                /* the sequence length interval (yacl) has to be set according
280
                   to the prescale value, e.g.  [n   .. 1/2) : 0
281
                                                [1/2 .. 1/3) : 1
282
                                                [1/3 .. 1/4) : 2
283
                                                ... */
284
                if ( ysci < 512) {
285
                        yacl = 0;
286
                } else {
287
                        yacl = ( ysci / (1024 - ysci) );
288
                }
289
 
290
                /* get filter coefficients for cya, cyb from table hps_v_coeff_tab */  
291
                cya_cyb = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].hps_coeff;
292
 
293
                /* get best match in the table of attenuations for vertical scaling */
294
                v_atten = hps_v_coeff_tab[ (yacl < 63 ? yacl : 63 ) ].weight_sum;
295
 
296
                for (i = 0; v_attenuation[i] != 0; i++) {
297
                        if (v_attenuation[i] >= v_atten)
298
                                break;
299
                }
300
 
301
                dcgy = i;
302
        }
303
 
304
        /* ypo and ype swapped in spec ? */
305
        *hps_v_scale    |= (yacm << 31) | (ysci << 21) | (yacl << 15) | (ypo << 8 ) | (ype << 1);
306
 
307
        *hps_v_gain     &= ~(MASK_W0|MASK_B2);
308
        *hps_v_gain     |= (dcgy << 16) | (cya_cyb << 0);
309
 
310
        return 0;
311
}
312
 
313
/* simple bubble-sort algorithm with duplicate elimination */
314
static int sort_and_eliminate(u32* values, int* count)
315
{
316
        int low = 0, high = 0, top = 0, temp = 0;
317
        int cur = 0, next = 0;
318
 
319
        /* sanity checks */
320
        if( (0 > *count) || (NULL == values) ) {
321
                return -EINVAL;
322
        }
323
 
324
        /* bubble sort the first ´count´ items of the array ´values´ */
325
        for( top = *count; top > 0; top--) {
326
                for( low = 0, high = 1; high < top; low++, high++) {
327
                        if( values[low] > values[high] ) {
328
                                temp = values[low];
329
                                values[low] = values[high];
330
                                values[high] = temp;
331
                        }
332
                }
333
        }
334
 
335
        /* remove duplicate items */
336
        for( cur = 0, next = 1; next < *count; next++) {
337
                if( values[cur] != values[next])
338
                        values[++cur] = values[next];
339
        }
340
 
341
        *count = cur + 1;
342
 
343
        return 0;
344
}
345
 
346
static void calculate_clipping_registers_rect(struct saa7146_dev *dev, struct saa7146_fh *fh,
347
        struct saa7146_video_dma *vdma2, u32* clip_format, u32* arbtr_ctrl, enum v4l2_field field)
348
{
349
        struct saa7146_vv *vv = dev->vv_data;
350
        u32 *clipping = vv->d_clipping.cpu_addr;
351
 
352
        int width = fh->ov.win.w.width;
353
        int height =  fh->ov.win.w.height;
354
        int clipcount = fh->ov.nclips;
355
 
356
        u32 line_list[32];                     
357
        u32 pixel_list[32];
358
        int numdwords = 0;
359
 
360
        int i = 0, j = 0;
361
        int cnt_line = 0, cnt_pixel = 0;
362
 
363
        int x[32], y[32], w[32], h[32];
364
 
365
        /* clear out memory */
366
        memset(&line_list[0],  0x00, sizeof(u32)*32);
367
        memset(&pixel_list[0], 0x00, sizeof(u32)*32);
368
        memset(clipping,  0x00, SAA7146_CLIPPING_MEM);
369
 
370
        /* fill the line and pixel-lists */
371
        for(i = 0; i < clipcount; i++) {
372
                int l = 0, r = 0, t = 0, b = 0;
373
 
374
                x[i] = fh->ov.clips[i].c.left;
375
                y[i] = fh->ov.clips[i].c.top;
376
                w[i] = fh->ov.clips[i].c.width;
377
                h[i] = fh->ov.clips[i].c.height;
378
 
379
                if( w[i] < 0) {
380
                        x[i] += w[i]; w[i] = -w[i];
381
                }
382
                if( h[i] < 0) {
383
                        y[i] += h[i]; h[i] = -h[i];
384
                }
385
                if( x[i] < 0) {
386
                        w[i] += x[i]; x[i] = 0;
387
                }
388
                if( y[i] < 0) {
389
                        h[i] += y[i]; y[i] = 0;
390
                }      
391
                if( 0 != vv->vflip ) {
392
                        y[i] = height - y[i] - h[i];
393
                }
394
 
395
                l = x[i];
396
                r = x[i]+w[i];
397
                t = y[i];
398
                b = y[i]+h[i];
399
 
400
                /* insert left/right coordinates */
401
                pixel_list[ 2*i   ] = my_min(int, l, width);
402
                pixel_list[(2*i)+1] = my_min(int, r, width);
403
                /* insert top/bottom coordinates */
404
                line_list[ 2*i   ] = my_min(int, t, height);
405
                line_list[(2*i)+1] = my_min(int, b, height);
406
        }
407
 
408
        /* sort and eliminate lists */
409
        cnt_line = cnt_pixel = 2*clipcount;
410
        sort_and_eliminate( &pixel_list[0], &cnt_pixel );
411
        sort_and_eliminate( &line_list[0], &cnt_line );
412
 
413
        /* calculate the number of used u32s */
414
        numdwords = my_max(int, (cnt_line+1), (cnt_pixel+1))*2;
415
        numdwords = my_max(int, 4, numdwords);
416
        numdwords = my_min(int, 64, numdwords);
417
 
418
        /* fill up cliptable */
419
        for(i = 0; i < cnt_pixel; i++) {
420
                clipping[2*i] |= (pixel_list[i] << 16);
421
        }
422
        for(i = 0; i < cnt_line; i++) {
423
                clipping[(2*i)+1] |= (line_list[i] << 16);
424
        }
425
 
426
        /* fill up cliptable with the display infos */
427
        for(j = 0; j < clipcount; j++) {
428
 
429
                for(i = 0; i < cnt_pixel; i++) {
430
 
431
                        if( x[j] < 0)
432
                                x[j] = 0;
433
 
434
                        if( pixel_list[i] < (x[j] + w[j])) {
435
 
436
                                if ( pixel_list[i] >= x[j] ) {
437
                                        clipping[2*i] |= (1 << j);                     
438
                                }
439
                        }
440
                }
441
                for(i = 0; i < cnt_line; i++) {
442
 
443
                        if( y[j] < 0)
444
                                y[j] = 0;
445
 
446
                        if( line_list[i] < (y[j] + h[j]) ) {
447
 
448
                                if( line_list[i] >= y[j] ) {
449
                                        clipping[(2*i)+1] |= (1 << j);                 
450
                                }
451
                        }
452
                }
453
        }
454
 
455
        /* adjust arbitration control register */
456
        *arbtr_ctrl &= 0xffff00ff;
457
        *arbtr_ctrl |= 0x00001c00;     
458
 
459
        vdma2->base_even        = vv->d_clipping.dma_handle;
460
        vdma2->base_odd         = vv->d_clipping.dma_handle;
461
        vdma2->prot_addr        = vv->d_clipping.dma_handle+((sizeof(u32))*(numdwords));
462
        vdma2->base_page        = 0x04;
463
        vdma2->pitch            = 0x00;
464
        vdma2->num_line_byte    = (0 << 16 | (sizeof(u32))*(numdwords-1) );
465
 
466
        /* set clipping-mode. this depends on the field(s) used */
467
        *clip_format &= 0xfffffff7;
468
        if (V4L2_FIELD_HAS_BOTH(field)) {
469
                *clip_format |= 0x00000008;
470
        } else {
471
                *clip_format |= 0x00000000;
472
        }
473
}
474
 
475
/* disable clipping */
476
static void saa7146_disable_clipping(struct saa7146_dev *dev)
477
{
478
        u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
479
 
480
        /* mask out relevant bits (=lower word)*/
481
        clip_format &= MASK_W1;
482
 
483
        /* upload clipping-registers*/
484
        saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
485
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
486
 
487
        /* disable video dma2 */
488
        saa7146_write(dev, MC1, MASK_21);
489
}
490
 
491
static void saa7146_set_clipping_rect(struct saa7146_fh *fh)
492
{
493
        struct saa7146_dev *dev = fh->dev;
494
        enum v4l2_field field = fh->ov.win.field;
495
        struct  saa7146_video_dma vdma2;
496
        u32 clip_format;
497
        u32 arbtr_ctrl;
498
 
499
        /* check clipcount, disable clipping if clipcount == 0*/
500
        if( fh->ov.nclips == 0 ) {
501
                saa7146_disable_clipping(dev);
502
                return;
503
        }
504
 
505
        clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
506
        arbtr_ctrl = saa7146_read(dev, PCI_BT_V1);
507
 
508
        calculate_clipping_registers_rect(dev, fh, &vdma2, &clip_format, &arbtr_ctrl, field);
509
 
510
        /* set clipping format */
511
        clip_format &= 0xffff0008;
512
        clip_format |= (SAA7146_CLIPPING_RECT << 4);
513
 
514
        /* prepare video dma2 */
515
        saa7146_write(dev, BASE_EVEN2,          vdma2.base_even);
516
        saa7146_write(dev, BASE_ODD2,           vdma2.base_odd);
517
        saa7146_write(dev, PROT_ADDR2,          vdma2.prot_addr);
518
        saa7146_write(dev, BASE_PAGE2,          vdma2.base_page);
519
        saa7146_write(dev, PITCH2,              vdma2.pitch);
520
        saa7146_write(dev, NUM_LINE_BYTE2,      vdma2.num_line_byte);
521
 
522
        /* prepare the rest */
523
        saa7146_write(dev, CLIP_FORMAT_CTRL,clip_format);
524
        saa7146_write(dev, PCI_BT_V1, arbtr_ctrl);     
525
 
526
        /* upload clip_control-register, clipping-registers, enable video dma2 */
527
        saa7146_write(dev, MC2, (MASK_05 | MASK_21 | MASK_03 | MASK_19));
528
        saa7146_write(dev, MC1, (MASK_05 | MASK_21));
529
}
530
 
531
static void saa7146_set_window(struct saa7146_dev *dev, int width, int height, enum v4l2_field field)
532
{
533
        struct saa7146_vv *vv = dev->vv_data;
534
 
535
        int source = vv->current_hps_source;
536
        int sync = vv->current_hps_sync;
537
 
538
        u32 hps_v_scale = 0, hps_v_gain  = 0, hps_ctrl = 0, hps_h_prescale = 0, hps_h_scale = 0;
539
 
540
        /* set vertical scale */
541
        hps_v_scale = 0; /* all bits get set by the function-call */
542
        hps_v_gain  = 0; /* fixme: saa7146_read(dev, HPS_V_GAIN);*/
543
        calculate_v_scale_registers(dev, field, vv->standard->v_calc, height, &hps_v_scale, &hps_v_gain);
544
 
545
        /* set horizontal scale */
546
        hps_ctrl        = 0;
547
        hps_h_prescale  = 0; /* all bits get set in the function */
548
        hps_h_scale     = 0;
549
        calculate_h_scale_registers(dev, vv->standard->h_calc, width, vv->hflip, &hps_ctrl, &hps_v_gain, &hps_h_prescale, &hps_h_scale);
550
 
551
        /* set hyo and hxo */
552
        calculate_hxo_and_hyo(vv, &hps_h_scale, &hps_ctrl);
553
        calculate_hps_source_and_sync(dev, source, sync, &hps_ctrl);
554
 
555
        /* write out new register contents */
556
        saa7146_write(dev, HPS_V_SCALE, hps_v_scale);
557
        saa7146_write(dev, HPS_V_GAIN,  hps_v_gain);
558
        saa7146_write(dev, HPS_CTRL,    hps_ctrl);
559
        saa7146_write(dev, HPS_H_PRESCALE,hps_h_prescale);
560
        saa7146_write(dev, HPS_H_SCALE, hps_h_scale);
561
 
562
        /* upload shadow-ram registers */
563
        saa7146_write(dev, MC2, (MASK_05 | MASK_06 | MASK_21 | MASK_22) );
564
}
565
 
566
/* calculate the new memory offsets for a desired position */
567
static void saa7146_set_position(struct saa7146_dev *dev, int w_x, int w_y, int w_height, enum v4l2_field field)
568
{      
569
        struct saa7146_vv *vv = dev->vv_data;
570
 
571
        int b_depth = vv->ov_fmt->depth;
572
        int b_bpl = vv->ov_fb.fmt.bytesperline;
573
        u32 base = (u32)vv->ov_fb.base;
574
 
575
        struct  saa7146_video_dma vdma1;
576
 
577
        /* calculate memory offsets for picture, look if we shall top-down-flip */
578
        vdma1.pitch     = 2*b_bpl;
579
        if ( 0 == vv->vflip ) {
580
                vdma1.base_even = (u32)base + (w_y * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
581
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch / 2);
582
                vdma1.prot_addr = vdma1.base_even + (w_height * (vdma1.pitch / 2));
583
        }
584
        else {
585
                vdma1.base_even = (u32)base + ((w_y+w_height) * (vdma1.pitch/2)) + (w_x * (b_depth / 8));
586
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch / 2);
587
                vdma1.prot_addr = vdma1.base_odd - (w_height * (vdma1.pitch / 2));
588
        }
589
 
590
        if (V4L2_FIELD_HAS_BOTH(field)) {
591
        } else if (field == V4L2_FIELD_ALTERNATE) {
592
                /* fixme */
593
                vdma1.base_odd = vdma1.prot_addr;
594
                vdma1.pitch /= 2;
595
        } else if (field == V4L2_FIELD_TOP) {
596
                vdma1.base_odd = vdma1.prot_addr;
597
                vdma1.pitch /= 2;
598
        } else if (field == V4L2_FIELD_BOTTOM) {
599
                vdma1.base_odd = vdma1.base_even;
600
                vdma1.base_even = vdma1.prot_addr;
601
                vdma1.pitch /= 2;
602
        }
603
 
604
        if ( 0 != vv->vflip ) {
605
                vdma1.pitch *= -1;
606
        }
607
 
608
        vdma1.base_page = 0;
609
        vdma1.num_line_byte = (vv->standard->v_field<<16)+vv->standard->h_pixels;
610
 
611
        saa7146_write_out_dma(dev, 1, &vdma1);
612
}
613
 
614
static void saa7146_set_output_format(struct saa7146_dev *dev, unsigned long palette)
615
{
616
        u32 clip_format = saa7146_read(dev, CLIP_FORMAT_CTRL);
617
 
618
        /* call helper function */
619
        calculate_output_format_register(dev,palette,&clip_format);
620
 
621
        /* update the hps registers */
622
        saa7146_write(dev, CLIP_FORMAT_CTRL, clip_format);
623
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
624
}
625
 
626
void saa7146_set_picture_prop(struct saa7146_dev *dev, int brightness, int contrast, int colour)
627
{
628
        u32 bcs_ctrl = 0;
629
 
630
        calculate_bcs_ctrl_register(dev, brightness, contrast, colour, &bcs_ctrl);
631
        saa7146_write(dev, BCS_CTRL, bcs_ctrl);
632
 
633
        /* update the bcs register */
634
        saa7146_write(dev, MC2, (MASK_06 | MASK_22));
635
}
636
 
637
 
638
/* select input-source */
639
void saa7146_set_hps_source_and_sync(struct saa7146_dev *dev, int source, int sync)
640
{
641
        struct saa7146_vv *vv = dev->vv_data;
642
        u32 hps_ctrl = 0;
643
 
644
        /* read old state */
645
        hps_ctrl = saa7146_read(dev, HPS_CTRL);
646
 
647
        hps_ctrl &= ~( MASK_31 | MASK_30 | MASK_28 );
648
        hps_ctrl |= (source << 30) | (sync << 28);
649
 
650
        /* write back & upload register */
651
        saa7146_write(dev, HPS_CTRL, hps_ctrl);
652
        saa7146_write(dev, MC2, (MASK_05 | MASK_21));
653
 
654
        vv->current_hps_source = source;
655
        vv->current_hps_sync = sync;
656
}
657
 
658
int saa7146_enable_overlay(struct saa7146_fh *fh)
659
{
660
        struct saa7146_dev *dev = fh->dev;
661
        struct saa7146_vv *vv = dev->vv_data;
662
 
663
        saa7146_set_window(dev, fh->ov.win.w.width, fh->ov.win.w.height, fh->ov.win.field);
664
        saa7146_set_position(dev, fh->ov.win.w.left, fh->ov.win.w.top, fh->ov.win.w.height, fh->ov.win.field);
665
        saa7146_set_output_format(dev, vv->ov_fmt->trans);
666
        saa7146_set_clipping_rect(fh);
667
 
668
        /* enable video dma1 */
669
        saa7146_write(dev, MC1, (MASK_06 | MASK_22));
670
        return 0;
671
}              
672
 
673
void saa7146_disable_overlay(struct saa7146_fh *fh)
674
{
675
        struct saa7146_dev *dev = fh->dev;
676
 
677
        /* disable clipping + video dma1 */
678
        saa7146_disable_clipping(dev);
679
        saa7146_write(dev, MC1, MASK_22);
680
}              
681
 
682
void saa7146_write_out_dma(struct saa7146_dev* dev, int which, struct saa7146_video_dma* vdma)
683
{
684
        int where = 0;
685
 
686
        if( which < 1 || which > 3) {
687
                return;
688
        }
689
 
690
        /* calculate starting address */
691
        where  = (which-1)*0x18;
692
 
693
        saa7146_write(dev, where,       vdma->base_odd);
694
        saa7146_write(dev, where+0x04,  vdma->base_even);
695
        saa7146_write(dev, where+0x08,  vdma->prot_addr);
696
        saa7146_write(dev, where+0x0c,  vdma->pitch);
697
        saa7146_write(dev, where+0x10,  vdma->base_page);
698
        saa7146_write(dev, where+0x14,  vdma->num_line_byte);
699
 
700
        /* upload */
701
        saa7146_write(dev, MC2, (MASK_02<<(which-1))|(MASK_18<<(which-1)));            
702
/*             
703
        printk("vdma%d.base_even:     0x%08x\n", which,vdma->base_even);
704
        printk("vdma%d.base_odd:      0x%08x\n", which,vdma->base_odd);
705
        printk("vdma%d.prot_addr:     0x%08x\n", which,vdma->prot_addr);
706
        printk("vdma%d.base_page:     0x%08x\n", which,vdma->base_page);
707
        printk("vdma%d.pitch:         0x%08x\n", which,vdma->pitch);
708
        printk("vdma%d.num_line_byte: 0x%08x\n", which,vdma->num_line_byte);
709
*/
710
}
711
 
712
static int calculate_video_dma_grab_packed(struct saa7146_dev* dev, struct saa7146_buf *buf)
713
{
714
        struct saa7146_vv *vv = dev->vv_data;
715
        struct saa7146_video_dma vdma1;
716
 
717
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
718
 
719
        int width = buf->fmt->width;
720
        int height = buf->fmt->height;
721
        int bytesperline = buf->fmt->bytesperline;
722
        enum v4l2_field field = buf->fmt->field;
723
 
724
        int depth = sfmt->depth;
725
 
726
        DEB_CAP(("[size=%dx%d,fields=%s]\n",
727
                width,height,v4l2_field_names[field]));
728
 
729
        if( bytesperline != 0) {
730
                vdma1.pitch = bytesperline*2;
731
        } else {
732
                vdma1.pitch = (width*depth*2)/8;
733
        }
734
        vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
735
        vdma1.base_page         = buf->pt[0].dma | ME1;
736
 
737
        if( 0 != vv->vflip ) {
738
                vdma1.prot_addr = buf->pt[0].offset;
739
                vdma1.base_even = buf->pt[0].offset+(vdma1.pitch/2)*height;
740
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
741
        } else {
742
                vdma1.base_even = buf->pt[0].offset;
743
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
744
                vdma1.prot_addr = buf->pt[0].offset+(vdma1.pitch/2)*height;
745
        }
746
 
747
        if (V4L2_FIELD_HAS_BOTH(field)) {
748
        } else if (field == V4L2_FIELD_ALTERNATE) {
749
                /* fixme */
750
                if ( vv->last_field == V4L2_FIELD_TOP ) {
751
                        vdma1.base_odd  = vdma1.prot_addr;
752
                        vdma1.pitch /= 2;
753
                } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
754
                        vdma1.base_odd  = vdma1.base_even;
755
                        vdma1.base_even = vdma1.prot_addr;
756
                        vdma1.pitch /= 2;
757
                }
758
        } else if (field == V4L2_FIELD_TOP) {
759
                vdma1.base_odd  = vdma1.prot_addr;
760
                vdma1.pitch /= 2;
761
        } else if (field == V4L2_FIELD_BOTTOM) {
762
                vdma1.base_odd  = vdma1.base_even;
763
                vdma1.base_even = vdma1.prot_addr;
764
                vdma1.pitch /= 2;
765
        }
766
 
767
        if( 0 != vv->vflip ) {
768
                vdma1.pitch *= -1;
769
        }      
770
 
771
        saa7146_write_out_dma(dev, 1, &vdma1);
772
        return 0;
773
}
774
 
775
static int calc_planar_422(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
776
{
777
        int height = buf->fmt->height;
778
        int width = buf->fmt->width;
779
 
780
        vdma2->pitch    = width;
781
        vdma3->pitch    = width;
782
 
783
        /* fixme: look at bytesperline! */
784
 
785
        if( 0 != vv->vflip ) {
786
                vdma2->prot_addr        = buf->pt[1].offset;
787
                vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[1].offset;
788
                vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
789
 
790
                vdma3->prot_addr        = buf->pt[2].offset;
791
                vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[2].offset;
792
                vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
793
        } else {
794
                vdma3->base_even        = buf->pt[2].offset;
795
                vdma3->base_odd         = vdma3->base_even + (vdma3->pitch/2);
796
                vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
797
 
798
                vdma2->base_even        = buf->pt[1].offset;
799
                vdma2->base_odd         = vdma2->base_even + (vdma2->pitch/2);
800
                vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
801
        }
802
 
803
        return 0;
804
}
805
 
806
static int calc_planar_420(struct saa7146_vv *vv, struct saa7146_buf *buf, struct saa7146_video_dma *vdma2, struct saa7146_video_dma *vdma3)
807
{
808
        int height = buf->fmt->height;
809
        int width = buf->fmt->width;
810
 
811
        vdma2->pitch    = width/2;
812
        vdma3->pitch    = width/2;
813
 
814
        if( 0 != vv->vflip ) {
815
                vdma2->prot_addr        = buf->pt[2].offset;
816
                vdma2->base_even        = ((vdma2->pitch/2)*height)+buf->pt[2].offset;
817
                vdma2->base_odd         = vdma2->base_even - (vdma2->pitch/2);
818
 
819
                vdma3->prot_addr        = buf->pt[1].offset;
820
                vdma3->base_even        = ((vdma3->pitch/2)*height)+buf->pt[1].offset;
821
                vdma3->base_odd         = vdma3->base_even - (vdma3->pitch/2);
822
 
823
        } else {
824
                vdma3->base_even        = buf->pt[2].offset;
825
                vdma3->base_odd         = vdma3->base_even + (vdma3->pitch);
826
                vdma3->prot_addr        = (vdma3->pitch/2)*height+buf->pt[2].offset;
827
 
828
                vdma2->base_even        = buf->pt[1].offset;
829
                vdma2->base_odd         = vdma2->base_even + (vdma2->pitch);
830
                vdma2->prot_addr        = (vdma2->pitch/2)*height+buf->pt[1].offset;
831
        }
832
        return 0;
833
}
834
 
835
 
836
static int calculate_video_dma_grab_planar(struct saa7146_dev* dev, struct saa7146_buf *buf)
837
{
838
        struct saa7146_vv *vv = dev->vv_data;
839
        struct saa7146_video_dma vdma1;
840
        struct saa7146_video_dma vdma2;
841
        struct saa7146_video_dma vdma3;
842
 
843
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
844
 
845
        int width = buf->fmt->width;
846
        int height = buf->fmt->height;
847
        enum v4l2_field field = buf->fmt->field;
848
 
849
        BUG_ON(0 == buf->pt[0].dma);
850
        BUG_ON(0 == buf->pt[1].dma);
851
        BUG_ON(0 == buf->pt[2].dma);
852
 
853
        DEB_CAP(("[size=%dx%d,fields=%s]\n",
854
                width,height,v4l2_field_names[field]));
855
 
856
        /* fixme: look at bytesperline! */
857
 
858
        /* fixme: what happens for user space buffers here?. The offsets are
859
           most likely wrong, this version here only works for page-aligned
860
           buffers, modifications to the pagetable-functions are necessary...*/
861
 
862
        vdma1.pitch             = width*2;
863
        vdma1.num_line_byte     = ((vv->standard->v_field<<16) + vv->standard->h_pixels);
864
        vdma1.base_page         = buf->pt[0].dma | ME1;
865
 
866
        if( 0 != vv->vflip ) {
867
                vdma1.prot_addr = buf->pt[0].offset;
868
                vdma1.base_even = ((vdma1.pitch/2)*height)+buf->pt[0].offset;
869
                vdma1.base_odd  = vdma1.base_even - (vdma1.pitch/2);
870
        } else {
871
                vdma1.base_even = buf->pt[0].offset;
872
                vdma1.base_odd  = vdma1.base_even + (vdma1.pitch/2);
873
                vdma1.prot_addr = (vdma1.pitch/2)*height+buf->pt[0].offset;
874
        }
875
 
876
        vdma2.num_line_byte     = 0; /* unused */
877
        vdma2.base_page         = buf->pt[1].dma | ME1;
878
 
879
        vdma3.num_line_byte     = 0; /* unused */
880
        vdma3.base_page         = buf->pt[2].dma | ME1;
881
 
882
        switch( sfmt->depth ) {
883
                case 12: {
884
                        calc_planar_420(vv,buf,&vdma2,&vdma3);
885
                        break;
886
                }
887
                case 16: {
888
                        calc_planar_422(vv,buf,&vdma2,&vdma3);
889
                        break;
890
                }
891
                default: {
892
                        return -1;
893
                }
894
        }
895
 
896
        if (V4L2_FIELD_HAS_BOTH(field)) {
897
        } else if (field == V4L2_FIELD_ALTERNATE) {
898
                /* fixme */
899
                vdma1.base_odd  = vdma1.prot_addr;
900
                vdma1.pitch /= 2;
901
                vdma2.base_odd  = vdma2.prot_addr;
902
                vdma2.pitch /= 2;
903
                vdma3.base_odd  = vdma3.prot_addr;
904
                vdma3.pitch /= 2;
905
        } else if (field == V4L2_FIELD_TOP) {
906
                vdma1.base_odd  = vdma1.prot_addr;
907
                vdma1.pitch /= 2;
908
                vdma2.base_odd  = vdma2.prot_addr;
909
                vdma2.pitch /= 2;
910
                vdma3.base_odd  = vdma3.prot_addr;
911
                vdma3.pitch /= 2;
912
        } else if (field == V4L2_FIELD_BOTTOM) {
913
                vdma1.base_odd  = vdma1.base_even;
914
                vdma1.base_even = vdma1.prot_addr;
915
                vdma1.pitch /= 2;
916
                vdma2.base_odd  = vdma2.base_even;
917
                vdma2.base_even = vdma2.prot_addr;
918
                vdma2.pitch /= 2;
919
                vdma3.base_odd  = vdma3.base_even;
920
                vdma3.base_even = vdma3.prot_addr;
921
                vdma3.pitch /= 2;
922
        }
923
 
924
        if( 0 != vv->vflip ) {
925
                vdma1.pitch *= -1;
926
                vdma2.pitch *= -1;
927
                vdma3.pitch *= -1;
928
        }      
929
 
930
        saa7146_write_out_dma(dev, 1, &vdma1);
931
        if( (sfmt->flags & FORMAT_BYTE_SWAP) != 0 ) {
932
                saa7146_write_out_dma(dev, 3, &vdma2);
933
                saa7146_write_out_dma(dev, 2, &vdma3);
934
        } else {
935
                saa7146_write_out_dma(dev, 2, &vdma2);
936
                saa7146_write_out_dma(dev, 3, &vdma3);
937
        }
938
        return 0;
939
}
940
 
941
static void program_capture_engine(struct saa7146_dev *dev, int planar)
942
{
943
        struct saa7146_vv *vv = dev->vv_data;
944
        int count = 0;
945
 
946
        unsigned long e_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_E_FID_A : CMD_E_FID_B;
947
        unsigned long o_wait = vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? CMD_O_FID_A : CMD_O_FID_B;
948
 
949
        /* wait for o_fid_a/b / e_fid_a/b toggle only if rps register 0 is not set*/
950
        WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | o_wait);
951
        WRITE_RPS0(CMD_PAUSE | CMD_OAN | CMD_SIG0 | e_wait);
952
 
953
        /* set rps register 0 */
954
        WRITE_RPS0(CMD_WR_REG | (1 << 8) | (MC2/4));    
955
        WRITE_RPS0(MASK_27 | MASK_11);
956
 
957
        /* turn on video-dma1 */
958
        WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
959
        WRITE_RPS0(MASK_06 | MASK_22);                  /* => mask */
960
        WRITE_RPS0(MASK_06 | MASK_22);                  /* => values */
961
        if( 0 != planar ) {
962
                /* turn on video-dma2 */
963
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
964
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
965
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => values */
966
 
967
                /* turn on video-dma3 */
968
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
969
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
970
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => values */
971
        }
972
 
973
        /* wait for o_fid_a/b / e_fid_a/b toggle */
974
        if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
975
                WRITE_RPS0(CMD_PAUSE | o_wait);
976
                WRITE_RPS0(CMD_PAUSE | e_wait);
977
        } else if ( vv->last_field == V4L2_FIELD_TOP ) {
978
                WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
979
                WRITE_RPS0(CMD_PAUSE | o_wait);
980
        } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
981
                WRITE_RPS0(CMD_PAUSE | (vv->current_hps_sync == SAA7146_HPS_SYNC_PORT_A ? MASK_10 : MASK_09));
982
                WRITE_RPS0(CMD_PAUSE | e_wait);
983
        }
984
 
985
        /* turn off video-dma1 */
986
        WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));
987
        WRITE_RPS0(MASK_22 | MASK_06);                  /* => mask */
988
        WRITE_RPS0(MASK_22);                                    /* => values */
989
        if( 0 != planar ) {
990
                /* turn off video-dma2 */
991
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
992
                WRITE_RPS0(MASK_05 | MASK_21);                  /* => mask */
993
                WRITE_RPS0(MASK_21);                                    /* => values */
994
 
995
                /* turn off video-dma3 */
996
                WRITE_RPS0(CMD_WR_REG_MASK | (MC1/4));         
997
                WRITE_RPS0(MASK_04 | MASK_20);                  /* => mask */
998
                WRITE_RPS0(MASK_20);                                    /* => values */
999
        }
1000
 
1001
        /* generate interrupt */
1002
        WRITE_RPS0(CMD_INTERRUPT);                                     
1003
 
1004
        /* stop */
1005
        WRITE_RPS0(CMD_STOP);                                  
1006
}
1007
 
1008
void saa7146_set_capture(struct saa7146_dev *dev, struct saa7146_buf *buf, struct saa7146_buf *next)
1009
{
1010
        struct saa7146_format *sfmt = format_by_fourcc(dev,buf->fmt->pixelformat);
1011
        struct saa7146_vv *vv = dev->vv_data;
1012
        u32 vdma1_prot_addr;
1013
 
1014
        DEB_CAP(("buf:%p, next:%p\n",buf,next));
1015
 
1016
        vdma1_prot_addr = saa7146_read(dev, PROT_ADDR1);
1017
        if( 0 == vdma1_prot_addr ) {
1018
                /* clear out beginning of streaming bit (rps register 0)*/
1019
                DEB_CAP(("forcing sync to new frame\n"));
1020
                saa7146_write(dev, MC2, MASK_27 );
1021
        }
1022
 
1023
        saa7146_set_window(dev, buf->fmt->width, buf->fmt->height, buf->fmt->field);
1024
        saa7146_set_output_format(dev, sfmt->trans);
1025
 
1026
        if ( vv->last_field == V4L2_FIELD_INTERLACED ) {
1027
        } else if ( vv->last_field == V4L2_FIELD_TOP ) {
1028
                vv->last_field = V4L2_FIELD_BOTTOM;
1029
        } else if ( vv->last_field == V4L2_FIELD_BOTTOM ) {
1030
                vv->last_field = V4L2_FIELD_TOP;
1031
        }
1032
 
1033
        if( 0 != IS_PLANAR(sfmt->trans)) {
1034
                calculate_video_dma_grab_planar(dev, buf);
1035
                program_capture_engine(dev,1);
1036
        } else {
1037
                calculate_video_dma_grab_packed(dev, buf);
1038
                program_capture_engine(dev,0);
1039
        }
1040
 
1041
/*
1042
        printk("vdma%d.base_even:     0x%08x\n", 1,saa7146_read(dev,BASE_EVEN1));
1043
        printk("vdma%d.base_odd:      0x%08x\n", 1,saa7146_read(dev,BASE_ODD1));
1044
        printk("vdma%d.prot_addr:     0x%08x\n", 1,saa7146_read(dev,PROT_ADDR1));
1045
        printk("vdma%d.base_page:     0x%08x\n", 1,saa7146_read(dev,BASE_PAGE1));
1046
        printk("vdma%d.pitch:         0x%08x\n", 1,saa7146_read(dev,PITCH1));
1047
        printk("vdma%d.num_line_byte: 0x%08x\n", 1,saa7146_read(dev,NUM_LINE_BYTE1));
1048
        printk("vdma%d => vptr      : 0x%08x\n", 1,saa7146_read(dev,PCI_VDP1));
1049
*/
1050
 
1051
        /* write the address of the rps-program */
1052
        saa7146_write(dev, RPS_ADDR0, dev->d_rps0.dma_handle);
1053
 
1054
        /* turn on rps */
1055
        saa7146_write(dev, MC1, (MASK_12 | MASK_28));  
1056
}
1057