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Rev | Author | Line No. | Line |
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582 | mauro | 1 | #include <linuxcomp.h> |
2 | |||
3 | #include <linux/init.h> |
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4 | #include <linux/bitops.h> |
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5 | #include <linux/mm.h> |
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6 | #include <asm/io.h> |
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7 | #include <asm/processor.h> |
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8 | |||
9 | #include "cpu.h" |
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10 | |||
11 | /* |
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12 | * B step AMD K6 before B 9730xxxx have hardware bugs that can cause |
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13 | * misexecution of code under Linux. Owners of such processors should |
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14 | * contact AMD for precise details and a CPU swap. |
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15 | * |
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16 | * See http://www.multimania.com/poulot/k6bug.html |
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17 | * http://www.amd.com/K6/k6docs/revgd.html |
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18 | * |
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19 | * The following test is erm.. interesting. AMD neglected to up |
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20 | * the chip setting when fixing the bug but they also tweaked some |
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21 | * performance at the same time.. |
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22 | */ |
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23 | |||
24 | extern void vide(void); |
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25 | __asm__(".align 4\nvide: ret"); |
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26 | |||
27 | static void __init init_amd(struct cpuinfo_x86 *c) |
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28 | { |
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29 | u32 l, h; |
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30 | int mbytes = 1; //!!!num_physpages >> (20-PAGE_SHIFT); |
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31 | int r; |
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32 | |||
33 | /* |
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34 | * FIXME: We should handle the K5 here. Set up the write |
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35 | * range and also turn on MSR 83 bits 4 and 31 (write alloc, |
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36 | * no bus pipeline) |
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37 | */ |
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38 | |||
39 | /* Bit 31 in normal CPUID used for nonstandard 3DNow ID; |
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40 | 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway */ |
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41 | clear_bit(0*32+31, c->x86_capability); |
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42 | |||
43 | r = get_model_name(c); |
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44 | |||
45 | switch(c->x86) |
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46 | { |
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47 | case 4: |
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48 | /* |
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49 | * General Systems BIOSen alias the cpu frequency registers |
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50 | * of the Elan at 0x000df000. Unfortuantly, one of the Linux |
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51 | * drivers subsequently pokes it, and changes the CPU speed. |
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52 | * Workaround : Remove the unneeded alias. |
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53 | */ |
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54 | #define CBAR (0xfffc) /* Configuration Base Address (32-bit) */ |
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55 | #define CBAR_ENB (0x80000000) |
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56 | #define CBAR_KEY (0X000000CB) |
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57 | if (c->x86_model==9 || c->x86_model == 10) { |
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58 | if (inl (CBAR) & CBAR_ENB) |
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59 | outl (0 | CBAR_KEY, CBAR); |
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60 | } |
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61 | break; |
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62 | case 5: |
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63 | if( c->x86_model < 6 ) |
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64 | { |
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65 | /* Based on AMD doc 20734R - June 2000 */ |
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66 | if ( c->x86_model == 0 ) { |
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67 | clear_bit(X86_FEATURE_APIC, c->x86_capability); |
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68 | set_bit(X86_FEATURE_PGE, c->x86_capability); |
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69 | } |
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70 | break; |
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71 | } |
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72 | |||
73 | if ( c->x86_model == 6 && c->x86_mask == 1 ) { |
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74 | const int K6_BUG_LOOP = 1000000; |
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75 | int n; |
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76 | void (*f_vide)(void); |
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77 | unsigned long d, d2; |
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78 | |||
79 | printk(KERN_INFO "AMD K6 stepping B detected - "); |
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80 | |||
81 | /* |
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82 | * It looks like AMD fixed the 2.6.2 bug and improved indirect |
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83 | * calls at the same time. |
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84 | */ |
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85 | |||
86 | n = K6_BUG_LOOP; |
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87 | f_vide = vide; |
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88 | rdtscl(d); |
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89 | while (n--) |
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90 | f_vide(); |
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91 | rdtscl(d2); |
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92 | d = d2-d; |
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93 | |||
94 | /* Knock these two lines out if it debugs out ok */ |
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95 | printk(KERN_INFO "AMD K6 stepping B detected - "); |
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96 | /* -- cut here -- */ |
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97 | if (d > 20*K6_BUG_LOOP) |
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98 | printk("system stability may be impaired when more than 32 MB are used.\n"); |
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99 | else |
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100 | printk("probably OK (after B9730xxxx).\n"); |
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101 | printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n"); |
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102 | } |
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103 | |||
104 | /* K6 with old style WHCR */ |
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105 | if (c->x86_model < 8 || |
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106 | (c->x86_model== 8 && c->x86_mask < 8)) { |
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107 | /* We can only write allocate on the low 508Mb */ |
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108 | if(mbytes>508) |
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109 | mbytes=508; |
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110 | |||
111 | rdmsr(MSR_K6_WHCR, l, h); |
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112 | if ((l&0x0000FFFF)==0) { |
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113 | unsigned long flags; |
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114 | l=(1<<0)|((mbytes/4)<<1); |
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115 | local_irq_save(flags); |
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116 | wbinvd(); |
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117 | wrmsr(MSR_K6_WHCR, l, h); |
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118 | local_irq_restore(flags); |
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119 | printk(KERN_INFO "Enabling old style K6 write allocation for %d Mb\n", |
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120 | mbytes); |
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121 | } |
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122 | break; |
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123 | } |
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124 | |||
125 | if ((c->x86_model == 8 && c->x86_mask >7) || |
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126 | c->x86_model == 9 || c->x86_model == 13) { |
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127 | /* The more serious chips .. */ |
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128 | |||
129 | if(mbytes>4092) |
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130 | mbytes=4092; |
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131 | |||
132 | rdmsr(MSR_K6_WHCR, l, h); |
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133 | if ((l&0xFFFF0000)==0) { |
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134 | unsigned long flags; |
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135 | l=((mbytes>>2)<<22)|(1<<16); |
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136 | local_irq_save(flags); |
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137 | wbinvd(); |
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138 | wrmsr(MSR_K6_WHCR, l, h); |
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139 | local_irq_restore(flags); |
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140 | printk(KERN_INFO "Enabling new style K6 write allocation for %d Mb\n", |
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141 | mbytes); |
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142 | } |
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143 | |||
144 | /* Set MTRR capability flag if appropriate */ |
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145 | if (c->x86_model == 13 || c->x86_model == 9 || |
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146 | (c->x86_model == 8 && c->x86_mask >= 8)) |
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147 | set_bit(X86_FEATURE_K6_MTRR, c->x86_capability); |
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148 | break; |
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149 | } |
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150 | break; |
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151 | |||
152 | case 6: /* An Athlon/Duron */ |
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153 | |||
154 | /* Bit 15 of Athlon specific MSR 15, needs to be 0 |
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155 | * to enable SSE on Palomino/Morgan/Barton CPU's. |
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156 | * If the BIOS didn't enable it already, enable it here. |
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157 | */ |
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158 | if (c->x86_model >= 6 && c->x86_model <= 10) { |
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159 | if (!cpu_has(c, X86_FEATURE_XMM)) { |
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160 | printk(KERN_INFO "Enabling disabled K7/SSE Support.\n"); |
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161 | rdmsr(MSR_K7_HWCR, l, h); |
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162 | l &= ~0x00008000; |
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163 | wrmsr(MSR_K7_HWCR, l, h); |
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164 | set_bit(X86_FEATURE_XMM, c->x86_capability); |
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165 | } |
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166 | } |
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167 | |||
168 | /* It's been determined by AMD that Athlons since model 8 stepping 1 |
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169 | * are more robust with CLK_CTL set to 200xxxxx instead of 600xxxxx |
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170 | * As per AMD technical note 27212 0.2 |
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171 | */ |
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172 | if ((c->x86_model == 8 && c->x86_mask>=1) || (c->x86_model > 8)) { |
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173 | rdmsr(MSR_K7_CLK_CTL, l, h); |
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174 | if ((l & 0xfff00000) != 0x20000000) { |
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175 | printk ("CPU: CLK_CTL MSR was %x. Reprogramming to %x\n", l, |
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176 | ((l & 0x000fffff)|0x20000000)); |
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177 | wrmsr(MSR_K7_CLK_CTL, (l & 0x000fffff)|0x20000000, h); |
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178 | } |
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179 | } |
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180 | break; |
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181 | } |
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182 | |||
183 | switch (c->x86) { |
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184 | case 15: |
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185 | set_bit(X86_FEATURE_K8, c->x86_capability); |
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186 | break; |
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187 | case 6: |
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188 | set_bit(X86_FEATURE_K7, c->x86_capability); |
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189 | break; |
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190 | } |
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191 | |||
192 | display_cacheinfo(c); |
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193 | } |
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194 | |||
195 | static unsigned int amd_size_cache(struct cpuinfo_x86 * c, unsigned int size) |
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196 | { |
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197 | /* AMD errata T13 (order #21922) */ |
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198 | if ((c->x86 == 6)) { |
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199 | if (c->x86_model == 3 && c->x86_mask == 0) /* Duron Rev A0 */ |
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200 | size = 64; |
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201 | if (c->x86_model == 4 && |
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202 | (c->x86_mask==0 || c->x86_mask==1)) /* Tbird rev A1/A2 */ |
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203 | size = 256; |
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204 | } |
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205 | return size; |
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206 | } |
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207 | |||
208 | static struct cpu_dev amd_cpu_dev __initdata = { |
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209 | .c_vendor = "AMD", |
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210 | .c_ident = { "AuthenticAMD" }, |
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211 | .c_models = { |
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212 | { .vendor = X86_VENDOR_AMD, .family = 4, .model_names = |
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213 | { |
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214 | [3] = "486 DX/2", |
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215 | [7] = "486 DX/2-WB", |
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216 | [8] = "486 DX/4", |
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217 | [9] = "486 DX/4-WB", |
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218 | [14] = "Am5x86-WT", |
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219 | [15] = "Am5x86-WB" |
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220 | } |
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221 | }, |
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222 | }, |
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223 | .c_init = init_amd, |
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224 | .c_identify = generic_identify, |
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225 | .c_size_cache = amd_size_cache, |
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226 | }; |
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227 | |||
228 | int __init amd_init_cpu(void) |
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229 | { |
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230 | cpu_devs[X86_VENDOR_AMD] = &amd_cpu_dev; |
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231 | return 0; |
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232 | } |
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233 | |||
234 | //early_arch_initcall(amd_init_cpu); |