WebSVN - shark - Blame - Rev 477 - /shark/trunk/drivers/fb/riva/fbdev.c

Rev	Author	Line No.	Line
472	giacomo	1	/*
		2	* linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
		3	*
		4	* Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
		5	*
		6	* Copyright 1999-2000 Jeff Garzik
		7	*
		8	* Contributors:
		9	*
		10	* Ani Joshi: Lots of debugging and cleanup work, really helped
		11	* get the driver going
		12	*
		13	* Ferenc Bakonyi: Bug fixes, cleanup, modularization
		14	*
		15	* Jindrich Makovicka: Accel code help, hw cursor, mtrr
		16	*
		17	* Paul Richards: Bug fixes, updates
		18	*
		19	* Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
		20	* Includes riva_hw.c from nVidia, see copyright below.
		21	* KGI code provided the basis for state storage, init, and mode switching.
		22	*
		23	* This file is subject to the terms and conditions of the GNU General Public
		24	* License. See the file COPYING in the main directory of this archive
		25	* for more details.
		26	*
		27	* Known bugs and issues:
		28	* restoring text mode fails
		29	* doublescan modes are broken
		30	*/
		31
		32	#include <linuxcomp.h>
		33
		34	#include <linux/config.h>
		35	#include <linux/module.h>
		36	#include <linux/kernel.h>
		37	#include <linux/errno.h>
		38	#include <linux/string.h>
		39	#include <linux/mm.h>
		40	#include <linux/tty.h>
		41	#include <linux/slab.h>
		42	#include <linux/delay.h>
		43	#include <linux/fb.h>
		44	#include <linux/init.h>
		45	#include <linux/pci.h>
		46	#ifdef CONFIG_MTRR
		47	#include <asm/mtrr.h>
		48	#endif
		49
		50	#include "rivafb.h"
		51	#include "nvreg.h"
		52
		53	#ifndef CONFIG_PCI /* sanity check */
		54	#error This driver requires PCI support.
		55	#endif
		56
		57	/* version number of this driver */
		58	#define RIVAFB_VERSION "0.9.5b"
		59
		60	/* ------------------------------------------------------------------------- *
		61	*
		62	* various helpful macros and constants
		63	*
		64	* ------------------------------------------------------------------------- */
		65
477	giacomo	66	#undef RIVAFBDEBUG
472	giacomo	67	#ifdef RIVAFBDEBUG
		68	#define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
		69	#else
		70	#define DPRINTK(fmt, args...)
		71	#endif
		72
		73	#ifndef RIVA_NDEBUG
		74	#define assert(expr) \
		75	if(!(expr)) { \
		76	printk( "Assertion failed! %s,%s,%s,line=%d\n",\
		77	#expr,__FILE__,__FUNCTION__,__LINE__); \
		78	BUG(); \
		79	}
		80	#else
		81	#define assert(expr)
		82	#endif
		83
		84	#define PFX "rivafb: "
		85
		86	/* macro that allows you to set overflow bits */
		87	#define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
		88	#define SetBit(n) (1<<(n))
		89	#define Set8Bits(value) ((value)&0xff)
		90
		91	/* HW cursor parameters */
		92	#define MAX_CURS 32
		93
		94	/* ------------------------------------------------------------------------- *
		95	*
		96	* prototypes
		97	*
		98	* ------------------------------------------------------------------------- */
		99
		100	static int rivafb_blank(int blank, struct fb_info *info);
		101
		102	/* ------------------------------------------------------------------------- *
		103	*
		104	* card identification
		105	*
		106	* ------------------------------------------------------------------------- */
		107
		108	enum riva_chips {
		109	CH_RIVA_128 = 0,
		110	CH_RIVA_TNT,
		111	CH_RIVA_TNT2,
		112	CH_RIVA_UTNT2,
		113	CH_RIVA_VTNT2,
		114	CH_RIVA_UVTNT2,
		115	CH_RIVA_ITNT2,
		116	CH_GEFORCE_SDR,
		117	CH_GEFORCE_DDR,
		118	CH_QUADRO,
		119	CH_GEFORCE2_MX,
		120	CH_GEFORCE2_MX2,
		121	CH_GEFORCE2_GO,
		122	CH_QUADRO2_MXR,
		123	CH_GEFORCE2_GTS,
		124	CH_GEFORCE2_GTS2,
		125	CH_GEFORCE2_ULTRA,
		126	CH_QUADRO2_PRO,
473	giacomo	127	CH_TEST,
472	giacomo	128	CH_GEFORCE4_MX_460,
		129	CH_GEFORCE4_MX_440,
		130	CH_GEFORCE4_MX_420,
		131	CH_GEFORCE4_440_GO,
		132	CH_GEFORCE4_420_GO,
		133	CH_GEFORCE4_420_GO_M32,
		134	CH_QUADRO4_500XGL,
		135	CH_GEFORCE4_440_GO_M64,
		136	CH_QUADRO4_200,
		137	CH_QUADRO4_550XGL,
		138	CH_QUADRO4_500_GOGL,
		139	CH_IGEFORCE2,
		140	CH_GEFORCE3,
		141	CH_GEFORCE3_1,
		142	CH_GEFORCE3_2,
		143	CH_QUADRO_DDC,
		144	CH_GEFORCE4_TI_4600,
		145	CH_GEFORCE4_TI_4400,
		146	CH_GEFORCE4_TI_4200,
		147	CH_QUADRO4_900XGL,
		148	CH_QUADRO4_750XGL,
		149	CH_QUADRO4_700XGL
		150	};
		151
		152	/* directly indexed by riva_chips enum, above */
		153	static struct riva_chip_info {
		154	const char *name;
		155	unsigned arch_rev;
		156	} riva_chip_info[] __initdata = {
		157	{ "RIVA-128", NV_ARCH_03 },
		158	{ "RIVA-TNT", NV_ARCH_04 },
		159	{ "RIVA-TNT2", NV_ARCH_04 },
		160	{ "RIVA-UTNT2", NV_ARCH_04 },
		161	{ "RIVA-VTNT2", NV_ARCH_04 },
		162	{ "RIVA-UVTNT2", NV_ARCH_04 },
		163	{ "RIVA-ITNT2", NV_ARCH_04 },
		164	{ "GeForce-SDR", NV_ARCH_10 },
		165	{ "GeForce-DDR", NV_ARCH_10 },
		166	{ "Quadro", NV_ARCH_10 },
		167	{ "GeForce2-MX", NV_ARCH_10 },
		168	{ "GeForce2-MX", NV_ARCH_10 },
		169	{ "GeForce2-GO", NV_ARCH_10 },
		170	{ "Quadro2-MXR", NV_ARCH_10 },
		171	{ "GeForce2-GTS", NV_ARCH_10 },
		172	{ "GeForce2-GTS", NV_ARCH_10 },
		173	{ "GeForce2-ULTRA", NV_ARCH_10 },
		174	{ "Quadro2-PRO", NV_ARCH_10 },
473	giacomo	175	{ "TEST",NV_ARCH_20 },
472	giacomo	176	{ "GeForce4-MX-460", NV_ARCH_20 },
		177	{ "GeForce4-MX-440", NV_ARCH_20 },
		178	{ "GeForce4-MX-420", NV_ARCH_20 },
		179	{ "GeForce4-440-GO", NV_ARCH_20 },
		180	{ "GeForce4-420-GO", NV_ARCH_20 },
		181	{ "GeForce4-420-GO-M32", NV_ARCH_20 },
		182	{ "Quadro4-500-XGL", NV_ARCH_20 },
		183	{ "GeForce4-440-GO-M64", NV_ARCH_20 },
		184	{ "Quadro4-200", NV_ARCH_20 },
		185	{ "Quadro4-550-XGL", NV_ARCH_20 },
		186	{ "Quadro4-500-GOGL", NV_ARCH_20 },
		187	{ "GeForce2", NV_ARCH_20 },
		188	{ "GeForce3", NV_ARCH_20 },
		189	{ "GeForce3 Ti 200", NV_ARCH_20 },
		190	{ "GeForce3 Ti 500", NV_ARCH_20 },
		191	{ "Quadro DDC", NV_ARCH_20 },
		192	{ "GeForce4 Ti 4600", NV_ARCH_20 },
		193	{ "GeForce4 Ti 4400", NV_ARCH_20 },
		194	{ "GeForce4 Ti 4200", NV_ARCH_20 },
		195	{ "Quadro4-900-XGL", NV_ARCH_20 },
		196	{ "Quadro4-750-XGL", NV_ARCH_20 },
		197	{ "Quadro4-700-XGL", NV_ARCH_20 }
		198	};
		199
		200	static struct pci_device_id rivafb_pci_tbl[] = {
		201	{ PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
		202	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_128 },
		203	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
		204	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT },
		205	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
		206	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_TNT2 },
		207	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
		208	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_UTNT2 },
		209	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
		210	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
		211	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
		212	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_VTNT2 },
		213	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
		214	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_RIVA_ITNT2 },
		215	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
		216	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_SDR },
		217	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
		218	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE_DDR },
		219	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
		220	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO },
		221	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
		222	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX },
		223	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
		224	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_MX2 },
		225	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
		226	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GO },
		227	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
		228	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_MXR },
		229	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
		230	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS },
		231	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
		232	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_GTS2 },
		233	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
		234	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE2_ULTRA },
		235	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
		236	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO2_PRO },
		237	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
		238	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_460 },
		239	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
		240	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_440 },
		241	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
		242	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_MX_420 },
473	giacomo	243	{ PCI_VENDOR_ID_NVIDIA, 0x0182,
		244	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_TEST },
472	giacomo	245	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
		246	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO },
		247	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
		248	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO },
		249	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
		250	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_420_GO_M32 },
		251	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
		252	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500XGL },
		253	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
		254	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_440_GO_M64 },
		255	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
		256	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_200 },
		257	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
		258	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_550XGL },
		259	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
		260	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_500_GOGL },
		261	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
		262	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_IGEFORCE2 },
		263	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
		264	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3 },
		265	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
		266	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_1 },
		267	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
		268	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE3_2 },
		269	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
		270	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO_DDC },
		271	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
		272	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4600 },
		273	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
		274	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4400 },
		275	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
		276	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_GEFORCE4_TI_4200 },
		277	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
		278	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_900XGL },
		279	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
		280	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_750XGL },
		281	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
		282	PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_QUADRO4_700XGL },
		283	{ 0, } /* terminate list */
		284	};
		285	MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
		286
		287	/* ------------------------------------------------------------------------- *
		288	*
		289	* global variables
		290	*
		291	* ------------------------------------------------------------------------- */
		292
		293	/* command line data, set in rivafb_setup() */
		294	static u32 pseudo_palette[17];
		295	static int flatpanel __initdata = -1; /* Autodetect later */
		296	static int forceCRTC __initdata = -1;
		297	#ifdef CONFIG_MTRR
		298	static int nomtrr __initdata = 0;
		299	#endif
		300
		301	#ifndef MODULE
		302	static char *mode_option __initdata = NULL;
		303	#endif
		304
		305	static struct fb_fix_screeninfo rivafb_fix = {
		306	.id = "nVidia",
		307	.type = FB_TYPE_PACKED_PIXELS,
		308	.xpanstep = 1,
		309	.ypanstep = 1,
		310	};
		311
		312	static struct fb_var_screeninfo rivafb_default_var = {
		313	.xres = 640,
		314	.yres = 480,
		315	.xres_virtual = 640,
		316	.yres_virtual = 480,
		317	.bits_per_pixel = 8,
		318	.red = {0, 8, 0},
		319	.green = {0, 8, 0},
		320	.blue = {0, 8, 0},
		321	.transp = {0, 0, 0},
		322	.activate = FB_ACTIVATE_NOW,
		323	.height = -1,
		324	.width = -1,
		325	.accel_flags = FB_ACCELF_TEXT,
		326	.pixclock = 39721,
		327	.left_margin = 40,
		328	.right_margin = 24,
		329	.upper_margin = 32,
		330	.lower_margin = 11,
		331	.hsync_len = 96,
		332	.vsync_len = 2,
		333	.vmode = FB_VMODE_NONINTERLACED
		334	};
		335
		336	/* from GGI */
		337	static const struct riva_regs reg_template = {
		338	{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
		339	0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
		340	0x41, 0x01, 0x0F, 0x00, 0x00},
		341	{0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
		342	0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
		343	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
		344	0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		345	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
		346	0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		347	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
		348	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
		349	0x00, /* 0x40 */
		350	},
		351	{0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
		352	0xFF},
		353	{0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
		354	0xEB /* MISC */
		355	};
		356
		357	/* ------------------------------------------------------------------------- *
		358	*
		359	* MMIO access macros
		360	*
		361	* ------------------------------------------------------------------------- */
		362
		363	static inline void CRTCout(struct riva_par *par, unsigned char index,
		364	unsigned char val)
		365	{
		366	VGA_WR08(par->riva.PCIO, 0x3d4, index);
		367	VGA_WR08(par->riva.PCIO, 0x3d5, val);
		368	}
		369
		370	static inline unsigned char CRTCin(struct riva_par *par,
		371	unsigned char index)
		372	{
		373	VGA_WR08(par->riva.PCIO, 0x3d4, index);
		374	return (VGA_RD08(par->riva.PCIO, 0x3d5));
		375	}
		376
		377	static inline void GRAout(struct riva_par *par, unsigned char index,
		378	unsigned char val)
		379	{
		380	VGA_WR08(par->riva.PVIO, 0x3ce, index);
		381	VGA_WR08(par->riva.PVIO, 0x3cf, val);
		382	}
		383
		384	static inline unsigned char GRAin(struct riva_par *par,
		385	unsigned char index)
		386	{
		387	VGA_WR08(par->riva.PVIO, 0x3ce, index);
		388	return (VGA_RD08(par->riva.PVIO, 0x3cf));
		389	}
		390
		391	static inline void SEQout(struct riva_par *par, unsigned char index,
		392	unsigned char val)
		393	{
		394	VGA_WR08(par->riva.PVIO, 0x3c4, index);
		395	VGA_WR08(par->riva.PVIO, 0x3c5, val);
		396	}
		397
		398	static inline unsigned char SEQin(struct riva_par *par,
		399	unsigned char index)
		400	{
		401	VGA_WR08(par->riva.PVIO, 0x3c4, index);
		402	return (VGA_RD08(par->riva.PVIO, 0x3c5));
		403	}
		404
		405	static inline void ATTRout(struct riva_par *par, unsigned char index,
		406	unsigned char val)
		407	{
		408	VGA_WR08(par->riva.PCIO, 0x3c0, index);
		409	VGA_WR08(par->riva.PCIO, 0x3c0, val);
		410	}
		411
		412	static inline unsigned char ATTRin(struct riva_par *par,
		413	unsigned char index)
		414	{
		415	VGA_WR08(par->riva.PCIO, 0x3c0, index);
		416	return (VGA_RD08(par->riva.PCIO, 0x3c1));
		417	}
		418
		419	static inline void MISCout(struct riva_par *par, unsigned char val)
		420	{
		421	VGA_WR08(par->riva.PVIO, 0x3c2, val);
		422	}
		423
		424	static inline unsigned char MISCin(struct riva_par *par)
		425	{
		426	return (VGA_RD08(par->riva.PVIO, 0x3cc));
		427	}
		428
		429	static u8 byte_rev[256] = {
		430	0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
		431	0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
		432	0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
		433	0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
		434	0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
		435	0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
		436	0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
		437	0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
		438	0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
		439	0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
		440	0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
		441	0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
		442	0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
		443	0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
		444	0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
		445	0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
		446	0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
		447	0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
		448	0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
		449	0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
		450	0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
		451	0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
		452	0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
		453	0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
		454	0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
		455	0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
		456	0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
		457	0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
		458	0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
		459	0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
		460	0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
		461	0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
		462	};
		463
		464	static inline void reverse_order(u32 *l)
		465	{
		466	u8 a = (u8 )l;
		467	a = byte_rev[a], a++;
		468	a = byte_rev[a], a++;
		469	a = byte_rev[a], a++;
		470	a = byte_rev[a];
		471	}
		472
		473	/* ------------------------------------------------------------------------- *
		474	*
		475	* cursor stuff
		476	*
		477	* ------------------------------------------------------------------------- */
		478
		479	/**
		480	* rivafb_load_cursor_image - load cursor image to hardware
		481	* @data: address to monochrome bitmap (1 = foreground color, 0 = background)
		482	* @par: pointer to private data
		483	* @w: width of cursor image in pixels
		484	* @h: height of cursor image in scanlines
		485	* @bg: background color (ARGB1555) - alpha bit determines opacity
		486	* @fg: foreground color (ARGB1555)
		487	*
		488	* DESCRIPTiON:
		489	* Loads cursor image based on a monochrome source and mask bitmap. The
		490	* image bits determines the color of the pixel, 0 for background, 1 for
		491	* foreground. Only the affected region (as determined by @w and @h
		492	* parameters) will be updated.
		493	*
		494	* CALLED FROM:
		495	* rivafb_cursor()
		496	*/
		497	static void rivafb_load_cursor_image(struct riva_par par, u8 data,
		498	u8 *mask, u16 bg, u16 fg, u32 w, u32 h)
		499	{
		500	int i, j, k = 0;
		501	u32 b, m, tmp;
		502
		503	for (i = 0; i < h; i++) {
		504	b = ((u32 )data)++;
		505	m = ((u32 )mask)++;
		506	reverse_order(&b);
		507
		508	for (j = 0; j < w/2; j++) {
		509	tmp = 0;
		510	#if defined (__BIG_ENDIAN)
		511	if (m & (1 << 31)) {
		512	fg \|= 1 << 15;
		513	bg \|= 1 << 15;
		514	}
		515	tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
		516	b <<= 1;
		517	m <<= 1;
		518
		519	if (m & (1 << 31)) {
		520	fg \|= 1 << 15;
		521	bg \|= 1 << 15;
		522	}
		523	tmp \|= (b & (1 << 31)) ? fg : bg;
		524	b <<= 1;
		525	m <<= 1;
		526	#else
		527	if (m & 1) {
		528	fg \|= 1 << 15;
		529	bg \|= 1 << 15;
		530	}
		531	tmp = (b & 1) ? fg : bg;
		532	b >>= 1;
		533	m >>= 1;
		534
		535	if (m & 1) {
		536	fg \|= 1 << 15;
		537	bg \|= 1 << 15;
		538	}
		539	tmp \|= (b & 1) ? fg << 16 : bg << 16;
		540	b >>= 1;
		541	m >>= 1;
		542	#endif
		543	writel(tmp, par->riva.CURSOR + k++);
		544	}
		545	k += (MAX_CURS - w)/2;
		546	}
		547	}
		548
		549	/* ------------------------------------------------------------------------- *
		550	*
		551	* general utility functions
		552	*
		553	* ------------------------------------------------------------------------- */
		554
		555	/**
		556	* riva_wclut - set CLUT entry
		557	* @chip: pointer to RIVA_HW_INST object
		558	* @regnum: register number
		559	* @red: red component
		560	* @green: green component
		561	* @blue: blue component
		562	*
		563	* DESCRIPTION:
		564	* Sets color register @regnum.
		565	*
		566	* CALLED FROM:
		567	* rivafb_setcolreg()
		568	*/
		569	static void riva_wclut(RIVA_HW_INST *chip,
		570	unsigned char regnum, unsigned char red,
		571	unsigned char green, unsigned char blue)
		572	{
		573	VGA_WR08(chip->PDIO, 0x3c8, regnum);
		574	VGA_WR08(chip->PDIO, 0x3c9, red);
		575	VGA_WR08(chip->PDIO, 0x3c9, green);
		576	VGA_WR08(chip->PDIO, 0x3c9, blue);
		577	}
		578
		579	/**
		580	* riva_rclut - read fromCLUT register
		581	* @chip: pointer to RIVA_HW_INST object
		582	* @regnum: register number
		583	* @red: red component
		584	* @green: green component
		585	* @blue: blue component
		586	*
		587	* DESCRIPTION:
		588	* Reads red, green, and blue from color register @regnum.
		589	*
		590	* CALLED FROM:
		591	* rivafb_setcolreg()
		592	*/
		593	static void riva_rclut(RIVA_HW_INST *chip,
		594	unsigned char regnum, unsigned char *red,
		595	unsigned char green, unsigned char blue)
		596	{
		597
		598	VGA_WR08(chip->PDIO, 0x3c8, regnum);
		599	*red = VGA_RD08(chip->PDIO, 0x3c9);
		600	*green = VGA_RD08(chip->PDIO, 0x3c9);
		601	*blue = VGA_RD08(chip->PDIO, 0x3c9);
		602	}
		603
		604	/**
		605	* riva_save_state - saves current chip state
		606	* @par: pointer to riva_par object containing info for current riva board
		607	* @regs: pointer to riva_regs object
		608	*
		609	* DESCRIPTION:
		610	* Saves current chip state to @regs.
		611	*
		612	* CALLED FROM:
		613	* rivafb_probe()
		614	*/
		615	/* from GGI */
		616	static void riva_save_state(struct riva_par par, struct riva_regs regs)
		617	{
		618	int i;
		619
		620	par->riva.LockUnlock(&par->riva, 0);
		621
		622	par->riva.UnloadStateExt(&par->riva, &regs->ext);
		623
		624	regs->misc_output = MISCin(par);
		625
		626	for (i = 0; i < NUM_CRT_REGS; i++)
		627	regs->crtc[i] = CRTCin(par, i);
		628
		629	for (i = 0; i < NUM_ATC_REGS; i++)
		630	regs->attr[i] = ATTRin(par, i);
		631
		632	for (i = 0; i < NUM_GRC_REGS; i++)
		633	regs->gra[i] = GRAin(par, i);
		634
		635	for (i = 0; i < NUM_SEQ_REGS; i++)
		636	regs->seq[i] = SEQin(par, i);
		637	}
		638
		639	/**
		640	* riva_load_state - loads current chip state
		641	* @par: pointer to riva_par object containing info for current riva board
		642	* @regs: pointer to riva_regs object
		643	*
		644	* DESCRIPTION:
		645	* Loads chip state from @regs.
		646	*
		647	* CALLED FROM:
		648	* riva_load_video_mode()
		649	* rivafb_probe()
		650	* rivafb_remove()
		651	*/
		652	/* from GGI */
		653	static void riva_load_state(struct riva_par par, struct riva_regs regs)
		654	{
		655	RIVA_HW_STATE *state = &regs->ext;
		656	int i;
		657
		658	CRTCout(par, 0x11, 0x00);
		659
		660	par->riva.LockUnlock(&par->riva, 0);
		661
		662	par->riva.LoadStateExt(&par->riva, state);
		663
		664	MISCout(par, regs->misc_output);
		665
		666	for (i = 0; i < NUM_CRT_REGS; i++) {
		667	switch (i) {
		668	case 0x19:
		669	case 0x20 ... 0x40:
		670	break;
		671	default:
		672	CRTCout(par, i, regs->crtc[i]);
		673	}
		674	}
		675
		676	for (i = 0; i < NUM_ATC_REGS; i++)
		677	ATTRout(par, i, regs->attr[i]);
		678
		679	for (i = 0; i < NUM_GRC_REGS; i++)
		680	GRAout(par, i, regs->gra[i]);
		681
		682	for (i = 0; i < NUM_SEQ_REGS; i++)
		683	SEQout(par, i, regs->seq[i]);
		684	}
		685
		686	/**
		687	* riva_load_video_mode - calculate timings
		688	* @info: pointer to fb_info object containing info for current riva board
		689	*
		690	* DESCRIPTION:
		691	* Calculate some timings and then send em off to riva_load_state().
		692	*
		693	* CALLED FROM:
		694	* rivafb_set_par()
		695	*/
		696	static void riva_load_video_mode(struct fb_info *info)
		697	{
		698	int bpp, width, hDisplaySize, hDisplay, hStart,
		699	hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
		700	int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
		701	struct riva_par par = (struct riva_par ) info->par;
		702	struct riva_regs newmode;
		703
		704	/* time to calculate */
		705	rivafb_blank(1, info);
		706
		707	bpp = info->var.bits_per_pixel;
		708	if (bpp == 16 && info->var.green.length == 5)
		709	bpp = 15;
		710	width = info->var.xres_virtual;
		711	hDisplaySize = info->var.xres;
		712	hDisplay = (hDisplaySize / 8) - 1;
		713	hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
		714	hEnd = (hDisplaySize + info->var.right_margin +
		715	info->var.hsync_len) / 8 - 1;
		716	hTotal = (hDisplaySize + info->var.right_margin +
		717	info->var.hsync_len + info->var.left_margin) / 8 - 5;
		718	hBlankStart = hDisplay;
		719	hBlankEnd = hTotal + 4;
		720
		721	height = info->var.yres_virtual;
		722	vDisplay = info->var.yres - 1;
		723	vStart = info->var.yres + info->var.lower_margin - 1;
		724	vEnd = info->var.yres + info->var.lower_margin +
		725	info->var.vsync_len - 1;
		726	vTotal = info->var.yres + info->var.lower_margin +
		727	info->var.vsync_len + info->var.upper_margin + 2;
		728	vBlankStart = vDisplay;
		729	vBlankEnd = vTotal + 1;
		730	dotClock = 1000000000 / info->var.pixclock;
		731
		732	memcpy(&newmode, &reg_template, sizeof(struct riva_regs));
		733
		734	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
		735	vTotal \|= 1;
		736
		737	if (par->FlatPanel) {
		738	vStart = vTotal - 3;
		739	vEnd = vTotal - 2;
		740	vBlankStart = vStart;
		741	hStart = hTotal - 3;
		742	hEnd = hTotal - 2;
		743	hBlankEnd = hTotal + 4;
		744	}
		745
		746	newmode.crtc[0x0] = Set8Bits (hTotal);
		747	newmode.crtc[0x1] = Set8Bits (hDisplay);
		748	newmode.crtc[0x2] = Set8Bits (hBlankStart);
		749	newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) \| SetBit (7);
		750	newmode.crtc[0x4] = Set8Bits (hStart);
		751	newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
		752	\| SetBitField (hEnd, 4: 0, 4:0);
		753	newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
		754	newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
		755	\| SetBitField (vDisplay, 8: 8, 1:1)
		756	\| SetBitField (vStart, 8: 8, 2:2)
		757	\| SetBitField (vBlankStart, 8: 8, 3:3)
		758	\| SetBit (4)
		759	\| SetBitField (vTotal, 9: 9, 5:5)
		760	\| SetBitField (vDisplay, 9: 9, 6:6)
		761	\| SetBitField (vStart, 9: 9, 7:7);
		762	newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
		763	\| SetBit (6);
		764	newmode.crtc[0x10] = Set8Bits (vStart);
		765	newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
		766	\| SetBit (5);
		767	newmode.crtc[0x12] = Set8Bits (vDisplay);
		768	newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
		769	newmode.crtc[0x15] = Set8Bits (vBlankStart);
		770	newmode.crtc[0x16] = Set8Bits (vBlankEnd);
		771
		772	newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
		773	\| SetBitField(vBlankStart,10:10,3:3)
		774	\| SetBitField(vStart,10:10,2:2)
		775	\| SetBitField(vDisplay,10:10,1:1)
		776	\| SetBitField(vTotal,10:10,0:0);
		777	newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
		778	\| SetBitField(hDisplay,8:8,1:1)
		779	\| SetBitField(hBlankStart,8:8,2:2)
		780	\| SetBitField(hStart,8:8,3:3);
		781	newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
		782	\| SetBitField(vDisplay,11:11,2:2)
		783	\| SetBitField(vStart,11:11,4:4)
		784	\| SetBitField(vBlankStart,11:11,6:6);
		785
		786	if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
		787	int tmp = (hTotal >> 1) & ~1;
		788	newmode.ext.interlace = Set8Bits(tmp);
		789	newmode.ext.horiz \|= SetBitField(tmp, 8:8,4:4);
		790	} else
		791	newmode.ext.interlace = 0xff; /* interlace off */
		792
		793	if (par->riva.Architecture >= NV_ARCH_10)
		794	par->riva.CURSOR = (U032 *)(info->screen_base + par->riva.CursorStart);
		795
		796	if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
		797	newmode.misc_output &= ~0x40;
		798	else
		799	newmode.misc_output \|= 0x40;
		800	if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
		801	newmode.misc_output &= ~0x80;
		802	else
		803	newmode.misc_output \|= 0x80;
		804
		805	par->riva.CalcStateExt(&par->riva, &newmode.ext, bpp, width,
		806	hDisplaySize, height, dotClock);
		807
		808	newmode.ext.scale = par->riva.PRAMDAC[0x00000848/4] & 0xfff000ff;
		809	if (par->FlatPanel == 1) {
		810	newmode.ext.pixel \|= (1 << 7);
		811	newmode.ext.scale \|= (1 << 8);
		812	}
		813	if (par->SecondCRTC) {
		814	newmode.ext.head = par->riva.PCRTC0[0x00000860/4] & ~0x00001000;
		815	newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] \| 0x00001000;
		816	newmode.ext.crtcOwner = 3;
		817	newmode.ext.pllsel \|= 0x20000800;
		818	newmode.ext.vpll2 = newmode.ext.vpll;
		819	} else if (par->riva.twoHeads) {
		820	newmode.ext.head = par->riva.PCRTC0[0x00000860/4] \| 0x00001000;
		821	newmode.ext.head2 = par->riva.PCRTC0[0x00002860/4] & ~0x00001000;
		822	newmode.ext.crtcOwner = 0;
		823	newmode.ext.vpll2 = par->riva.PRAMDAC0[0x00000520/4];
		824	}
		825	if (par->FlatPanel == 1) {
		826	newmode.ext.pixel \|= (1 << 7);
		827	newmode.ext.scale \|= (1 << 8);
		828	}
		829	newmode.ext.cursorConfig = 0x02000100;
		830	par->current_state = newmode;
		831	riva_load_state(par, &par->current_state);
		832	par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
		833	rivafb_blank(0, info);
		834	}
		835
		836	/**
		837	* rivafb_do_maximize -
		838	* @info: pointer to fb_info object containing info for current riva board
		839	* @var:
		840	* @nom:
		841	* @den:
		842	*
		843	* DESCRIPTION:
		844	* .
		845	*
		846	* RETURNS:
		847	* -EINVAL on failure, 0 on success
		848	*
		849	*
		850	* CALLED FROM:
		851	* rivafb_check_var()
		852	*/
		853	static int rivafb_do_maximize(struct fb_info *info,
		854	struct fb_var_screeninfo *var,
		855	int nom, int den)
		856	{
		857	static struct {
		858	int xres, yres;
		859	} modes[] = {
		860	{1600, 1280},
		861	{1280, 1024},
		862	{1024, 768},
		863	{800, 600},
		864	{640, 480},
		865	{-1, -1}
		866	};
		867	int i;
		868
		869	/* use highest possible virtual resolution */
		870	if (var->xres_virtual == -1 && var->yres_virtual == -1) {
		871	printk(KERN_WARNING PFX
		872	"using maximum available virtual resolution\n");
		873	for (i = 0; modes[i].xres != -1; i++) {
		874	if (modes[i].xres * nom / den * modes[i].yres <
		875	info->fix.smem_len / 2)
		876	break;
		877	}
		878	if (modes[i].xres == -1) {
		879	printk(KERN_ERR PFX
		880	"could not find a virtual resolution that fits into video memory!!\n");
		881	DPRINTK("EXIT - EINVAL error\n");
		882	return -EINVAL;
		883	}
		884	var->xres_virtual = modes[i].xres;
		885	var->yres_virtual = modes[i].yres;
		886
		887	printk(KERN_INFO PFX
		888	"virtual resolution set to maximum of %dx%d\n",
		889	var->xres_virtual, var->yres_virtual);
		890	} else if (var->xres_virtual == -1) {
		891	var->xres_virtual = (info->fix.smem_len * den /
		892	(nom * var->yres_virtual * 2)) & ~15;
		893	printk(KERN_WARNING PFX
		894	"setting virtual X resolution to %d\n", var->xres_virtual);
		895	} else if (var->yres_virtual == -1) {
		896	var->xres_virtual = (var->xres_virtual + 15) & ~15;
		897	var->yres_virtual = info->fix.smem_len * den /
		898	(nom * var->xres_virtual * 2);
		899	printk(KERN_WARNING PFX
		900	"setting virtual Y resolution to %d\n", var->yres_virtual);
		901	} else {
		902	var->xres_virtual = (var->xres_virtual + 15) & ~15;
		903	if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
		904	printk(KERN_ERR PFX
		905	"mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
		906	var->xres, var->yres, var->bits_per_pixel);
		907	DPRINTK("EXIT - EINVAL error\n");
		908	return -EINVAL;
		909	}
		910	}
		911
		912	if (var->xres_virtual * nom / den >= 8192) {
		913	printk(KERN_WARNING PFX
		914	"virtual X resolution (%d) is too high, lowering to %d\n",
		915	var->xres_virtual, 8192 * den / nom - 16);
		916	var->xres_virtual = 8192 * den / nom - 16;
		917	}
		918
		919	if (var->xres_virtual < var->xres) {
		920	printk(KERN_ERR PFX
		921	"virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
		922	return -EINVAL;
		923	}
		924
		925	if (var->yres_virtual < var->yres) {
		926	printk(KERN_ERR PFX
		927	"virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
		928	return -EINVAL;
		929	}
		930	return 0;
		931	}
		932
		933	/* acceleration routines */
		934	inline void wait_for_idle(struct riva_par *par)
		935	{
		936	while (par->riva.Busy(&par->riva));
		937	}
		938
		939	/* set copy ROP, no mask */
		940	static void riva_setup_ROP(struct riva_par *par)
		941	{
		942	RIVA_FIFO_FREE(par->riva, Patt, 5);
		943	par->riva.Patt->Shape = 0;
		944	par->riva.Patt->Color0 = 0xffffffff;
		945	par->riva.Patt->Color1 = 0xffffffff;
		946	par->riva.Patt->Monochrome[0] = 0xffffffff;
		947	par->riva.Patt->Monochrome[1] = 0xffffffff;
		948
		949	RIVA_FIFO_FREE(par->riva, Rop, 1);
		950	par->riva.Rop->Rop3 = 0xCC;
		951	}
		952
		953	void riva_setup_accel(struct riva_par *par)
		954	{
		955	RIVA_FIFO_FREE(par->riva, Clip, 2);
		956	par->riva.Clip->TopLeft = 0x0;
		957	par->riva.Clip->WidthHeight = 0x80008000;
		958	riva_setup_ROP(par);
		959	wait_for_idle(par);
		960	}
		961
		962	/**
		963	* riva_get_cmap_len - query current color map length
		964	* @var: standard kernel fb changeable data
		965	*
		966	* DESCRIPTION:
		967	* Get current color map length.
		968	*
		969	* RETURNS:
		970	* Length of color map
		971	*
		972	* CALLED FROM:
		973	* rivafb_setcolreg()
		974	*/
		975	static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
		976	{
		977	int rc = 256; /* reasonable default */
		978
		979	switch (var->green.length) {
		980	case 8:
		981	rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
		982	break;
		983	case 5:
		984	rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
		985	break;
		986	case 6:
		987	rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
		988	break;
		989	default:
		990	/* should not occur */
		991	break;
		992	}
		993	return rc;
		994	}
		995
		996	/* ------------------------------------------------------------------------- *
		997	*
		998	* framebuffer operations
		999	*
		1000	* ------------------------------------------------------------------------- */
		1001
		1002	static int rivafb_open(struct fb_info *info, int user)
		1003	{
		1004	struct riva_par par = (struct riva_par ) info->par;
		1005	int cnt = atomic_read(&par->ref_count);
		1006
		1007	if (!cnt) {
		1008	memset(&par->state, 0, sizeof(struct vgastate));
		1009	par->state.flags = VGA_SAVE_MODE \| VGA_SAVE_FONTS;
		1010	/* save the DAC for Riva128 */
		1011	if (par->riva.Architecture == NV_ARCH_03)
		1012	par->state.flags \|= VGA_SAVE_CMAP;
		1013	save_vga(&par->state);
		1014
		1015	RivaGetConfig(&par->riva, par->Chipset);
		1016	/* vgaHWunlock() + riva unlock (0x7F) */
		1017	CRTCout(par, 0x11, 0xFF);
		1018	par->riva.LockUnlock(&par->riva, 0);
		1019
		1020	riva_save_state(par, &par->initial_state);
		1021	}
		1022	atomic_inc(&par->ref_count);
		1023	return 0;
		1024	}
		1025
		1026	static int rivafb_release(struct fb_info *info, int user)
		1027	{
		1028	struct riva_par par = (struct riva_par ) info->par;
		1029	int cnt = atomic_read(&par->ref_count);
		1030
		1031	if (!cnt)
		1032	return -EINVAL;
		1033	if (cnt == 1) {
		1034	par->riva.LockUnlock(&par->riva, 0);
		1035	par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
		1036	riva_load_state(par, &par->initial_state);
		1037	restore_vga(&par->state);
		1038	par->riva.LockUnlock(&par->riva, 1);
		1039	}
		1040	atomic_dec(&par->ref_count);
		1041	return 0;
		1042	}
		1043
		1044	static int rivafb_check_var(struct fb_var_screeninfo var, struct fb_info info)
		1045	{
		1046	int nom, den; /* translating from pixels->bytes */
		1047
		1048	switch (var->bits_per_pixel) {
		1049	case 1 ... 8:
		1050	var->red.offset = var->green.offset = var->blue.offset = 0;
		1051	var->red.length = var->green.length = var->blue.length = 8;
		1052	var->bits_per_pixel = 8;
		1053	nom = den = 1;
		1054	break;
		1055	case 9 ... 15:
		1056	var->green.length = 5;
		1057	/* fall through */
		1058	case 16:
		1059	var->bits_per_pixel = 16;
		1060	if (var->green.length == 5) {
		1061	/* 0rrrrrgg gggbbbbb */
		1062	var->red.offset = 10;
		1063	var->green.offset = 5;
		1064	var->blue.offset = 0;
		1065	var->red.length = 5;
		1066	var->green.length = 5;
		1067	var->blue.length = 5;
		1068	} else {
		1069	/* rrrrrggg gggbbbbb */
		1070	var->red.offset = 11;
		1071	var->green.offset = 5;
		1072	var->blue.offset = 0;
		1073	var->red.length = 5;
		1074	var->green.length = 6;
		1075	var->blue.length = 5;
		1076	}
		1077	nom = 2;
		1078	den = 1;
		1079	break;
		1080	case 17 ... 32:
		1081	var->red.length = var->green.length = var->blue.length = 8;
		1082	var->bits_per_pixel = 32;
		1083	var->red.offset = 16;
		1084	var->green.offset = 8;
		1085	var->blue.offset = 0;
		1086	nom = 4;
		1087	den = 1;
		1088	break;
		1089	default:
		1090	printk(KERN_ERR PFX
		1091	"mode %dx%dx%d rejected...color depth not supported.\n",
		1092	var->xres, var->yres, var->bits_per_pixel);
		1093	DPRINTK("EXIT, returning -EINVAL\n");
		1094	return -EINVAL;
		1095	}
		1096
		1097	if (rivafb_do_maximize(info, var, nom, den) < 0)
		1098	return -EINVAL;
		1099
		1100	if (var->xoffset < 0)
		1101	var->xoffset = 0;
		1102	if (var->yoffset < 0)
		1103	var->yoffset = 0;
		1104
		1105	/* truncate xoffset and yoffset to maximum if too high */
		1106	if (var->xoffset > var->xres_virtual - var->xres)
		1107	var->xoffset = var->xres_virtual - var->xres - 1;
		1108
		1109	if (var->yoffset > var->yres_virtual - var->yres)
		1110	var->yoffset = var->yres_virtual - var->yres - 1;
		1111
		1112	var->red.msb_right =
		1113	var->green.msb_right =
		1114	var->blue.msb_right =
		1115	var->transp.offset = var->transp.length = var->transp.msb_right = 0;
		1116	return 0;
		1117	}
		1118
		1119	static int rivafb_set_par(struct fb_info *info)
		1120	{
		1121	struct riva_par par = (struct riva_par ) info->par;
		1122
		1123	riva_load_video_mode(info);
		1124	riva_setup_accel(par);
		1125
		1126	info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
		1127	info->fix.visual = (info->var.bits_per_pixel == 8) ?
		1128	FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
		1129	return 0;
		1130	}
		1131
		1132	/**
		1133	* rivafb_pan_display
		1134	* @var: standard kernel fb changeable data
		1135	* @con: TODO
		1136	* @info: pointer to fb_info object containing info for current riva board
		1137	*
		1138	* DESCRIPTION:
		1139	* Pan (or wrap, depending on the `vmode' field) the display using the
		1140	* `xoffset' and `yoffset' fields of the `var' structure.
		1141	* If the values don't fit, return -EINVAL.
		1142	*
		1143	* This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
		1144	*/
		1145	static int rivafb_pan_display(struct fb_var_screeninfo *var,
		1146	struct fb_info *info)
		1147	{
		1148	struct riva_par par = (struct riva_par )info->par;
		1149	unsigned int base;
		1150
		1151	if (var->xoffset > (var->xres_virtual - var->xres))
		1152	return -EINVAL;
		1153	if (var->yoffset > (var->yres_virtual - var->yres))
		1154	return -EINVAL;
		1155
		1156	if (var->vmode & FB_VMODE_YWRAP) {
		1157	if (var->yoffset < 0
		1158	\|\| var->yoffset >= info->var.yres_virtual
		1159	\|\| var->xoffset) return -EINVAL;
		1160	} else {
		1161	if (var->xoffset + info->var.xres > info->var.xres_virtual \|\|
		1162	var->yoffset + info->var.yres > info->var.yres_virtual)
		1163	return -EINVAL;
		1164	}
		1165
		1166	base = var->yoffset * info->fix.line_length + var->xoffset;
		1167
		1168	par->riva.SetStartAddress(&par->riva, base);
		1169
		1170	info->var.xoffset = var->xoffset;
		1171	info->var.yoffset = var->yoffset;
		1172
		1173	if (var->vmode & FB_VMODE_YWRAP)
		1174	info->var.vmode \|= FB_VMODE_YWRAP;
		1175	else
		1176	info->var.vmode &= ~FB_VMODE_YWRAP;
		1177	return 0;
		1178	}
		1179
		1180	static int rivafb_blank(int blank, struct fb_info *info)
		1181	{
		1182	struct riva_par par= (struct riva_par )info->par;
		1183	unsigned char tmp, vesa;
		1184
		1185	tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
		1186	vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
		1187
		1188	if (blank) {
		1189	tmp \|= 0x20;
		1190	switch (blank - 1) {
		1191	case VESA_NO_BLANKING:
		1192	break;
		1193	case VESA_VSYNC_SUSPEND:
		1194	vesa \|= 0x80;
		1195	break;
		1196	case VESA_HSYNC_SUSPEND:
		1197	vesa \|= 0x40;
		1198	break;
		1199	case VESA_POWERDOWN:
		1200	vesa \|= 0xc0;
		1201	break;
		1202	}
		1203	}
		1204	SEQout(par, 0x01, tmp);
		1205	CRTCout(par, 0x1a, vesa);
		1206	return 0;
		1207	}
		1208
		1209	/**
		1210	* rivafb_setcolreg
		1211	* @regno: register index
		1212	* @red: red component
		1213	* @green: green component
		1214	* @blue: blue component
		1215	* @transp: transparency
		1216	* @info: pointer to fb_info object containing info for current riva board
		1217	*
		1218	* DESCRIPTION:
		1219	* Set a single color register. The values supplied have a 16 bit
		1220	* magnitude.
		1221	*
		1222	* RETURNS:
		1223	* Return != 0 for invalid regno.
		1224	*
		1225	* CALLED FROM:
		1226	* fbcmap.c:fb_set_cmap()
		1227	*/
		1228	static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
		1229	unsigned blue, unsigned transp,
		1230	struct fb_info *info)
		1231	{
		1232	struct riva_par par = (struct riva_par )info->par;
		1233	RIVA_HW_INST *chip = &par->riva;
		1234	int i;
		1235
		1236	if (regno >= riva_get_cmap_len(&info->var))
		1237	return -EINVAL;
		1238
		1239	if (info->var.grayscale) {
		1240	/* gray = 0.30R + 0.59G + 0.11B /
		1241	red = green = blue =
		1242	(red * 77 + green * 151 + blue * 28) >> 8;
		1243	}
		1244
		1245	switch (info->var.bits_per_pixel) {
		1246	case 8:
		1247	/* "transparent" stuff is completely ignored. */
		1248	riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
		1249	break;
		1250	case 16:
		1251	if (info->var.green.length == 5) {
		1252	if (regno < 16) {
		1253	/* 0rrrrrgg gggbbbbb */
		1254	((u32 *)info->pseudo_palette)[regno] =
		1255	((red & 0xf800) >> 1) \|
		1256	((green & 0xf800) >> 6) \|
		1257	((blue & 0xf800) >> 11);
		1258	}
		1259	for (i = 0; i < 8; i++)
		1260	riva_wclut(chip, regno*8+i, red >> 8,
		1261	green >> 8, blue >> 8);
		1262	} else {
		1263	u8 r, g, b;
		1264
		1265	if (regno < 16) {
		1266	/* rrrrrggg gggbbbbb */
		1267	((u32 *)info->pseudo_palette)[regno] =
		1268	((red & 0xf800) >> 0) \|
		1269	((green & 0xf800) >> 5) \|
		1270	((blue & 0xf800) >> 11);
		1271	}
		1272	if (regno < 32) {
		1273	for (i = 0; i < 8; i++) {
		1274	riva_wclut(chip, regno*8+i, red >> 8,
		1275	green >> 8, blue >> 8);
		1276	}
		1277	}
		1278	for (i = 0; i < 4; i++) {
		1279	riva_rclut(chip, regno*2+i, &r, &g, &b);
		1280	riva_wclut(chip, regno*4+i, r, green >> 8, b);
		1281	}
		1282	}
		1283	break;
		1284	case 32:
		1285	if (regno < 16) {
		1286	((u32 *)info->pseudo_palette)[regno] =
		1287	((red & 0xff00) << 8) \|
		1288	((green & 0xff00)) \| ((blue & 0xff00) >> 8);
		1289
		1290	}
		1291	riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
		1292	break;
		1293	default:
		1294	/* do nothing */
		1295	break;
		1296	}
		1297	return 0;
		1298	}
		1299
		1300	/**
		1301	* rivafb_fillrect - hardware accelerated color fill function
		1302	* @info: pointer to fb_info structure
		1303	* @rect: pointer to fb_fillrect structure
		1304	*
		1305	* DESCRIPTION:
		1306	* This function fills up a region of framebuffer memory with a solid
		1307	* color with a choice of two different ROP's, copy or invert.
		1308	*
		1309	* CALLED FROM:
		1310	* framebuffer hook
		1311	*/
		1312	static void rivafb_fillrect(struct fb_info info, const struct fb_fillrect rect)
		1313	{
		1314	struct riva_par par = (struct riva_par ) info->par;
		1315	u_int color, rop = 0;
		1316
		1317	if (info->var.bits_per_pixel == 8)
		1318	color = rect->color;
		1319	else
		1320	color = ((u32 *)info->pseudo_palette)[rect->color];
		1321
		1322	switch (rect->rop) {
		1323	case ROP_XOR:
		1324	rop = 0x66;
		1325	break;
		1326	case ROP_COPY:
		1327	default:
		1328	rop = 0xCC;
		1329	break;
		1330	}
		1331
		1332	RIVA_FIFO_FREE(par->riva, Rop, 1);
		1333	par->riva.Rop->Rop3 = rop;
		1334
		1335	RIVA_FIFO_FREE(par->riva, Bitmap, 1);
		1336	par->riva.Bitmap->Color1A = color;
		1337
		1338	RIVA_FIFO_FREE(par->riva, Bitmap, 2);
		1339	par->riva.Bitmap->UnclippedRectangle[0].TopLeft =
		1340	(rect->dx << 16) \| rect->dy;
		1341	par->riva.Bitmap->UnclippedRectangle[0].WidthHeight =
		1342	(rect->width << 16) \| rect->height;
		1343	RIVA_FIFO_FREE(par->riva, Rop, 1);
		1344	par->riva.Rop->Rop3 = 0xCC; // back to COPY
		1345	}
		1346
		1347	/**
		1348	* rivafb_copyarea - hardware accelerated blit function
		1349	* @info: pointer to fb_info structure
		1350	* @region: pointer to fb_copyarea structure
		1351	*
		1352	* DESCRIPTION:
		1353	* This copies an area of pixels from one location to another
		1354	*
		1355	* CALLED FROM:
		1356	* framebuffer hook
		1357	*/
		1358	static void rivafb_copyarea(struct fb_info info, const struct fb_copyarea region)
		1359	{
		1360	struct riva_par par = (struct riva_par ) info->par;
		1361
		1362	RIVA_FIFO_FREE(par->riva, Blt, 3);
		1363	par->riva.Blt->TopLeftSrc = (region->sy << 16) \| region->sx;
		1364	par->riva.Blt->TopLeftDst = (region->dy << 16) \| region->dx;
		1365	par->riva.Blt->WidthHeight = (region->height << 16) \| region->width;
		1366	wait_for_idle(par);
		1367	}
		1368
		1369	static inline void convert_bgcolor_16(u32 *col)
		1370	{
		1371	col = ((col & 0x00007C00) << 9)
		1372	\| ((*col & 0x000003E0) << 6)
		1373	\| ((*col & 0x0000001F) << 3)
		1374	\| 0xFF000000;
		1375	}
		1376
		1377	/**
		1378	* rivafb_imageblit: hardware accelerated color expand function
		1379	* @info: pointer to fb_info structure
		1380	* @image: pointer to fb_image structure
		1381	*
		1382	* DESCRIPTION:
		1383	* If the source is a monochrome bitmap, the function fills up a a region
		1384	* of framebuffer memory with pixels whose color is determined by the bit
		1385	* setting of the bitmap, 1 - foreground, 0 - background.
		1386	*
		1387	* If the source is not a monochrome bitmap, color expansion is not done.
		1388	* In this case, it is channeled to a software function.
		1389	*
		1390	* CALLED FROM:
		1391	* framebuffer hook
		1392	*/
		1393	static void rivafb_imageblit(struct fb_info *info,
		1394	const struct fb_image *image)
		1395	{
		1396	struct riva_par par = (struct riva_par ) info->par;
		1397	u32 fgx = 0, bgx = 0, width, tmp;
		1398	u8 cdat = (u8 ) image->data;
		1399	volatile u32 *d;
		1400	int i, size;
		1401
		1402	if (image->depth != 1) {
		1403	cfb_imageblit(info, image);
		1404	return;
		1405	}
		1406
		1407	switch (info->var.bits_per_pixel) {
		1408	case 8:
		1409	fgx = image->fg_color;
		1410	bgx = image->bg_color;
		1411	break;
		1412	case 16:
		1413	fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
		1414	bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
		1415	if (info->var.green.length == 6)
		1416	convert_bgcolor_16(&bgx);
		1417	break;
		1418	case 32:
		1419	fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
		1420	bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
		1421	break;
		1422	}
		1423
		1424	RIVA_FIFO_FREE(par->riva, Bitmap, 7);
		1425	par->riva.Bitmap->ClipE.TopLeft =
		1426	(image->dy << 16) \| (image->dx & 0xFFFF);
		1427	par->riva.Bitmap->ClipE.BottomRight =
		1428	(((image->dy + image->height) << 16) \|
		1429	((image->dx + image->width) & 0xffff));
		1430	par->riva.Bitmap->Color0E = bgx;
		1431	par->riva.Bitmap->Color1E = fgx;
		1432	par->riva.Bitmap->WidthHeightInE =
		1433	(image->height << 16) \| ((image->width + 31) & ~31);
		1434	par->riva.Bitmap->WidthHeightOutE =
		1435	(image->height << 16) \| ((image->width + 31) & ~31);
		1436	par->riva.Bitmap->PointE =
		1437	(image->dy << 16) \| (image->dx & 0xFFFF);
		1438
		1439	d = &par->riva.Bitmap->MonochromeData01E;
		1440
		1441	width = (image->width + 31)/32;
		1442	size = width * image->height;
		1443	while (size >= 16) {
		1444	RIVA_FIFO_FREE(par->riva, Bitmap, 16);
		1445	for (i = 0; i < 16; i++) {
		1446	tmp = ((u32 )cdat)++;
		1447	reverse_order(&tmp);
		1448	d[i] = tmp;
		1449	}
		1450	size -= 16;
		1451	}
		1452	if (size) {
		1453	RIVA_FIFO_FREE(par->riva, Bitmap, size);
		1454	for (i = 0; i < size; i++) {
		1455	tmp = ((u32 ) cdat)++;
		1456	reverse_order(&tmp);
		1457	d[i] = tmp;
		1458	}
		1459	}
		1460	}
		1461
		1462	/**
		1463	* rivafb_cursor - hardware cursor function
		1464	* @info: pointer to info structure
		1465	* @cursor: pointer to fbcursor structure
		1466	*
		1467	* DESCRIPTION:
		1468	* A cursor function that supports displaying a cursor image via hardware.
		1469	* Within the kernel, copy and invert rops are supported. If exported
		1470	* to user space, only the copy rop will be supported.
		1471	*
		1472	* CALLED FROM
		1473	* framebuffer hook
		1474	*/
		1475	static int rivafb_cursor(struct fb_info info, struct fb_cursor cursor)
		1476	{
		1477	struct riva_par par = (struct riva_par ) info->par;
		1478	u8 data[MAX_CURS * MAX_CURS/8];
		1479	u8 mask[MAX_CURS * MAX_CURS/8];
		1480	u16 fg, bg;
		1481	int i;
		1482
		1483	par->riva.ShowHideCursor(&par->riva, 0);
		1484
		1485	if (cursor->set & FB_CUR_SETPOS) {
		1486	u32 xx, yy, temp;
		1487
		1488	info->cursor.image.dx = cursor->image.dx;
		1489	info->cursor.image.dy = cursor->image.dy;
		1490	yy = cursor->image.dy - info->var.yoffset;
		1491	xx = cursor->image.dx - info->var.xoffset;
		1492	temp = xx & 0xFFFF;
		1493	temp \|= yy << 16;
		1494
		1495	par->riva.PRAMDAC[0x0000300/4] = temp;
		1496	}
		1497
		1498	if (cursor->set & FB_CUR_SETSIZE) {
		1499	info->cursor.image.height = cursor->image.height;
		1500	info->cursor.image.width = cursor->image.width;
		1501	memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
		1502	}
		1503
		1504	if (cursor->set & FB_CUR_SETCMAP) {
		1505	info->cursor.image.bg_color = cursor->image.bg_color;
		1506	info->cursor.image.fg_color = cursor->image.fg_color;
		1507	}
		1508
		1509	if (cursor->set & (FB_CUR_SETSHAPE \| FB_CUR_SETCMAP)) {
		1510	u32 bg_idx = info->cursor.image.bg_color;
		1511	u32 fg_idx = info->cursor.image.fg_color;
		1512	u32 s_pitch = (info->cursor.image.width+7) >> 3;
		1513	u32 d_pitch = MAX_CURS/8;
		1514	u8 dat = (u8 ) cursor->image.data;
		1515	u8 msk = (u8 ) info->cursor.mask;
		1516	u8 src[64];
		1517
		1518	switch (info->cursor.rop) {
		1519	case ROP_XOR:
		1520	for (i = 0; i < s_pitch * info->cursor.image.height; i++)
		1521	src[i] = dat[i] ^ msk[i];
		1522	break;
		1523	case ROP_COPY:
		1524	default:
		1525	for (i = 0; i < s_pitch * info->cursor.image.height; i++)
		1526
		1527	src[i] = dat[i] & msk[i];
		1528	break;
		1529	}
		1530
		1531	move_buf_aligned(info, data, src, d_pitch, s_pitch, info->cursor.image.height);
		1532
		1533	move_buf_aligned(info, mask, msk, d_pitch, s_pitch, info->cursor.image.height);
		1534
		1535	bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) \|
		1536	((info->cmap.green[bg_idx] & 0xf8) << 2) \|
		1537	((info->cmap.blue[bg_idx] & 0xf8) >> 3);
		1538
		1539	fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) \|
		1540	((info->cmap.green[fg_idx] & 0xf8) << 2) \|
		1541	((info->cmap.blue[fg_idx] & 0xf8) >> 3);
		1542
		1543	par->riva.LockUnlock(&par->riva, 0);
		1544
		1545	rivafb_load_cursor_image(par, data, mask, bg, fg,
		1546	info->cursor.image.width,
		1547	info->cursor.image.height);
		1548	}
		1549	if (info->cursor.enable)
		1550	par->riva.ShowHideCursor(&par->riva, 1);
		1551	return 0;
		1552	}
		1553
		1554	static int rivafb_sync(struct fb_info *info)
		1555	{
		1556	struct riva_par par = (struct riva_par )info->par;
		1557
		1558	wait_for_idle(par);
		1559	return 0;
		1560	}
		1561
		1562	/* ------------------------------------------------------------------------- *
		1563	*
		1564	* initialization helper functions
		1565	*
		1566	* ------------------------------------------------------------------------- */
		1567
		1568	/* kernel interface */
		1569	static struct fb_ops riva_fb_ops = {
		1570	.owner = THIS_MODULE,
		1571	.fb_open = rivafb_open,
		1572	.fb_release = rivafb_release,
		1573	.fb_check_var = rivafb_check_var,
		1574	.fb_set_par = rivafb_set_par,
		1575	.fb_setcolreg = rivafb_setcolreg,
		1576	.fb_pan_display = rivafb_pan_display,
		1577	.fb_blank = rivafb_blank,
		1578	.fb_fillrect = rivafb_fillrect,
		1579	.fb_copyarea = rivafb_copyarea,
		1580	.fb_imageblit = rivafb_imageblit,
		1581	.fb_cursor = rivafb_cursor,
		1582	.fb_sync = rivafb_sync,
		1583	};
		1584
		1585	static int __devinit riva_set_fbinfo(struct fb_info *info)
		1586	{
		1587	struct riva_par par = (struct riva_par ) info->par;
		1588	unsigned int cmap_len;
		1589
		1590	info->flags = FBINFO_FLAG_DEFAULT;
		1591	info->var = rivafb_default_var;
		1592	info->fix = rivafb_fix;
		1593	info->fbops = &riva_fb_ops;
		1594	info->pseudo_palette = pseudo_palette;
		1595
		1596	#ifndef MODULE
		1597	if (mode_option)
		1598	fb_find_mode(&info->var, info, mode_option,
		1599	NULL, 0, NULL, 8);
		1600	#endif
		1601	if (par->use_default_var)
		1602	/* We will use the modified default var */
		1603	info->var = rivafb_default_var;
		1604
		1605	cmap_len = riva_get_cmap_len(&info->var);
		1606	fb_alloc_cmap(&info->cmap, cmap_len, 0);
		1607
		1608	info->pixmap.size = 64 * 1024;
		1609	info->pixmap.buf_align = 4;
		1610	info->pixmap.scan_align = 4;
		1611	info->pixmap.flags = FB_PIXMAP_SYSTEM;
		1612	return 0;
		1613	}
		1614
		1615	#ifdef CONFIG_PPC_OF
		1616	static int riva_get_EDID_OF(struct riva_par par, struct pci_dev pd)
		1617	{
		1618	struct device_node *dp;
		1619	unsigned char *pedid = NULL;
		1620
		1621	dp = pci_device_to_OF_node(pd);
		1622	pedid = (unsigned char *)get_property(dp, "EDID,B", 0);
		1623
		1624	if (pedid) {
		1625	par->EDID = pedid;
		1626	return 1;
		1627	} else
		1628	return 0;
		1629	}
		1630	#endif /* CONFIG_PPC_OF */
		1631
		1632	static int riva_dfp_parse_EDID(struct riva_par *par)
		1633	{
		1634	unsigned char *block = par->EDID;
		1635
		1636	if (!block)
		1637	return 0;
		1638
		1639	/* jump to detailed timing block section */
		1640	block += 54;
		1641
		1642	par->clock = (block[0] + (block[1] << 8));
		1643	par->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
		1644	par->hblank = (block[3] + ((block[4] & 0x0f) << 8));
		1645	par->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
		1646	par->vblank = (block[6] + ((block[7] & 0x0f) << 8));
		1647	par->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
		1648	par->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
		1649	par->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
		1650	par->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
		1651	par->interlaced = ((block[17] & 0x80) >> 7);
		1652	par->synct = ((block[17] & 0x18) >> 3);
		1653	par->misc = ((block[17] & 0x06) >> 1);
		1654	par->hAct_high = par->vAct_high = 0;
		1655	if (par->synct == 3) {
		1656	if (par->misc & 2)
		1657	par->hAct_high = 1;
		1658	if (par->misc & 1)
		1659	par->vAct_high = 1;
		1660	}
		1661
		1662	printk(KERN_INFO PFX
		1663	"detected DFP panel size from EDID: %dx%d\n",
		1664	par->panel_xres, par->panel_yres);
		1665	par->got_dfpinfo = 1;
		1666	return 1;
		1667	}
		1668
		1669	static void riva_update_default_var(struct fb_info *info)
		1670	{
		1671	struct fb_var_screeninfo *var = &rivafb_default_var;
		1672	struct riva_par par = (struct riva_par ) info->par;
		1673
		1674	var->xres = par->panel_xres;
		1675	var->yres = par->panel_yres;
		1676	var->xres_virtual = par->panel_xres;
		1677	var->yres_virtual = par->panel_yres;
		1678	var->xoffset = var->yoffset = 0;
		1679	var->bits_per_pixel = 8;
		1680	var->pixclock = 100000000 / par->clock;
		1681	var->left_margin = (par->hblank - par->hOver_plus - par->hSync_width);
		1682	var->right_margin = par->hOver_plus;
		1683	var->upper_margin = (par->vblank - par->vOver_plus - par->vSync_width);
		1684	var->lower_margin = par->vOver_plus;
		1685	var->hsync_len = par->hSync_width;
		1686	var->vsync_len = par->vSync_width;
		1687	var->sync = 0;
		1688
		1689	if (par->synct == 3) {
		1690	if (par->hAct_high)
		1691	var->sync \|= FB_SYNC_HOR_HIGH_ACT;
		1692	if (par->vAct_high)
		1693	var->sync \|= FB_SYNC_VERT_HIGH_ACT;
		1694	}
		1695
		1696	var->vmode = 0;
		1697	if (par->interlaced)
		1698	var->vmode \|= FB_VMODE_INTERLACED;
		1699
		1700	var->accel_flags \|= FB_ACCELF_TEXT;
		1701
		1702	par->use_default_var = 1;
		1703	}
		1704
		1705
		1706	static void riva_get_EDID(struct fb_info info, struct pci_dev pdev)
		1707	{
		1708	#ifdef CONFIG_PPC_OF
		1709	if (!riva_get_EDID_OF(info, pdev))
		1710	printk("rivafb: could not retrieve EDID from OF\n");
		1711	#else
		1712	/* XXX use other methods later */
		1713	#endif
		1714	}
		1715
		1716
		1717	static void riva_get_dfpinfo(struct fb_info *info)
		1718	{
		1719	struct riva_par par = (struct riva_par ) info->par;
		1720
		1721	if (riva_dfp_parse_EDID(par))
		1722	riva_update_default_var(info);
		1723
		1724	/* if user specified flatpanel, we respect that */
		1725	if (par->got_dfpinfo == 1)
		1726	par->FlatPanel = 1;
		1727	}
		1728
		1729	/* ------------------------------------------------------------------------- *
		1730	*
		1731	* PCI bus
		1732	*
		1733	* ------------------------------------------------------------------------- */
		1734
		1735	static int __devinit rivafb_probe(struct pci_dev *pd,
		1736	const struct pci_device_id *ent)
		1737	{
		1738	struct riva_chip_info *rci = &riva_chip_info[ent->driver_data];
		1739	struct riva_par *default_par;
		1740	struct fb_info *info;
		1741
		1742	assert(pd != NULL);
		1743	assert(rci != NULL);
		1744
		1745	info = kmalloc(sizeof(struct fb_info), GFP_KERNEL);
		1746	if (!info)
		1747	goto err_out;
		1748
		1749	default_par = kmalloc(sizeof(struct riva_par), GFP_KERNEL);
		1750	if (!default_par)
		1751	goto err_out_kfree;
		1752
		1753	memset(info, 0, sizeof(struct fb_info));
		1754	memset(default_par, 0, sizeof(struct riva_par));
		1755
		1756	info->pixmap.addr = kmalloc(64 * 1024, GFP_KERNEL);
		1757	if (info->pixmap.addr == NULL)
		1758	goto err_out_kfree1;
		1759	memset(info->pixmap.addr, 0, 64 * 1024);
		1760
		1761	strcat(rivafb_fix.id, rci->name);
		1762	default_par->riva.Architecture = rci->arch_rev;
		1763
		1764	default_par->Chipset = (pd->vendor << 16) \| pd->device;
		1765	printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
		1766
		1767	default_par->FlatPanel = flatpanel;
		1768	if (flatpanel == 1)
		1769	printk(KERN_INFO PFX "flatpanel support enabled\n");
		1770	default_par->forceCRTC = forceCRTC;
		1771
		1772	rivafb_fix.mmio_len = pci_resource_len(pd, 0);
		1773	rivafb_fix.smem_len = pci_resource_len(pd, 1);
		1774
		1775	{
		1776	/* enable IO and mem if not already done */
		1777	unsigned short cmd;
		1778
		1779	pci_read_config_word(pd, PCI_COMMAND, &cmd);
		1780	cmd \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEMORY);
		1781	pci_write_config_word(pd, PCI_COMMAND, cmd);
		1782	}
		1783
		1784	rivafb_fix.mmio_start = pci_resource_start(pd, 0);
		1785	rivafb_fix.smem_start = pci_resource_start(pd, 1);
		1786
		1787	if (!request_mem_region(rivafb_fix.mmio_start,
		1788	rivafb_fix.mmio_len, "rivafb")) {
		1789	printk(KERN_ERR PFX "cannot reserve MMIO region\n");
		1790	goto err_out_kfree2;
		1791	}
		1792
		1793	default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
		1794	rivafb_fix.mmio_len);
		1795	if (!default_par->ctrl_base) {
		1796	printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
		1797	goto err_out_free_base0;
		1798	}
		1799
		1800	info->par = default_par;
		1801
		1802	riva_get_EDID(info, pd);
		1803
		1804	riva_get_dfpinfo(info);
		1805
		1806	switch (default_par->riva.Architecture) {
		1807	case NV_ARCH_03:
		1808	/* Riva128's PRAMIN is in the "framebuffer" space
		1809	* Since these cards were never made with more than 8 megabytes
		1810	* we can safely allocate this separately.
		1811	*/
		1812	if (!request_mem_region(rivafb_fix.smem_start + 0x00C00000,
		1813	0x00008000, "rivafb")) {
		1814	printk(KERN_ERR PFX "cannot reserve PRAMIN region\n");
		1815	goto err_out_iounmap_ctrl;
		1816	}
		1817	default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
		1818	if (!default_par->riva.PRAMIN) {
		1819	printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
		1820	goto err_out_free_nv3_pramin;
		1821	}
		1822	rivafb_fix.accel = FB_ACCEL_NV3;
		1823	break;
		1824	case NV_ARCH_04:
		1825	case NV_ARCH_10:
		1826	case NV_ARCH_20:
		1827	default_par->riva.PCRTC0 = (unsigned *)(default_par->ctrl_base + 0x00600000);
		1828	default_par->riva.PRAMIN = (unsigned *)(default_par->ctrl_base + 0x00710000);
		1829	rivafb_fix.accel = FB_ACCEL_NV4;
		1830	break;
		1831	}
		1832
		1833	riva_common_setup(default_par);
		1834
		1835	if (default_par->riva.Architecture == NV_ARCH_03) {
		1836	default_par->riva.PCRTC = default_par->riva.PCRTC0 = default_par->riva.PGRAPH;
		1837	}
		1838
		1839	rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
		1840	default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
		1841
		1842	if (!request_mem_region(rivafb_fix.smem_start,
		1843	rivafb_fix.smem_len, "rivafb")) {
		1844	printk(KERN_ERR PFX "cannot reserve FB region\n");
		1845	goto err_out_iounmap_nv3_pramin;
		1846	}
		1847
		1848	info->screen_base = ioremap(rivafb_fix.smem_start,
		1849	rivafb_fix.smem_len);
		1850	if (!info->screen_base) {
		1851	printk(KERN_ERR PFX "cannot ioremap FB base\n");
		1852	goto err_out_free_base1;
		1853	}
		1854
		1855	#ifdef CONFIG_MTRR
		1856	if (!nomtrr) {
		1857	default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
		1858	rivafb_fix.smem_len,
		1859	MTRR_TYPE_WRCOMB, 1);
		1860	if (default_par->mtrr.vram < 0) {
		1861	printk(KERN_ERR PFX "unable to setup MTRR\n");
		1862	} else {
		1863	default_par->mtrr.vram_valid = 1;
		1864	/* let there be speed */
		1865	printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
		1866	}
		1867	}
		1868	#endif /* CONFIG_MTRR */
		1869
		1870	if (riva_set_fbinfo(info) < 0) {
		1871	printk(KERN_ERR PFX "error setting initial video mode\n");
		1872	goto err_out_iounmap_fb;
		1873	}
		1874
		1875	if (register_framebuffer(info) < 0) {
		1876	printk(KERN_ERR PFX
		1877	"error registering riva framebuffer\n");
		1878	goto err_out_iounmap_fb;
		1879	}
		1880
		1881	pci_set_drvdata(pd, info);
		1882
		1883	printk(KERN_INFO PFX
475	giacomo	1884	"PCI nVidia NV%x framebuffer ver %s (%s, %dMB @ 0x%x)\n",
472	giacomo	1885	default_par->riva.Architecture,
		1886	RIVAFB_VERSION,
		1887	info->fix.id,
		1888	info->fix.smem_len / (1024 * 1024),
477	giacomo	1889	(int)info->fix.smem_start);
472	giacomo	1890	return 0;
		1891
		1892	err_out_iounmap_fb:
		1893	iounmap(info->screen_base);
		1894	err_out_free_base1:
		1895	release_mem_region(rivafb_fix.smem_start, rivafb_fix.smem_len);
		1896	err_out_iounmap_nv3_pramin:
		1897	if (default_par->riva.Architecture == NV_ARCH_03)
		1898	iounmap((caddr_t)default_par->riva.PRAMIN);
		1899	err_out_free_nv3_pramin:
		1900	if (default_par->riva.Architecture == NV_ARCH_03)
		1901	release_mem_region(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
		1902	err_out_iounmap_ctrl:
		1903	iounmap(default_par->ctrl_base);
		1904	err_out_free_base0:
		1905	release_mem_region(rivafb_fix.mmio_start, rivafb_fix.mmio_len);
		1906	err_out_kfree2:
		1907	kfree(info->pixmap.addr);
		1908	err_out_kfree1:
		1909	kfree(default_par);
		1910	err_out_kfree:
		1911	kfree(info);
		1912	err_out:
		1913	return -ENODEV;
		1914	}
		1915
		1916	static void __exit rivafb_remove(struct pci_dev *pd)
		1917	{
		1918	struct fb_info *info = pci_get_drvdata(pd);
		1919	struct riva_par par = (struct riva_par ) info->par;
		1920
		1921	if (!info)
		1922	return;
		1923
		1924	unregister_framebuffer(info);
		1925	#ifdef CONFIG_MTRR
		1926	if (par->mtrr.vram_valid)
		1927	mtrr_del(par->mtrr.vram, info->fix.smem_start,
		1928	info->fix.smem_len);
		1929	#endif /* CONFIG_MTRR */
		1930
		1931	iounmap(par->ctrl_base);
		1932	iounmap(info->screen_base);
		1933
		1934	release_mem_region(info->fix.mmio_start,
		1935	info->fix.mmio_len);
		1936	release_mem_region(info->fix.smem_start,
		1937	info->fix.smem_len);
		1938
		1939	if (par->riva.Architecture == NV_ARCH_03) {
		1940	iounmap((caddr_t)par->riva.PRAMIN);
		1941	release_mem_region(info->fix.smem_start + 0x00C00000, 0x00008000);
		1942	}
		1943	kfree(info->pixmap.addr);
		1944	kfree(par);
		1945	kfree(info);
		1946	pci_set_drvdata(pd, NULL);
		1947	}
		1948
		1949	/* ------------------------------------------------------------------------- *
		1950	*
		1951	* initialization
		1952	*
		1953	* ------------------------------------------------------------------------- */
		1954
		1955	#ifndef MODULE
		1956	int __init rivafb_setup(char *options)
		1957	{
		1958	char *this_opt;
		1959
		1960	if (!options \|\| !*options)
		1961	return 0;
		1962
		1963	while ((this_opt = strsep(&options, ",")) != NULL) {
		1964	if (!strncmp(this_opt, "forceCRTC", 9)) {
		1965	char *p;
		1966
		1967	p = this_opt + 9;
		1968	if (!p \|\| !(++p)) continue;
		1969	forceCRTC = *p - '0';
		1970	if (forceCRTC < 0 \|\| forceCRTC > 1)
		1971	forceCRTC = -1;
		1972	} else if (!strncmp(this_opt, "flatpanel", 9)) {
		1973	flatpanel = 1;
		1974	#ifdef CONFIG_MTRR
		1975	} else if (!strncmp(this_opt, "nomtrr", 6)) {
		1976	nomtrr = 1;
		1977	#endif
		1978	} else
		1979	mode_option = this_opt;
		1980	}
		1981	return 0;
		1982	}
		1983	#endif /* !MODULE */
		1984
		1985	static struct pci_driver rivafb_driver = {
		1986	.name = "rivafb",
		1987	.id_table = rivafb_pci_tbl,
		1988	.probe = rivafb_probe,
		1989	.remove = __exit_p(rivafb_remove),
		1990	};
		1991
		1992
		1993
		1994	/* ------------------------------------------------------------------------- *
		1995	*
		1996	* modularization
		1997	*
		1998	* ------------------------------------------------------------------------- */
		1999
		2000	int __init rivafb_init(void)
		2001	{
		2002	if (pci_register_driver(&rivafb_driver) > 0)
		2003	return 0;
		2004	pci_unregister_driver(&rivafb_driver);
		2005	return -ENODEV;
		2006	}
		2007
		2008
		2009	#ifdef MODULE
		2010	static void __exit rivafb_exit(void)
		2011	{
		2012	pci_unregister_driver(&rivafb_driver);
		2013	}
		2014
		2015	module_init(rivafb_init);
		2016	module_exit(rivafb_exit);
		2017
		2018	MODULE_PARM(flatpanel, "i");
		2019	MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
		2020	MODULE_PARM(forceCRTC, "i");
		2021	MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
		2022
		2023	#ifdef CONFIG_MTRR
		2024	MODULE_PARM(nomtrr, "i");
		2025	MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
		2026	#endif
		2027	#endif /* MODULE */
		2028
		2029	MODULE_AUTHOR("Ani Joshi, maintainer");
		2030	MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
		2031	MODULE_LICENSE("GPL");

Subversion Repositories shark

(root)/shark/trunk/drivers/fb/riva/fbdev.c - Rev 477