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472 giacomo 1
/***************************************************************************\
2
|*                                                                           *|
3
|*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
4
|*                                                                           *|
5
|*     NOTICE TO USER:   The source code  is copyrighted under  U.S. and     *|
6
|*     international laws.  Users and possessors of this source code are     *|
7
|*     hereby granted a nonexclusive,  royalty-free copyright license to     *|
8
|*     use this code in individual and commercial software.                  *|
9
|*                                                                           *|
10
|*     Any use of this source code must include,  in the user documenta-     *|
11
|*     tion and  internal comments to the code,  notices to the end user     *|
12
|*     as follows:                                                           *|
13
|*                                                                           *|
14
|*       Copyright 1993-1999 NVIDIA, Corporation.  All rights reserved.      *|
15
|*                                                                           *|
16
|*     NVIDIA, CORPORATION MAKES NO REPRESENTATION ABOUT THE SUITABILITY     *|
17
|*     OF  THIS SOURCE  CODE  FOR ANY PURPOSE.  IT IS  PROVIDED  "AS IS"     *|
18
|*     WITHOUT EXPRESS OR IMPLIED WARRANTY OF ANY KIND.  NVIDIA, CORPOR-     *|
19
|*     ATION DISCLAIMS ALL WARRANTIES  WITH REGARD  TO THIS SOURCE CODE,     *|
20
|*     INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGE-     *|
21
|*     MENT,  AND FITNESS  FOR A PARTICULAR PURPOSE.   IN NO EVENT SHALL     *|
22
|*     NVIDIA, CORPORATION  BE LIABLE FOR ANY SPECIAL,  INDIRECT,  INCI-     *|
23
|*     DENTAL, OR CONSEQUENTIAL DAMAGES,  OR ANY DAMAGES  WHATSOEVER RE-     *|
24
|*     SULTING FROM LOSS OF USE,  DATA OR PROFITS,  WHETHER IN AN ACTION     *|
25
|*     OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION,  ARISING OUT OF     *|
26
|*     OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOURCE CODE.     *|
27
|*                                                                           *|
28
|*     U.S. Government  End  Users.   This source code  is a "commercial     *|
29
|*     item,"  as that  term is  defined at  48 C.F.R. 2.101 (OCT 1995),     *|
30
|*     consisting  of "commercial  computer  software"  and  "commercial     *|
31
|*     computer  software  documentation,"  as such  terms  are  used in     *|
32
|*     48 C.F.R. 12.212 (SEPT 1995)  and is provided to the U.S. Govern-     *|
33
|*     ment only as  a commercial end item.   Consistent with  48 C.F.R.     *|
34
|*     12.212 and  48 C.F.R. 227.7202-1 through  227.7202-4 (JUNE 1995),     *|
35
|*     all U.S. Government End Users  acquire the source code  with only     *|
36
|*     those rights set forth herein.                                        *|
37
|*                                                                           *|
38
\***************************************************************************/
39
 
40
/*
41
 * GPL licensing note -- nVidia is allowing a liberal interpretation of
42
 * the documentation restriction above, to merely say that this nVidia's
43
 * copyright and disclaimer should be included with all code derived
44
 * from this source.  -- Jeff Garzik <jgarzik@pobox.com>, 01/Nov/99
45
 */
46
 
47
/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/nv/riva_hw.h,v 1.21 2002/10/14 18:22:46 mvojkovi Exp $ */
48
#ifndef __RIVA_HW_H__
49
#define __RIVA_HW_H__
50
#define RIVA_SW_VERSION 0x00010003
51
 
52
#ifndef Bool
53
typedef int Bool;
54
#endif
55
 
56
#ifndef TRUE
57
#define TRUE 1
58
#endif
59
#ifndef FALSE
60
#define FALSE 0
61
#endif
62
#ifndef NULL
63
#define NULL 0
64
#endif
65
 
66
/*
67
 * Typedefs to force certain sized values.
68
 */
69
typedef unsigned char  U008;
70
typedef unsigned short U016;
71
typedef unsigned int   U032;
72
 
73
/*
74
 * HW access macros.
75
 */
76
#if defined(__powerpc__)
77
#include <asm/io.h>
78
#define NV_WR08(p,i,d)  out_8(p+i, d)
79
#define NV_RD08(p,i)    in_8(p+i)
80
#else
81
#define NV_WR08(p,i,d)  (((U008 *)(p))[i]=(d))
82
#define NV_RD08(p,i)    (((U008 *)(p))[i])
83
#endif
84
#define NV_WR16(p,i,d)  (((U016 *)(p))[(i)/2]=(d))
85
#define NV_RD16(p,i)    (((U016 *)(p))[(i)/2])
86
#define NV_WR32(p,i,d)  (((U032 *)(p))[(i)/4]=(d))
87
#define NV_RD32(p,i)    (((U032 *)(p))[(i)/4])
88
#define VGA_WR08(p,i,d) NV_WR08(p,i,d)
89
#define VGA_RD08(p,i)   NV_RD08(p,i)
90
 
91
/*
92
 * Define supported architectures.
93
 */
94
#define NV_ARCH_03  0x03
95
#define NV_ARCH_04  0x04
96
#define NV_ARCH_10  0x10
97
#define NV_ARCH_20  0x20
98
 
99
/***************************************************************************\
100
*                                                                           *
101
*                             FIFO registers.                               *
102
*                                                                           *
103
\***************************************************************************/
104
 
105
/*
106
 * Raster OPeration. Windows style ROP3.
107
 */
108
typedef volatile struct
109
{
110
    U032 reserved00[4];
111
#ifdef __BIG_ENDIAN
112
    U032 FifoFree;
113
#else
114
    U016 FifoFree;
115
    U016 Nop;
116
#endif
117
    U032 reserved01[0x0BB];
118
    U032 Rop3;
119
} RivaRop;
120
/*
121
 * 8X8 Monochrome pattern.
122
 */
123
typedef volatile struct
124
{
125
    U032 reserved00[4];
126
#ifdef __BIG_ENDIAN
127
    U032 FifoFree;
128
#else
129
    U016 FifoFree;
130
    U016 Nop;
131
#endif
132
    U032 reserved01[0x0BD];
133
    U032 Shape;
134
    U032 reserved03[0x001];
135
    U032 Color0;
136
    U032 Color1;
137
    U032 Monochrome[2];
138
} RivaPattern;
139
/*
140
 * Scissor clip rectangle.
141
 */
142
typedef volatile struct
143
{
144
    U032 reserved00[4];
145
#ifdef __BIG_ENDIAN
146
    U032 FifoFree;
147
#else
148
    U016 FifoFree;
149
    U016 Nop;
150
#endif
151
    U032 reserved01[0x0BB];
152
    U032 TopLeft;
153
    U032 WidthHeight;
154
} RivaClip;
155
/*
156
 * 2D filled rectangle.
157
 */
158
typedef volatile struct
159
{
160
    U032 reserved00[4];
161
#ifdef __BIG_ENDIAN
162
    U032 FifoFree;
163
#else
164
    U016 FifoFree;
165
    U016 Nop[1];
166
#endif
167
    U032 reserved01[0x0BC];
168
    U032 Color;
169
    U032 reserved03[0x03E];
170
    U032 TopLeft;
171
    U032 WidthHeight;
172
} RivaRectangle;
173
/*
174
 * 2D screen-screen BLT.
175
 */
176
typedef volatile struct
177
{
178
    U032 reserved00[4];
179
#ifdef __BIG_ENDIAN
180
    U032 FifoFree;
181
#else
182
    U016 FifoFree;
183
    U016 Nop;
184
#endif
185
    U032 reserved01[0x0BB];
186
    U032 TopLeftSrc;
187
    U032 TopLeftDst;
188
    U032 WidthHeight;
189
} RivaScreenBlt;
190
/*
191
 * 2D pixel BLT.
192
 */
193
typedef volatile struct
194
{
195
    U032 reserved00[4];
196
#ifdef __BIG_ENDIAN
197
    U032 FifoFree;
198
#else
199
    U016 FifoFree;
200
    U016 Nop[1];
201
#endif
202
    U032 reserved01[0x0BC];
203
    U032 TopLeft;
204
    U032 WidthHeight;
205
    U032 WidthHeightIn;
206
    U032 reserved02[0x03C];
207
    U032 Pixels;
208
} RivaPixmap;
209
/*
210
 * Filled rectangle combined with monochrome expand.  Useful for glyphs.
211
 */
212
typedef volatile struct
213
{
214
    U032 reserved00[4];
215
#ifdef __BIG_ENDIAN
216
    U032 FifoFree;
217
#else
218
    U016 FifoFree;
219
    U016 Nop;
220
#endif
221
    U032 reserved01[0x0BB];
222
    U032 reserved03[(0x040)-1];
223
    U032 Color1A;
224
    struct
225
    {
226
        U032 TopLeft;
227
        U032 WidthHeight;
228
    } UnclippedRectangle[64];
229
    U032 reserved04[(0x080)-3];
230
    struct
231
    {
232
        U032 TopLeft;
233
        U032 BottomRight;
234
    } ClipB;
235
    U032 Color1B;
236
    struct
237
    {
238
        U032 TopLeft;
239
        U032 BottomRight;
240
    } ClippedRectangle[64];
241
    U032 reserved05[(0x080)-5];
242
    struct
243
    {
244
        U032 TopLeft;
245
        U032 BottomRight;
246
    } ClipC;
247
    U032 Color1C;
248
    U032 WidthHeightC;
249
    U032 PointC;
250
    U032 MonochromeData1C;
251
    U032 reserved06[(0x080)+121];
252
    struct
253
    {
254
        U032 TopLeft;
255
        U032 BottomRight;
256
    } ClipD;
257
    U032 Color1D;
258
    U032 WidthHeightInD;
259
    U032 WidthHeightOutD;
260
    U032 PointD;
261
    U032 MonochromeData1D;
262
    U032 reserved07[(0x080)+120];
263
    struct
264
    {
265
        U032 TopLeft;
266
        U032 BottomRight;
267
    } ClipE;
268
    U032 Color0E;
269
    U032 Color1E;
270
    U032 WidthHeightInE;
271
    U032 WidthHeightOutE;
272
    U032 PointE;
273
    U032 MonochromeData01E;
274
} RivaBitmap;
275
/*
276
 * 3D textured, Z buffered triangle.
277
 */
278
typedef volatile struct
279
{
280
    U032 reserved00[4];
281
#ifdef __BIG_ENDIAN
282
    U032 FifoFree;
283
#else
284
    U016 FifoFree;
285
    U016 Nop;
286
#endif
287
    U032 reserved01[0x0BC];
288
    U032 TextureOffset;
289
    U032 TextureFormat;
290
    U032 TextureFilter;
291
    U032 FogColor;
292
/* This is a problem on LynxOS */
293
#ifdef Control
294
#undef Control
295
#endif
296
    U032 Control;
297
    U032 AlphaTest;
298
    U032 reserved02[0x339];
299
    U032 FogAndIndex;
300
    U032 Color;
301
    float ScreenX;
302
    float ScreenY;
303
    float ScreenZ;
304
    float EyeM;
305
    float TextureS;
306
    float TextureT;
307
} RivaTexturedTriangle03;
308
typedef volatile struct
309
{
310
    U032 reserved00[4];
311
#ifdef __BIG_ENDIAN
312
    U032 FifoFree;
313
#else
314
    U016 FifoFree;
315
    U016 Nop;
316
#endif
317
    U032 reserved01[0x0BB];
318
    U032 ColorKey;
319
    U032 TextureOffset;
320
    U032 TextureFormat;
321
    U032 TextureFilter;
322
    U032 Blend;
323
/* This is a problem on LynxOS */
324
#ifdef Control
325
#undef Control
326
#endif
327
    U032 Control;
328
    U032 FogColor;
329
    U032 reserved02[0x39];
330
    struct
331
    {
332
        float ScreenX;
333
        float ScreenY;
334
        float ScreenZ;
335
        float EyeM;
336
        U032 Color;
337
        U032 Specular;
338
        float TextureS;
339
        float TextureT;
340
    } Vertex[16];
341
    U032 DrawTriangle3D;
342
} RivaTexturedTriangle05;
343
/*
344
 * 2D line.
345
 */
346
typedef volatile struct
347
{
348
    U032 reserved00[4];
349
#ifdef __BIG_ENDIAN
350
    U032 FifoFree;
351
#else
352
    U016 FifoFree;
353
    U016 Nop[1];
354
#endif
355
    U032 reserved01[0x0BC];
356
    U032 Color;             /* source color               0304-0307*/
357
    U032 Reserved02[0x03e];
358
    struct {                /* start aliased methods in array   0400-    */
359
        U032 point0;        /* y_x S16_S16 in pixels            0-   3*/
360
        U032 point1;        /* y_x S16_S16 in pixels            4-   7*/
361
    } Lin[16];              /* end of aliased methods in array      -047f*/
362
    struct {                /* start aliased methods in array   0480-    */
363
        U032 point0X;       /* in pixels, 0 at left                0-   3*/
364
        U032 point0Y;       /* in pixels, 0 at top                 4-   7*/
365
        U032 point1X;       /* in pixels, 0 at left                8-   b*/
366
        U032 point1Y;       /* in pixels, 0 at top                 c-   f*/
367
    } Lin32[8];             /* end of aliased methods in array      -04ff*/
368
    U032 PolyLin[32];       /* y_x S16_S16 in pixels         0500-057f*/
369
    struct {                /* start aliased methods in array   0580-    */
370
        U032 x;             /* in pixels, 0 at left                0-   3*/
371
        U032 y;             /* in pixels, 0 at top                 4-   7*/
372
    } PolyLin32[16];        /* end of aliased methods in array      -05ff*/
373
    struct {                /* start aliased methods in array   0600-    */
374
        U032 color;         /* source color                     0-   3*/
375
        U032 point;         /* y_x S16_S16 in pixels            4-   7*/
376
    } ColorPolyLin[16];     /* end of aliased methods in array      -067f*/
377
} RivaLine;
378
/*
379
 * 2D/3D surfaces
380
 */
381
typedef volatile struct
382
{
383
    U032 reserved00[4];
384
#ifdef __BIG_ENDIAN
385
    U032 FifoFree;
386
#else
387
    U016 FifoFree;
388
    U016 Nop;
389
#endif
390
    U032 reserved01[0x0BE];
391
    U032 Offset;
392
} RivaSurface;
393
typedef volatile struct
394
{
395
    U032 reserved00[4];
396
#ifdef __BIG_ENDIAN
397
    U032 FifoFree;
398
#else
399
    U016 FifoFree;
400
    U016 Nop;
401
#endif
402
    U032 reserved01[0x0BD];
403
    U032 Pitch;
404
    U032 RenderBufferOffset;
405
    U032 ZBufferOffset;
406
} RivaSurface3D;
407
 
408
/***************************************************************************\
409
*                                                                           *
410
*                        Virtualized RIVA H/W interface.                    *
411
*                                                                           *
412
\***************************************************************************/
413
 
414
#define FP_ENABLE  1
415
#define FP_DITHER  2
416
 
417
struct _riva_hw_inst;
418
struct _riva_hw_state;
419
/*
420
 * Virtialized chip interface. Makes RIVA 128 and TNT look alike.
421
 */
422
typedef struct _riva_hw_inst
423
{
424
    /*
425
     * Chip specific settings.
426
     */
427
    U032 Architecture;
428
    U032 Version;
429
    U032 Chipset;
430
    U032 CrystalFreqKHz;
431
    U032 RamAmountKBytes;
432
    U032 MaxVClockFreqKHz;
433
    U032 RamBandwidthKBytesPerSec;
434
    U032 EnableIRQ;
435
    U032 IO;
436
    U032 VBlankBit;
437
    U032 FifoFreeCount;
438
    U032 FifoEmptyCount;
439
    U032 CursorStart;
440
    U032 flatPanel;
441
    Bool twoHeads;
442
    /*
443
     * Non-FIFO registers.
444
     */
445
    volatile U032 *PCRTC0;
446
    volatile U032 *PCRTC;
447
    volatile U032 *PRAMDAC0;
448
    volatile U032 *PFB;
449
    volatile U032 *PFIFO;
450
    volatile U032 *PGRAPH;
451
    volatile U032 *PEXTDEV;
452
    volatile U032 *PTIMER;
453
    volatile U032 *PMC;
454
    volatile U032 *PRAMIN;
455
    volatile U032 *FIFO;
456
    volatile U032 *CURSOR;
457
    volatile U008 *PCIO0;
458
    volatile U008 *PCIO;
459
    volatile U008 *PVIO;
460
    volatile U008 *PDIO0;
461
    volatile U008 *PDIO;
462
    volatile U032 *PRAMDAC;
463
    /*
464
     * Common chip functions.
465
     */
466
    int  (*Busy)(struct _riva_hw_inst *);
467
    void (*CalcStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *,int,int,int,int,int);
468
    void (*LoadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
469
    void (*UnloadStateExt)(struct _riva_hw_inst *,struct _riva_hw_state *);
470
    void (*SetStartAddress)(struct _riva_hw_inst *,U032);
471
    void (*SetSurfaces2D)(struct _riva_hw_inst *,U032,U032);
472
    void (*SetSurfaces3D)(struct _riva_hw_inst *,U032,U032);
473
    int  (*ShowHideCursor)(struct _riva_hw_inst *,int);
474
    void (*LockUnlock)(struct _riva_hw_inst *, int);
475
    /*
476
     * Current extended mode settings.
477
     */
478
    struct _riva_hw_state *CurrentState;
479
    /*
480
     * FIFO registers.
481
     */
482
    RivaRop                 *Rop;
483
    RivaPattern             *Patt;
484
    RivaClip                *Clip;
485
    RivaPixmap              *Pixmap;
486
    RivaScreenBlt           *Blt;
487
    RivaBitmap              *Bitmap;
488
    RivaLine                *Line;
489
    RivaTexturedTriangle03  *Tri03;
490
    RivaTexturedTriangle05  *Tri05;
491
} RIVA_HW_INST;
492
/*
493
 * Extended mode state information.
494
 */
495
typedef struct _riva_hw_state
496
{
497
    U032 bpp;
498
    U032 width;
499
    U032 height;
500
    U032 interlace;
501
    U032 repaint0;
502
    U032 repaint1;
503
    U032 screen;
504
    U032 scale;
505
    U032 dither;
506
    U032 extra;
507
    U032 pixel;
508
    U032 horiz;
509
    U032 arbitration0;
510
    U032 arbitration1;
511
    U032 vpll;
512
    U032 vpll2;
513
    U032 pllsel;
514
    U032 general;
515
    U032 crtcOwner;
516
    U032 head;
517
    U032 head2;
518
    U032 config;
519
    U032 cursorConfig; 
520
    U032 cursor0;
521
    U032 cursor1;
522
    U032 cursor2;
523
    U032 offset0;
524
    U032 offset1;
525
    U032 offset2;
526
    U032 offset3;
527
    U032 pitch0;
528
    U032 pitch1;
529
    U032 pitch2;
530
    U032 pitch3;
531
} RIVA_HW_STATE;
532
/*
533
 * External routines.
534
 */
535
int RivaGetConfig(RIVA_HW_INST *, unsigned int);
536
/*
537
 * FIFO Free Count. Should attempt to yield processor if RIVA is busy.
538
 */
539
 
540
#define RIVA_FIFO_FREE(hwinst,hwptr,cnt)                            \
541
{                                                                   \
542
    while ((hwinst).FifoFreeCount < (cnt))                          \
543
        (hwinst).FifoFreeCount = (hwinst).hwptr->FifoFree >> 2;     \
544
    (hwinst).FifoFreeCount -= (cnt);                                \
545
}
546
#endif /* __RIVA_HW_H__ */
547