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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1063 | tullio | 1 | |
| 2 | /* |
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| 3 | * This program is free software; you can redistribute it and/or modify |
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| 4 | * it under the terms of the GNU General Public License as published by |
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| 5 | * the Free Software Foundation; either version 2 of the License, or |
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| 6 | * (at your option) any later version. |
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| 7 | * |
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| 8 | * This program is distributed in the hope that it will be useful, |
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| 9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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| 10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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| 11 | * GNU General Public License for more details. |
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| 12 | * |
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| 13 | * You should have received a copy of the GNU General Public License |
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| 14 | * along with this program; if not, write to the Free Software |
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| 15 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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| 16 | * |
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| 17 | */ |
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| 18 | |||
| 2 | pj | 19 | #include <ll/i386/hw-data.h> |
| 20 | #include <ll/i386/mem.h> |
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| 21 | /* |
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| 22 | #include <ll/i386/x-dos.h> |
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| 23 | #include <ll/i386/x-dosmem.h> |
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| 24 | */ |
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| 25 | #include <ll/i386/cons.h> |
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| 26 | #include <ll/sys/ll/ll-func.h> |
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| 27 | |||
| 28 | #include "s3.h" |
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| 29 | #include "chips.h" |
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| 30 | |||
| 31 | |||
| 32 | enum { |
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| 33 | S3_911, S3_924, S3_801, S3_805, S3_928, S3_864, S3_964, S3_TRIO32, |
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| 34 | S3_TRIO64, S3_866, S3_868, S3_968, S3_765, S3_VIRGE, S3_VIRGE_VX, |
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| 35 | S3_UNKNOWN |
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| 36 | }; |
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| 37 | |||
| 38 | static const char *s3_chipname[] = |
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| 39 | {"911", "924", "801", "805", "928", |
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| 40 | "864", "964", "Trio32", "Trio64", |
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| 41 | "866", "868", "968", "Trio64V+", |
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| 42 | "ViRGE", "ViRGE VX", |
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| 43 | "Unknown S3 chip"}; |
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| 44 | |||
| 45 | |||
| 46 | |||
| 47 | |||
| 48 | #define CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ |
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| 49 | #define CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ |
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| 50 | |||
| 51 | /* flags used by this driver */ |
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| 52 | #define S3_LOCALBUS 0x01 |
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| 53 | #define S3_CLUT8_8 0x02 |
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| 54 | #define S3_OLD_STEPPING 0x04 |
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| 55 | |||
| 56 | DWORD s3_linear_addr = 0; |
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| 57 | |||
| 58 | int s3_chiptype; |
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| 59 | int s3_flags; |
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| 60 | int s3_memory; |
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| 61 | |||
| 62 | /* S3 specific Graphic drivers... */ |
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| 63 | |||
| 64 | static void s3_lock(void) |
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| 65 | { |
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| 66 | outp(0x3d4, 0x39); |
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| 67 | outp(0x3d5, 0x00); |
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| 68 | outp(0x3d4, 0x38); |
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| 69 | outp(0x3d5, 0x00); |
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| 70 | } |
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| 71 | |||
| 72 | static void s3_lock_enh(void) |
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| 73 | { |
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| 74 | BYTE tmp; |
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| 75 | |||
| 76 | if (s3_chiptype > S3_911) { |
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| 77 | outp(0x3d4, 40); |
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| 78 | tmp = inp(0x3d5); |
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| 79 | outp(0x3d5, tmp & ~0x01); |
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| 80 | } |
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| 81 | s3_lock(); |
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| 82 | } |
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| 83 | |||
| 84 | |||
| 85 | static void s3_unlock(void) |
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| 86 | { |
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| 87 | outp(0x3d4, 0x38); |
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| 88 | outp(0x3d5, 0x48); |
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| 89 | outp(0x3d4, 0x39); |
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| 90 | outp(0x3d5, 0xA5); |
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| 91 | } |
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| 92 | |||
| 93 | static void s3_unlock_enh(void) |
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| 94 | { |
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| 95 | BYTE tmp; |
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| 96 | |||
| 97 | s3_unlock(); |
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| 98 | if (s3_chiptype > S3_911) { |
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| 99 | outp(0x3d4, 0x40); |
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| 100 | tmp = inp(0x3d5); |
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| 101 | outp(0x3d5, tmp | 0x01); |
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| 102 | } |
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| 103 | } |
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| 104 | |||
| 105 | static int s3_init(int par1, int par2) |
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| 106 | { |
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| 107 | int id, rev; |
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| 108 | BYTE config; |
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| 109 | |||
| 110 | s3_unlock(); |
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| 111 | |||
| 112 | s3_flags = 0; /* initialize */ |
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| 113 | outp(0x3d4, 0x30); /* Get chip id. */ |
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| 114 | id = inp(0x3d5); |
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| 115 | rev = id & 0x0F; |
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| 116 | if (id >= 0xE0) { |
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| 117 | outp(0x3d4, 0x2D); |
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| 118 | id = inp(0x3d5) << 8; |
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| 119 | outp(0x3d4, 0x2E); |
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| 120 | id |= inp(0x3d5); |
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| 121 | outp(0x3d4, 0x2F); |
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| 122 | rev = inp(0x3d5); |
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| 123 | } |
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| 124 | s3_chiptype = -1; |
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| 125 | outp(0x3d4, 0x36); /* Get config info */ |
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| 126 | config = inp(0x3d5); |
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| 127 | switch (id & 0xf0) { |
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| 128 | case 0x80: |
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| 129 | if (rev == 1) { |
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| 130 | s3_chiptype = S3_911; |
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| 131 | break; |
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| 132 | } |
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| 133 | if (rev == 2) { |
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| 134 | s3_chiptype = S3_924; |
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| 135 | break; |
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| 136 | } |
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| 137 | break; |
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| 138 | case 0xa0: |
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| 139 | switch (config & 0x03) { |
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| 140 | case 0x00: |
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| 141 | case 0x01: |
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| 142 | /* EISA or VLB - 805 */ |
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| 143 | s3_chiptype = S3_805; |
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| 144 | /* ARI: Test stepping: 0:B, 1:unknown, 2,3,4:C, 8:I, >=5:D */ |
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| 145 | if ((rev & 0x0F) < 2) |
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| 146 | s3_flags |= S3_OLD_STEPPING; /* can't handle 1152 width */ |
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| 147 | break; |
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| 148 | case 0x03: |
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| 149 | /* ISA - 801 */ |
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| 150 | s3_chiptype = S3_801; |
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| 151 | /* Stepping same as 805, just ISA */ |
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| 152 | if ((rev & 0x0F) < 2) |
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| 153 | s3_flags |= S3_OLD_STEPPING; /* can't handle 1152 width */ |
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| 154 | break; |
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| 155 | } |
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| 156 | break; |
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| 157 | case 0x90: |
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| 158 | s3_chiptype = S3_928; |
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| 159 | if ((rev & 0x0F) < 4) /* ARI: Stepping D or below */ |
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| 160 | s3_flags |= S3_OLD_STEPPING; /* can't handle 1152 width */ |
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| 161 | break; |
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| 162 | case 0xB0: |
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| 163 | /* 928P */ |
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| 164 | s3_chiptype = S3_928; |
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| 165 | break; |
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| 166 | case 0xC0: |
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| 167 | s3_chiptype = S3_864; |
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| 168 | break; |
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| 169 | case 0xD0: |
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| 170 | s3_chiptype = S3_964; |
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| 171 | break; |
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| 172 | default: |
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| 173 | switch (id) { |
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| 174 | case 0x8811: |
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| 175 | switch (id & 0xFFF0) { |
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| 176 | case 0x10E0: |
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| 177 | s3_chiptype = S3_TRIO32; |
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| 178 | break; |
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| 179 | case 0x01E0: /* S3Trio64V2/DX ... any others? */ |
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| 180 | case 0x11E0: |
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| 181 | if (rev & 0x0400) |
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| 182 | s3_chiptype = S3_765; |
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| 183 | else |
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| 184 | s3_chiptype = S3_TRIO64; |
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| 185 | break; |
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| 186 | } |
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| 187 | case 0x883d: /*ME*/ |
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| 188 | s3_chiptype = S3_VIRGE_VX; |
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| 189 | break; |
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| 190 | case 0x5631: /* ViRGE ID */ |
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| 191 | s3_chiptype = S3_VIRGE; |
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| 192 | break; |
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| 193 | case 0x8901: /*ME*/ |
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| 194 | s3_chiptype = S3_765; |
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| 195 | break; |
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| 196 | case 0x80E0: |
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| 197 | s3_chiptype = S3_866; /* Not Ok... */ |
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| 198 | break; |
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| 199 | case 0x8880: |
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| 200 | s3_chiptype = S3_868; |
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| 201 | break; |
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| 202 | case 0x88f0: /* XXXX From data book; XF86 says 0xB0E0? */ |
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| 203 | s3_chiptype = S3_968; |
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| 204 | break; |
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| 205 | default: |
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| 206 | s3_chiptype = S3_UNKNOWN; |
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| 207 | break; |
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| 208 | } |
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| 209 | } |
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| 210 | /* s3_lock();*/ |
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| 211 | if (s3_chiptype == -1) { |
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| 212 | return -1; |
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| 213 | } |
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| 214 | if (s3_chiptype == S3_UNKNOWN) { |
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| 215 | cprintf("svgalib: S3: Unknown chip id %02x\n", id); |
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| 216 | return -1; |
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| 217 | } |
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| 218 | if (s3_chiptype <= S3_924) { |
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| 219 | if ((config & 0x20) != 0) { |
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| 220 | s3_memory = 512; |
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| 221 | } else { |
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| 222 | s3_memory = 1024; |
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| 223 | } |
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| 224 | } else { |
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| 225 | if (s3_chiptype == S3_VIRGE_VX) { |
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| 226 | BYTE config2; |
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| 227 | int m1; |
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| 228 | |||
| 229 | outp(0x3d4, 0x37); |
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| 230 | config2 = inp(0x3d5); |
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| 231 | switch ((config & 0x60) >> 5) { |
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| 232 | case 0: |
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| 233 | s3_memory = 2 * 1024; |
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| 234 | break; |
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| 235 | case 1: |
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| 236 | s3_memory = 4 * 1024; |
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| 237 | break; |
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| 238 | case 2: |
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| 239 | s3_memory = 6 * 1024; |
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| 240 | break; |
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| 241 | case 3: |
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| 242 | s3_memory = 8 * 1024; |
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| 243 | break; |
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| 244 | } |
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| 245 | m1 = 0; |
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| 246 | switch ((config2 & 0x60) >> 5) { |
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| 247 | case 0: |
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| 248 | m1 = 4 * 1024; |
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| 249 | break; |
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| 250 | case 2: |
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| 251 | m1 = 2 * 1024; |
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| 252 | break; |
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| 253 | } |
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| 254 | cprintf("M1: %d M2: %d\n", s3_memory, m1); |
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| 255 | s3_memory -= m1; |
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| 256 | } else { |
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| 257 | /* look at bits 5, 6 and 7 */ |
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| 258 | switch ((config & 0xE0) >> 5) { |
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| 259 | case 0: |
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| 260 | s3_memory = 4096; |
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| 261 | break; |
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| 262 | case 2: |
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| 263 | s3_memory = 3072; |
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| 264 | break; |
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| 265 | case 3: |
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| 266 | s3_memory = 8192; |
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| 267 | break; |
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| 268 | case 4: |
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| 269 | s3_memory = 2048; |
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| 270 | break; |
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| 271 | case 5: |
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| 272 | s3_memory = 6144; |
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| 273 | break; |
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| 274 | case 6: |
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| 275 | s3_memory = 1024; |
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| 276 | break; |
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| 277 | case 7: |
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| 278 | s3_memory = 512; |
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| 279 | break; /* Trio32 */ |
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| 280 | } |
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| 281 | } |
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| 282 | } |
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| 283 | if ((config & 0x03) < 3) /* XXXX 928P is ignored */ |
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| 284 | s3_flags |= S3_LOCALBUS; |
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| 285 | |||
| 286 | cprintf("svgalib: Using S3 driver (%s, %dK).\n", s3_chipname[s3_chiptype], |
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| 287 | s3_memory); |
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| 288 | if (s3_flags & S3_OLD_STEPPING) |
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| 289 | cprintf("svgalib: Chip revision cannot handle modes with width 1152.\n"); |
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| 290 | if (s3_chiptype > S3_864) { |
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| 291 | cprintf("svgalib: s3: chipsets newer than S3-864 is not supported well yet.\n"); |
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| 292 | } |
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| 293 | |||
| 294 | #ifdef DAC |
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| 295 | cardspecs = malloc(sizeof(CardSpecs)); |
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| 296 | cardspecs->videoMemory = s3_memory; |
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| 297 | cardspecs->nClocks = 0; |
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| 298 | /* cardspecs->maxHorizontalCrtc = 2040; SL: kills 800x600x32k and above */ |
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| 299 | cardspecs->maxHorizontalCrtc = 4088; |
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| 300 | cardspecs->flags = INTERLACE_DIVIDE_VERT; |
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| 301 | |||
| 302 | /* Process S3-specific config file options. */ |
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| 303 | __svgalib_read_options(s3_config_options, s3_process_option); |
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| 304 | |||
| 305 | #ifdef INCLUDE_S3_TRIO64_DAC |
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| 306 | if ((s3_chiptype == S3_TRIO64 || s3_chiptype == S3_765) && dac_used == NULL) dac_used = &__svgalib_Trio64_methods; |
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| 307 | #endif |
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| 308 | |||
| 309 | if (dac_used == NULL) |
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| 310 | dac_used = __svgalib_probeDacs(dacs_to_probe); |
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| 311 | else |
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| 312 | dac_used->initialize(); |
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| 313 | |||
| 314 | |||
| 315 | if (dac_used == NULL) { |
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| 316 | /* Not supported. */ |
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| 317 | cprintf("svgalib: s3: Assuming normal VGA DAC.\n"); |
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| 318 | |||
| 319 | #ifdef INCLUDE_NORMAL_DAC |
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| 320 | dac_used = &__svgalib_normal_dac_methods; |
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| 321 | dac_used->initialize(); |
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| 322 | #else |
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| 323 | cprintf("svgalib: Alas, normal VGA DAC support is not compiled in, goodbye.\n"); |
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| 324 | return 1; |
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| 325 | #endif |
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| 326 | } |
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| 327 | if (clk_used) |
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| 328 | clk_used->initialize(cardspecs, dac_used); |
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| 329 | |||
| 330 | dac_used->qualifyCardSpecs(cardspecs, dac_speed); |
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| 331 | |||
| 332 | /* Initialize standard clocks for unknown DAC. */ |
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| 333 | if ((!(cardspecs->flags & CLOCK_PROGRAMMABLE)) |
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| 334 | && cardspecs->nClocks == 0) { |
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| 335 | /* |
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| 336 | * Almost all cards have 25 and 28 MHz on VGA clocks 0 and 1, |
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| 337 | * so use these for an unknown DAC, yielding 640x480x256. |
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| 338 | */ |
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| 339 | cardspecs->nClocks = 2; |
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| 340 | cardspecs->clocks = malloc(sizeof(int) * 2); |
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| 341 | cardspecs->clocks[0] = 25175; |
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| 342 | |||
| 343 | cardspecs->clocks[1] = 28322; |
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| 344 | } |
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| 345 | /* Limit pixel clocks according to chip specifications. */ |
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| 346 | if (s3_chiptype == S3_864 || s3_chiptype == S3_868) { |
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| 347 | /* Limit max clocks according to 95 MHz DCLK spec. */ |
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| 348 | /* SL: might just be 95000 for 4/8bpp since no pixmux'ing */ |
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| 349 | LIMIT(cardspecs->maxPixelClock4bpp, 95000 * 2); |
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| 350 | LIMIT(cardspecs->maxPixelClock8bpp, 95000 * 2); |
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| 351 | LIMIT(cardspecs->maxPixelClock16bpp, 95000); |
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| 352 | /* see explanation below */ |
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| 353 | LIMIT(cardspecs->maxPixelClock24bpp, 36000); |
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| 354 | /* |
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| 355 | * The official 32bpp limit is 47500, but we allow |
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| 356 | * 50 MHz for VESA 800x600 timing (actually the |
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| 357 | * S3-864 doesn't have the horizontal timing range |
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| 358 | * to run unmodified VESA 800x600 72 Hz timings). |
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| 359 | */ |
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| 360 | LIMIT(cardspecs->maxPixelClock32bpp, 50000); |
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| 361 | } |
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| 362 | __svgalib_driverspecs = &__svgalib_s3_driverspecs; |
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| 363 | #endif /* DAC & c. */ |
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| 364 | s3_lock(); |
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| 365 | return 0; |
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| 366 | } |
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| 367 | |||
| 368 | int s3_test(void) |
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| 369 | { |
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| 370 | BYTE new_val1, new_val2; |
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| 371 | |||
| 372 | s3_unlock(); |
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| 373 | outp(0x3d4, 0x47); |
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| 374 | outp(0x3d5, 0xff); |
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| 375 | new_val1 = inp(0x3d5); |
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| 376 | outp(0x3d5, 0x00); |
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| 377 | new_val2 = inp(0x3d5); |
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| 378 | s3_lock(); |
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| 379 | |||
| 380 | if ((new_val1 == 0xff) && (new_val2 == 0x00)) { |
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| 381 | if (s3_init(0, 0)) /* type not OK */ |
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| 382 | return 0; |
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| 383 | return 1; |
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| 384 | } |
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| 385 | cprintf("V1: %x V2: %x\n", new_val1, new_val2); |
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| 386 | return 0; |
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| 387 | } |
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| 388 | |||
| 389 | DWORD s3_getmem(void) |
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| 390 | { |
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| 391 | return s3_memory * 1024; |
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| 392 | } |
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| 393 | |||
| 394 | void s3_showinfo(void) |
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| 395 | { |
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| 396 | cprintf("\t Using S3 driver (%s, %dK).\n", s3_chipname[s3_chiptype], |
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| 397 | s3_memory); |
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| 398 | if (s3_flags & S3_OLD_STEPPING) { |
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| 399 | cprintf("\t Chip revision cannot handle modes with width 1152.\n"); |
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| 400 | } |
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| 401 | if (s3_chiptype > S3_864) { |
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| 402 | cprintf("\t s3: chipsets newer than S3-864 is not supported well yet.\n"); |
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| 403 | } |
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| 404 | cprintf ("\t s3: Frame Linear Buffer @ %lx (%ld)\n", s3_linear_addr, s3_linear_addr); |
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| 405 | } |
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| 406 | |||
| 407 | /* These are important!!! */ |
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| 408 | void s3_setpage(int page) |
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| 409 | { |
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| 410 | s3_unlock(); |
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| 411 | outp(0x3d4, 0x35); |
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| 412 | outp(0x3d5, (inp(0x3d5) & 0xF0) | (page & 0x0F)); |
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| 413 | /* is it important??? |
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| 414 | if (s3_chiptype >= S3_801) { |
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| 415 | outb(0x3d4, 0x51); |
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| 416 | outb(0x3d5, (inb(0x3d5) & ~0x0C) | ((page & 0x30) >> 2)); |
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| 417 | } |
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| 418 | */ |
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| 419 | inp(0x3d5); /* ARI: Ferraro says: required for first generation 911 only */ |
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| 420 | s3_lock(); |
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| 421 | } |
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| 422 | |||
| 423 | void s3_setpage864(int page) |
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| 424 | { |
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| 425 | /* Let's try this... */ |
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| 426 | s3_unlock(); |
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| 427 | /* "Linear" mode banking. */ |
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| 428 | outp(0x3d4, 0x6A); |
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| 429 | outp(0x3d5, (inp(0x3d5) & ~0x3F) | page); |
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| 430 | s3_lock(); |
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| 431 | } |
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| 432 | |||
| 433 | void s3_linear(DWORD l_a) |
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| 434 | { |
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| 435 | BYTE r59, r5A, tmp, linopt; |
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| 436 | BYTE i3; |
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| 437 | |||
| 438 | s3_setpage(0); |
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| 439 | r59 = l_a >> 24; |
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| 440 | r5A = (l_a >> 16) & 0x08; |
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| 441 | if (s3_memory <= 1024) { |
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| 442 | linopt = 0x15; |
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| 443 | } else if (s3_memory <= 2048) { |
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| 444 | linopt = 0x16; |
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| 445 | } else { |
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| 446 | linopt = 0x17; |
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| 447 | } |
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| 448 | |||
| 449 | s3_unlock(); |
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| 450 | |||
| 451 | /*#ifdef OLD*/ |
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| 452 | /* 4 805... */ |
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| 453 | outp(0x3d4, 0x40); |
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| 454 | i3 = inp(0x3d5); |
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| 455 | i3 = (i3 & 0xf6) | 0x0a;/* enable fast write buffer and disable |
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| 456 | * 8514/a mode */ |
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| 457 | outp(0x3d4, i3); |
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| 458 | /* DISABLE_MMIO;*/ |
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| 459 | { unsigned char tmp; |
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| 460 | outp(0x3d4, 0x53); |
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| 461 | tmp = inp(0x3d5); |
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| 462 | outp(0x3d5, tmp & 0xEF); } |
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| 463 | /* outb (vgaCRReg, s3LinApOpt | s3SAM256); |
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| 464 | if (!S3_x64_SERIES(s3ChipId)) { |
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| 465 | outb (vgaCRIndex, 0x54); |
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| 466 | outb (vgaCRReg, (s3Port54 + 07)); |
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| 467 | } |
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| 468 | */ |
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| 469 | /*#endif*/ |
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| 470 | |||
| 471 | outp(0x3d4, 0x58); |
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| 472 | tmp = inp(0x3d5) /*& 0x80*/; |
||
| 473 | /* outp(0x3d5, linopt & ~0x04 | tmp);*/ |
||
| 474 | outp(0x3d5, linopt | tmp); |
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| 475 | |||
| 476 | outp(0x3d4, 0x59); |
||
| 477 | outp(0x3d5, r59); |
||
| 478 | outp(0x3d4, 0x5A); |
||
| 479 | outp(0x3d5, r5A); |
||
| 480 | |||
| 481 | s3_lock(); |
||
| 482 | } |