Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
420 | giacomo | 1 | /* |
2 | * SMBus 2.0 driver for AMD-8111 IO-Hub. |
||
3 | * |
||
4 | * Copyright (c) 2002 Vojtech Pavlik |
||
5 | * |
||
6 | * This program is free software; you can redistribute it and/or modify |
||
7 | * it under the terms of the GNU General Public License as published by |
||
8 | * the Free Software Foundation version 2. |
||
9 | */ |
||
10 | |||
11 | #include <linux/module.h> |
||
12 | #include <linux/pci.h> |
||
13 | #include <linux/kernel.h> |
||
14 | #include <linux/stddef.h> |
||
15 | #include <linux/sched.h> |
||
16 | #include <linux/ioport.h> |
||
17 | #include <linux/init.h> |
||
18 | #include <linux/i2c.h> |
||
19 | #include <linux/delay.h> |
||
20 | #include <asm/io.h> |
||
21 | |||
22 | MODULE_LICENSE("GPL"); |
||
23 | MODULE_AUTHOR ("Vojtech Pavlik <vojtech@suse.cz>"); |
||
24 | MODULE_DESCRIPTION("AMD8111 SMBus 2.0 driver"); |
||
25 | |||
26 | struct amd_smbus { |
||
27 | struct pci_dev *dev; |
||
28 | struct i2c_adapter adapter; |
||
29 | int base; |
||
30 | int size; |
||
31 | }; |
||
32 | |||
33 | /* |
||
34 | * AMD PCI control registers definitions. |
||
35 | */ |
||
36 | |||
37 | #define AMD_PCI_MISC 0x48 |
||
38 | |||
39 | #define AMD_PCI_MISC_SCI 0x04 /* deliver SCI */ |
||
40 | #define AMD_PCI_MISC_INT 0x02 /* deliver PCI IRQ */ |
||
41 | #define AMD_PCI_MISC_SPEEDUP 0x01 /* 16x clock speedup */ |
||
42 | |||
43 | /* |
||
44 | * ACPI 2.0 chapter 13 PCI interface definitions. |
||
45 | */ |
||
46 | |||
47 | #define AMD_EC_DATA 0x00 /* data register */ |
||
48 | #define AMD_EC_SC 0x04 /* status of controller */ |
||
49 | #define AMD_EC_CMD 0x04 /* command register */ |
||
50 | #define AMD_EC_ICR 0x08 /* interrupt control register */ |
||
51 | |||
52 | #define AMD_EC_SC_SMI 0x04 /* smi event pending */ |
||
53 | #define AMD_EC_SC_SCI 0x02 /* sci event pending */ |
||
54 | #define AMD_EC_SC_BURST 0x01 /* burst mode enabled */ |
||
55 | #define AMD_EC_SC_CMD 0x08 /* byte in data reg is command */ |
||
56 | #define AMD_EC_SC_IBF 0x02 /* data ready for embedded controller */ |
||
57 | #define AMD_EC_SC_OBF 0x01 /* data ready for host */ |
||
58 | |||
59 | #define AMD_EC_CMD_RD 0x80 /* read EC */ |
||
60 | #define AMD_EC_CMD_WR 0x81 /* write EC */ |
||
61 | #define AMD_EC_CMD_BE 0x82 /* enable burst mode */ |
||
62 | #define AMD_EC_CMD_BD 0x83 /* disable burst mode */ |
||
63 | #define AMD_EC_CMD_QR 0x84 /* query EC */ |
||
64 | |||
65 | /* |
||
66 | * ACPI 2.0 chapter 13 access of registers of the EC |
||
67 | */ |
||
68 | |||
69 | unsigned int amd_ec_wait_write(struct amd_smbus *smbus) |
||
70 | { |
||
71 | int timeout = 500; |
||
72 | |||
73 | while (timeout-- && (inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_IBF)) |
||
74 | udelay(1); |
||
75 | |||
76 | if (!timeout) { |
||
77 | dev_warn(&smbus->dev->dev, "Timeout while waiting for IBF to clear\n"); |
||
78 | return -1; |
||
79 | } |
||
80 | |||
81 | return 0; |
||
82 | } |
||
83 | |||
84 | unsigned int amd_ec_wait_read(struct amd_smbus *smbus) |
||
85 | { |
||
86 | int timeout = 500; |
||
87 | |||
88 | while (timeout-- && (~inb(smbus->base + AMD_EC_SC) & AMD_EC_SC_OBF)) |
||
89 | udelay(1); |
||
90 | |||
91 | if (!timeout) { |
||
92 | dev_warn(&smbus->dev->dev, "Timeout while waiting for OBF to set\n"); |
||
93 | return -1; |
||
94 | } |
||
95 | |||
96 | return 0; |
||
97 | } |
||
98 | |||
99 | unsigned int amd_ec_read(struct amd_smbus *smbus, unsigned char address, unsigned char *data) |
||
100 | { |
||
101 | if (amd_ec_wait_write(smbus)) |
||
102 | return -1; |
||
103 | outb(AMD_EC_CMD_RD, smbus->base + AMD_EC_CMD); |
||
104 | |||
105 | if (amd_ec_wait_write(smbus)) |
||
106 | return -1; |
||
107 | outb(address, smbus->base + AMD_EC_DATA); |
||
108 | |||
109 | if (amd_ec_wait_read(smbus)) |
||
110 | return -1; |
||
111 | *data = inb(smbus->base + AMD_EC_DATA); |
||
112 | |||
113 | return 0; |
||
114 | } |
||
115 | |||
116 | unsigned int amd_ec_write(struct amd_smbus *smbus, unsigned char address, unsigned char data) |
||
117 | { |
||
118 | if (amd_ec_wait_write(smbus)) |
||
119 | return -1; |
||
120 | outb(AMD_EC_CMD_WR, smbus->base + AMD_EC_CMD); |
||
121 | |||
122 | if (amd_ec_wait_write(smbus)) |
||
123 | return -1; |
||
124 | outb(address, smbus->base + AMD_EC_DATA); |
||
125 | |||
126 | if (amd_ec_wait_write(smbus)) |
||
127 | return -1; |
||
128 | outb(data, smbus->base + AMD_EC_DATA); |
||
129 | |||
130 | return 0; |
||
131 | } |
||
132 | |||
133 | /* |
||
134 | * ACPI 2.0 chapter 13 SMBus 2.0 EC register model |
||
135 | */ |
||
136 | |||
137 | #define AMD_SMB_PRTCL 0x00 /* protocol, PEC */ |
||
138 | #define AMD_SMB_STS 0x01 /* status */ |
||
139 | #define AMD_SMB_ADDR 0x02 /* address */ |
||
140 | #define AMD_SMB_CMD 0x03 /* command */ |
||
141 | #define AMD_SMB_DATA 0x04 /* 32 data registers */ |
||
142 | #define AMD_SMB_BCNT 0x24 /* number of data bytes */ |
||
143 | #define AMD_SMB_ALRM_A 0x25 /* alarm address */ |
||
144 | #define AMD_SMB_ALRM_D 0x26 /* 2 bytes alarm data */ |
||
145 | |||
146 | #define AMD_SMB_STS_DONE 0x80 |
||
147 | #define AMD_SMB_STS_ALRM 0x40 |
||
148 | #define AMD_SMB_STS_RES 0x20 |
||
149 | #define AMD_SMB_STS_STATUS 0x1f |
||
150 | |||
151 | #define AMD_SMB_STATUS_OK 0x00 |
||
152 | #define AMD_SMB_STATUS_FAIL 0x07 |
||
153 | #define AMD_SMB_STATUS_DNAK 0x10 |
||
154 | #define AMD_SMB_STATUS_DERR 0x11 |
||
155 | #define AMD_SMB_STATUS_CMD_DENY 0x12 |
||
156 | #define AMD_SMB_STATUS_UNKNOWN 0x13 |
||
157 | #define AMD_SMB_STATUS_ACC_DENY 0x17 |
||
158 | #define AMD_SMB_STATUS_TIMEOUT 0x18 |
||
159 | #define AMD_SMB_STATUS_NOTSUP 0x19 |
||
160 | #define AMD_SMB_STATUS_BUSY 0x1A |
||
161 | #define AMD_SMB_STATUS_PEC 0x1F |
||
162 | |||
163 | #define AMD_SMB_PRTCL_WRITE 0x00 |
||
164 | #define AMD_SMB_PRTCL_READ 0x01 |
||
165 | #define AMD_SMB_PRTCL_QUICK 0x02 |
||
166 | #define AMD_SMB_PRTCL_BYTE 0x04 |
||
167 | #define AMD_SMB_PRTCL_BYTE_DATA 0x06 |
||
168 | #define AMD_SMB_PRTCL_WORD_DATA 0x08 |
||
169 | #define AMD_SMB_PRTCL_BLOCK_DATA 0x0a |
||
170 | #define AMD_SMB_PRTCL_PROC_CALL 0x0c |
||
171 | #define AMD_SMB_PRTCL_BLOCK_PROC_CALL 0x0d |
||
172 | #define AMD_SMB_PRTCL_I2C_BLOCK_DATA 0x4a |
||
173 | #define AMD_SMB_PRTCL_PEC 0x80 |
||
174 | |||
175 | |||
176 | s32 amd8111_access(struct i2c_adapter * adap, u16 addr, unsigned short flags, |
||
177 | char read_write, u8 command, int size, union i2c_smbus_data * data) |
||
178 | { |
||
179 | struct amd_smbus *smbus = adap->algo_data; |
||
180 | unsigned char protocol, len, pec, temp[2]; |
||
181 | int i; |
||
182 | |||
183 | protocol = (read_write == I2C_SMBUS_READ) ? AMD_SMB_PRTCL_READ : AMD_SMB_PRTCL_WRITE; |
||
184 | pec = (flags & I2C_CLIENT_PEC) ? AMD_SMB_PRTCL_PEC : 0; |
||
185 | |||
186 | switch (size) { |
||
187 | |||
188 | case I2C_SMBUS_QUICK: |
||
189 | protocol |= AMD_SMB_PRTCL_QUICK; |
||
190 | read_write = I2C_SMBUS_WRITE; |
||
191 | break; |
||
192 | |||
193 | case I2C_SMBUS_BYTE: |
||
194 | if (read_write == I2C_SMBUS_WRITE) |
||
195 | amd_ec_write(smbus, AMD_SMB_DATA, data->byte); |
||
196 | protocol |= AMD_SMB_PRTCL_BYTE; |
||
197 | break; |
||
198 | |||
199 | case I2C_SMBUS_BYTE_DATA: |
||
200 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
201 | if (read_write == I2C_SMBUS_WRITE) |
||
202 | amd_ec_write(smbus, AMD_SMB_DATA, data->byte); |
||
203 | protocol |= AMD_SMB_PRTCL_BYTE_DATA; |
||
204 | break; |
||
205 | |||
206 | case I2C_SMBUS_WORD_DATA: |
||
207 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
208 | if (read_write == I2C_SMBUS_WRITE) { |
||
209 | amd_ec_write(smbus, AMD_SMB_DATA, data->word); |
||
210 | amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8); |
||
211 | } |
||
212 | protocol |= AMD_SMB_PRTCL_WORD_DATA | pec; |
||
213 | break; |
||
214 | |||
215 | case I2C_SMBUS_BLOCK_DATA: |
||
216 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
217 | if (read_write == I2C_SMBUS_WRITE) { |
||
218 | len = min_t(u8, data->block[0], 32); |
||
219 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
||
220 | for (i = 0; i < len; i++) |
||
221 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
||
222 | } |
||
223 | protocol |= AMD_SMB_PRTCL_BLOCK_DATA | pec; |
||
224 | break; |
||
225 | |||
226 | case I2C_SMBUS_I2C_BLOCK_DATA: |
||
227 | len = min_t(u8, data->block[0], 32); |
||
228 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
229 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
||
230 | if (read_write == I2C_SMBUS_WRITE) |
||
231 | for (i = 0; i < len; i++) |
||
232 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
||
233 | protocol |= AMD_SMB_PRTCL_I2C_BLOCK_DATA; |
||
234 | break; |
||
235 | |||
236 | case I2C_SMBUS_PROC_CALL: |
||
237 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
238 | amd_ec_write(smbus, AMD_SMB_DATA, data->word); |
||
239 | amd_ec_write(smbus, AMD_SMB_DATA + 1, data->word >> 8); |
||
240 | protocol = AMD_SMB_PRTCL_PROC_CALL | pec; |
||
241 | read_write = I2C_SMBUS_READ; |
||
242 | break; |
||
243 | |||
244 | case I2C_SMBUS_BLOCK_PROC_CALL: |
||
245 | protocol |= pec; |
||
246 | len = min_t(u8, data->block[0], 31); |
||
247 | amd_ec_write(smbus, AMD_SMB_CMD, command); |
||
248 | amd_ec_write(smbus, AMD_SMB_BCNT, len); |
||
249 | for (i = 0; i < len; i++) |
||
250 | amd_ec_write(smbus, AMD_SMB_DATA + i, data->block[i + 1]); |
||
251 | protocol = AMD_SMB_PRTCL_BLOCK_PROC_CALL | pec; |
||
252 | read_write = I2C_SMBUS_READ; |
||
253 | break; |
||
254 | |||
255 | case I2C_SMBUS_WORD_DATA_PEC: |
||
256 | case I2C_SMBUS_BLOCK_DATA_PEC: |
||
257 | case I2C_SMBUS_PROC_CALL_PEC: |
||
258 | case I2C_SMBUS_BLOCK_PROC_CALL_PEC: |
||
259 | dev_warn(&adap->dev, "Unexpected software PEC transaction %d\n.", size); |
||
260 | return -1; |
||
261 | |||
262 | default: |
||
263 | dev_warn(&adap->dev, "Unsupported transaction %d\n", size); |
||
264 | return -1; |
||
265 | } |
||
266 | |||
267 | amd_ec_write(smbus, AMD_SMB_ADDR, addr << 1); |
||
268 | amd_ec_write(smbus, AMD_SMB_PRTCL, protocol); |
||
269 | |||
270 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
||
271 | |||
272 | if (~temp[0] & AMD_SMB_STS_DONE) { |
||
273 | udelay(500); |
||
274 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
||
275 | } |
||
276 | |||
277 | if (~temp[0] & AMD_SMB_STS_DONE) { |
||
278 | i2c_delay(HZ/100); |
||
279 | amd_ec_read(smbus, AMD_SMB_STS, temp + 0); |
||
280 | } |
||
281 | |||
282 | if ((~temp[0] & AMD_SMB_STS_DONE) || (temp[0] & AMD_SMB_STS_STATUS)) |
||
283 | return -1; |
||
284 | |||
285 | if (read_write == I2C_SMBUS_WRITE) |
||
286 | return 0; |
||
287 | |||
288 | switch (size) { |
||
289 | |||
290 | case I2C_SMBUS_BYTE: |
||
291 | case I2C_SMBUS_BYTE_DATA: |
||
292 | amd_ec_read(smbus, AMD_SMB_DATA, &data->byte); |
||
293 | break; |
||
294 | |||
295 | case I2C_SMBUS_WORD_DATA: |
||
296 | case I2C_SMBUS_PROC_CALL: |
||
297 | amd_ec_read(smbus, AMD_SMB_DATA, temp + 0); |
||
298 | amd_ec_read(smbus, AMD_SMB_DATA + 1, temp + 1); |
||
299 | data->word = (temp[1] << 8) | temp[0]; |
||
300 | break; |
||
301 | |||
302 | case I2C_SMBUS_BLOCK_DATA: |
||
303 | case I2C_SMBUS_BLOCK_PROC_CALL: |
||
304 | amd_ec_read(smbus, AMD_SMB_BCNT, &len); |
||
305 | len = min_t(u8, len, 32); |
||
306 | case I2C_SMBUS_I2C_BLOCK_DATA: |
||
307 | for (i = 0; i < len; i++) |
||
308 | amd_ec_read(smbus, AMD_SMB_DATA + i, data->block + i + 1); |
||
309 | data->block[0] = len; |
||
310 | break; |
||
311 | } |
||
312 | |||
313 | return 0; |
||
314 | } |
||
315 | |||
316 | |||
317 | u32 amd8111_func(struct i2c_adapter *adapter) |
||
318 | { |
||
319 | return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | I2C_FUNC_SMBUS_BYTE_DATA | |
||
320 | I2C_FUNC_SMBUS_WORD_DATA | I2C_FUNC_SMBUS_BLOCK_DATA | |
||
321 | I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_BLOCK_PROC_CALL | |
||
322 | I2C_FUNC_SMBUS_I2C_BLOCK | I2C_FUNC_SMBUS_HWPEC_CALC; |
||
323 | } |
||
324 | |||
325 | static struct i2c_algorithm smbus_algorithm = { |
||
326 | .name = "Non-I2C SMBus 2.0 adapter", |
||
327 | .id = I2C_ALGO_SMBUS, |
||
328 | .smbus_xfer = amd8111_access, |
||
329 | .functionality = amd8111_func, |
||
330 | }; |
||
331 | |||
332 | |||
333 | static struct pci_device_id amd8111_ids[] = { |
||
334 | { 0x1022, 0x746a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, |
||
335 | { 0, } |
||
336 | }; |
||
337 | |||
338 | static int __devinit amd8111_probe(struct pci_dev *dev, const struct pci_device_id *id) |
||
339 | { |
||
340 | struct amd_smbus *smbus; |
||
341 | int error = -ENODEV; |
||
342 | |||
343 | if (~pci_resource_flags(dev, 0) & IORESOURCE_IO) |
||
344 | return -ENODEV; |
||
345 | |||
346 | smbus = kmalloc(sizeof(struct amd_smbus), GFP_KERNEL); |
||
347 | if (!smbus) |
||
348 | return -ENOMEM; |
||
349 | memset(smbus, 0, sizeof(struct amd_smbus)); |
||
350 | |||
351 | smbus->dev = dev; |
||
352 | smbus->base = pci_resource_start(dev, 0); |
||
353 | smbus->size = pci_resource_len(dev, 0); |
||
354 | |||
355 | if (!request_region(smbus->base, smbus->size, "amd8111 SMBus 2.0")) |
||
356 | goto out_kfree; |
||
357 | |||
358 | smbus->adapter.owner = THIS_MODULE; |
||
359 | snprintf(smbus->adapter.name, I2C_NAME_SIZE, |
||
360 | "SMBus2 AMD8111 adapter at %04x", smbus->base); |
||
361 | smbus->adapter.class = I2C_ADAP_CLASS_SMBUS; |
||
362 | smbus->adapter.algo = &smbus_algorithm; |
||
363 | smbus->adapter.algo_data = smbus; |
||
364 | |||
365 | /* set up the driverfs linkage to our parent device */ |
||
366 | smbus->adapter.dev.parent = &dev->dev; |
||
367 | |||
368 | error = i2c_add_adapter(&smbus->adapter); |
||
369 | if (error) |
||
370 | goto out_release_region; |
||
371 | |||
372 | pci_write_config_dword(smbus->dev, AMD_PCI_MISC, 0); |
||
373 | pci_set_drvdata(dev, smbus); |
||
374 | return 0; |
||
375 | |||
376 | out_release_region: |
||
377 | release_region(smbus->base, smbus->size); |
||
378 | out_kfree: |
||
379 | kfree(smbus); |
||
380 | return -1; |
||
381 | } |
||
382 | |||
383 | |||
384 | static void __devexit amd8111_remove(struct pci_dev *dev) |
||
385 | { |
||
386 | struct amd_smbus *smbus = pci_get_drvdata(dev); |
||
387 | |||
388 | i2c_del_adapter(&smbus->adapter); |
||
389 | release_region(smbus->base, smbus->size); |
||
390 | kfree(smbus); |
||
391 | } |
||
392 | |||
393 | static struct pci_driver amd8111_driver = { |
||
394 | .name = "amd8111 smbus 2", |
||
395 | .id_table = amd8111_ids, |
||
396 | .probe = amd8111_probe, |
||
397 | .remove = __devexit_p(amd8111_remove), |
||
398 | }; |
||
399 | |||
400 | static int __init i2c_amd8111_init(void) |
||
401 | { |
||
402 | return pci_module_init(&amd8111_driver); |
||
403 | } |
||
404 | |||
405 | |||
406 | static void __exit i2c_amd8111_exit(void) |
||
407 | { |
||
408 | pci_unregister_driver(&amd8111_driver); |
||
409 | } |
||
410 | |||
411 | module_init(i2c_amd8111_init); |
||
412 | module_exit(i2c_amd8111_exit); |