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Rev | Author | Line No. | Line |
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420 | giacomo | 1 | /* |
2 | * drivers/i2c/i2c-ibm_iic.h |
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3 | * |
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4 | * Support for the IIC peripheral on IBM PPC 4xx |
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5 | * |
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6 | * Copyright (c) 2003 Zultys Technologies. |
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7 | * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net> |
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8 | * |
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9 | * Based on original work by |
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10 | * Ian DaSilva <idasilva@mvista.com> |
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11 | * Armin Kuster <akuster@mvista.com> |
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12 | * Matt Porter <mporter@mvista.com> |
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13 | * |
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14 | * Copyright 2000-2003 MontaVista Software Inc. |
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15 | * |
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16 | * This program is free software; you can redistribute it and/or modify it |
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17 | * under the terms of the GNU General Public License as published by the |
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18 | * Free Software Foundation; either version 2 of the License, or (at your |
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19 | * option) any later version. |
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20 | * |
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21 | */ |
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22 | #ifndef __I2C_IBM_IIC_H_ |
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23 | #define __I2C_IBM_IIC_H_ |
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24 | |||
25 | #include <linux/config.h> |
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26 | #include <linux/i2c.h> |
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27 | |||
28 | struct iic_regs { |
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29 | u16 mdbuf; |
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30 | u16 sbbuf; |
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31 | u8 lmadr; |
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32 | u8 hmadr; |
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33 | u8 cntl; |
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34 | u8 mdcntl; |
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35 | u8 sts; |
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36 | u8 extsts; |
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37 | u8 lsadr; |
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38 | u8 hsadr; |
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39 | u8 clkdiv; |
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40 | u8 intmsk; |
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41 | u8 xfrcnt; |
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42 | u8 xtcntlss; |
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43 | u8 directcntl; |
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44 | }; |
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45 | |||
46 | struct ibm_iic_private { |
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47 | struct i2c_adapter adap; |
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48 | volatile struct iic_regs *vaddr; |
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49 | wait_queue_head_t wq; |
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50 | int idx; |
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51 | int irq; |
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52 | int fast_mode; |
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53 | u8 clckdiv; |
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54 | }; |
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55 | |||
56 | /* IICx_CNTL register */ |
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57 | #define CNTL_HMT 0x80 |
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58 | #define CNTL_AMD 0x40 |
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59 | #define CNTL_TCT_MASK 0x30 |
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60 | #define CNTL_TCT_SHIFT 4 |
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61 | #define CNTL_RPST 0x08 |
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62 | #define CNTL_CHT 0x04 |
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63 | #define CNTL_RW 0x02 |
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64 | #define CNTL_PT 0x01 |
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65 | |||
66 | /* IICx_MDCNTL register */ |
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67 | #define MDCNTL_FSDB 0x80 |
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68 | #define MDCNTL_FMDB 0x40 |
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69 | #define MDCNTL_EGC 0x20 |
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70 | #define MDCNTL_FSM 0x10 |
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71 | #define MDCNTL_ESM 0x08 |
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72 | #define MDCNTL_EINT 0x04 |
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73 | #define MDCNTL_EUBS 0x02 |
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74 | #define MDCNTL_HSCL 0x01 |
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75 | |||
76 | /* IICx_STS register */ |
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77 | #define STS_SSS 0x80 |
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78 | #define STS_SLPR 0x40 |
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79 | #define STS_MDBS 0x20 |
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80 | #define STS_MDBF 0x10 |
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81 | #define STS_SCMP 0x08 |
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82 | #define STS_ERR 0x04 |
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83 | #define STS_IRQA 0x02 |
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84 | #define STS_PT 0x01 |
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85 | |||
86 | /* IICx_EXTSTS register */ |
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87 | #define EXTSTS_IRQP 0x80 |
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88 | #define EXTSTS_BCS_MASK 0x70 |
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89 | #define EXTSTS_BCS_FREE 0x40 |
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90 | #define EXTSTS_IRQD 0x08 |
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91 | #define EXTSTS_LA 0x04 |
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92 | #define EXTSTS_ICT 0x02 |
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93 | #define EXTSTS_XFRA 0x01 |
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94 | |||
95 | /* IICx_INTRMSK register */ |
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96 | #define INTRMSK_EIRC 0x80 |
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97 | #define INTRMSK_EIRS 0x40 |
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98 | #define INTRMSK_EIWC 0x20 |
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99 | #define INTRMSK_EIWS 0x10 |
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100 | #define INTRMSK_EIHE 0x08 |
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101 | #define INTRMSK_EIIC 0x04 |
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102 | #define INTRMSK_EITA 0x02 |
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103 | #define INTRMSK_EIMTC 0x01 |
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104 | |||
105 | /* IICx_XFRCNT register */ |
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106 | #define XFRCNT_MTC_MASK 0x07 |
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107 | |||
108 | /* IICx_XTCNTLSS register */ |
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109 | #define XTCNTLSS_SRC 0x80 |
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110 | #define XTCNTLSS_SRS 0x40 |
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111 | #define XTCNTLSS_SWC 0x20 |
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112 | #define XTCNTLSS_SWS 0x10 |
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113 | #define XTCNTLSS_SRST 0x01 |
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114 | |||
115 | /* IICx_DIRECTCNTL register */ |
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116 | #define DIRCNTL_SDAC 0x08 |
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117 | #define DIRCNTL_SCC 0x04 |
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118 | #define DIRCNTL_MSDA 0x02 |
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119 | #define DIRCNTL_MSC 0x01 |
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120 | |||
121 | /* Check if we really control the I2C bus and bus is free */ |
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122 | #define DIRCTNL_FREE(v) (((v) & 0x0f) == 0x0f) |
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123 | |||
124 | #endif /* __I2C_IBM_IIC_H_ */ |