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494 giacomo 1
/*
2
 *  i8042 keyboard and mouse controller driver for Linux
3
 *
4
 *  Copyright (c) 1999-2002 Vojtech Pavlik
5
 */
6
 
7
/*
8
 * This program is free software; you can redistribute it and/or modify it
9
 * under the terms of the GNU General Public License version 2 as published by
10
 * the Free Software Foundation.
11
 */
12
 
13
#include <linuxcomp.h>
14
 
15
#include <linux/delay.h>
16
#include <linux/module.h>
17
#include <linux/interrupt.h>
18
#include <linux/ioport.h>
19
#include <linux/config.h>
20
#include <linux/reboot.h>
21
#include <linux/init.h>
22
#include <linux/serio.h>
23
 
24
#include <asm/io.h>
25
 
26
MODULE_AUTHOR("Vojtech Pavlik <vojtech@suse.cz>");
27
MODULE_DESCRIPTION("i8042 keyboard and mouse controller driver");
28
MODULE_LICENSE("GPL");
29
 
30
MODULE_PARM(i8042_noaux, "1i");
31
MODULE_PARM(i8042_nomux, "1i");
32
MODULE_PARM(i8042_unlock, "1i");
33
MODULE_PARM(i8042_reset, "1i");
34
MODULE_PARM(i8042_direct, "1i");
35
MODULE_PARM(i8042_dumbkbd, "1i");
36
 
37
static int i8042_reset;
38
static int i8042_noaux;
39
static int i8042_nomux;
40
static int i8042_unlock;
41
static int i8042_direct;
42
static int i8042_dumbkbd;
43
 
44
#undef DEBUG
45
#include "i8042.h"
46
 
47
spinlock_t i8042_lock = SPIN_LOCK_UNLOCKED;
48
 
49
struct i8042_values {
50
        int irq;
51
        unsigned char disable;
52
        unsigned char irqen;
53
        unsigned char exists;
54
        signed char mux;
55
        unsigned char *name;
56
        unsigned char *phys;
57
};
58
 
59
static struct serio i8042_kbd_port;
60
static struct serio i8042_aux_port;
61
static unsigned char i8042_initial_ctr;
62
static unsigned char i8042_ctr;
63
static unsigned char i8042_mux_open;
64
struct timer_list i8042_timer;
65
 
66
/*
67
 * Shared IRQ's require a device pointer, but this driver doesn't support
68
 * multiple devices
69
 */
70
#define i8042_request_irq_cookie (&i8042_timer)
71
 
72
static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs);
73
 
74
/*
75
 * The i8042_wait_read() and i8042_wait_write functions wait for the i8042 to
76
 * be ready for reading values from it / writing values to it.
77
 */
78
 
79
static int i8042_wait_read(void)
80
{
81
        int i = 0;
82
        while ((~i8042_read_status() & I8042_STR_OBF) && (i < I8042_CTL_TIMEOUT)) {
83
                udelay(50);
84
                i++;
85
        }
86
        return -(i == I8042_CTL_TIMEOUT);
87
}
88
 
89
static int i8042_wait_write(void)
90
{
91
        int i = 0;
92
        while ((i8042_read_status() & I8042_STR_IBF) && (i < I8042_CTL_TIMEOUT)) {
93
                udelay(50);
94
                i++;
95
        }
96
        return -(i == I8042_CTL_TIMEOUT);
97
}
98
 
99
/*
100
 * i8042_flush() flushes all data that may be in the keyboard and mouse buffers
101
 * of the i8042 down the toilet.
102
 */
103
 
104
static int i8042_flush(void)
105
{
106
        unsigned long flags;
107
        unsigned char data;
108
        int i = 0;
109
 
110
        spin_lock_irqsave(&i8042_lock, flags);
111
 
112
        while ((i8042_read_status() & I8042_STR_OBF) && (i++ < I8042_BUFFER_SIZE)) {
113
                data = i8042_read_data();
114
                dbg("%02x <- i8042 (flush, %s)", data,
115
                        i8042_read_status() & I8042_STR_AUXDATA ? "aux" : "kbd");
116
        }
117
 
118
        spin_unlock_irqrestore(&i8042_lock, flags);
119
 
120
        return i;
121
}
122
 
123
/*
124
 * i8042_command() executes a command on the i8042. It also sends the input
125
 * parameter(s) of the commands to it, and receives the output value(s). The
126
 * parameters are to be stored in the param array, and the output is placed
127
 * into the same array. The number of the parameters and output values is
128
 * encoded in bits 8-11 of the command number.
129
 */
130
 
131
static int i8042_command(unsigned char *param, int command)
132
{
133
        unsigned long flags;
134
        int retval = 0, i = 0;
135
 
136
        spin_lock_irqsave(&i8042_lock, flags);
137
 
138
        retval = i8042_wait_write();
139
        if (!retval) {
140
                dbg("%02x -> i8042 (command)", command & 0xff);
141
                i8042_write_command(command & 0xff);
142
        }
143
 
144
        if (!retval)
145
                for (i = 0; i < ((command >> 12) & 0xf); i++) {
146
                        if ((retval = i8042_wait_write())) break;
147
                        dbg("%02x -> i8042 (parameter)", param[i]);
148
                        i8042_write_data(param[i]);
149
                }
150
 
151
        if (!retval)
152
                for (i = 0; i < ((command >> 8) & 0xf); i++) {
153
                        if ((retval = i8042_wait_read())) break;
154
                        if (i8042_read_status() & I8042_STR_AUXDATA)
155
                                param[i] = ~i8042_read_data();
156
                        else
157
                                param[i] = i8042_read_data();
158
                        dbg("%02x <- i8042 (return)", param[i]);
159
                }
160
 
161
        spin_unlock_irqrestore(&i8042_lock, flags);
162
 
163
        if (retval)
164
                dbg("     -- i8042 (timeout)");
165
 
166
        return retval;
167
}
168
 
169
/*
170
 * i8042_kbd_write() sends a byte out through the keyboard interface.
171
 */
172
 
173
static int i8042_kbd_write(struct serio *port, unsigned char c)
174
{
175
        unsigned long flags;
176
        int retval = 0;
177
 
178
        spin_lock_irqsave(&i8042_lock, flags);
179
 
180
        if(!(retval = i8042_wait_write())) {
181
                dbg("%02x -> i8042 (kbd-data)", c);
182
                i8042_write_data(c);
183
        }
184
 
185
        spin_unlock_irqrestore(&i8042_lock, flags);
186
 
187
        return retval;
188
}
189
 
190
/*
191
 * i8042_aux_write() sends a byte out through the aux interface.
192
 */
193
 
194
static int i8042_aux_write(struct serio *port, unsigned char c)
195
{
196
        struct i8042_values *values = port->driver;
197
        int retval;
198
 
199
/*
200
 * Send the byte out.
201
 */
202
 
203
        if (values->mux == -1)
204
                retval = i8042_command(&c, I8042_CMD_AUX_SEND);
205
        else
206
                retval = i8042_command(&c, I8042_CMD_MUX_SEND + values->mux);
207
 
208
/*
209
 * Make sure the interrupt happens and the character is received even
210
 * in the case the IRQ isn't wired, so that we can receive further
211
 * characters later.
212
 */
213
 
214
        i8042_interrupt(0, NULL, NULL);
215
        return retval;
216
}
217
 
218
/*
219
 * i8042_open() is called when a port is open by the higher layer.
220
 * It allocates the interrupt and enables it in the chip.
221
 */
222
 
223
static int i8042_open(struct serio *port)
224
{
225
        struct i8042_values *values = port->driver;
226
 
227
        i8042_flush();
228
 
229
        if (values->mux != -1)
230
                if (i8042_mux_open++)
231
                        return 0;
232
 
233
        if (request_irq(values->irq, i8042_interrupt,
234
                        SA_SHIRQ, "i8042", i8042_request_irq_cookie)) {
235
                printk(KERN_ERR "i8042.c: Can't get irq %d for %s, unregistering the port.\n", values->irq, values->name);
236
                values->exists = 0;
237
                serio_unregister_port(port);
238
                return -1;
239
        }
240
 
241
        i8042_ctr |= values->irqen;
242
 
243
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
244
                printk(KERN_ERR "i8042.c: Can't write CTR while opening %s.\n", values->name);
245
                return -1;
246
        }
247
 
248
        i8042_interrupt(0, NULL, NULL);
249
 
250
        return 0;
251
}
252
 
253
/*
254
 * i8042_close() frees the interrupt, so that it can possibly be used
255
 * by another driver. We never know - if the user doesn't have a mouse,
256
 * the BIOS could have used the AUX interrupt for PCI.
257
 */
258
 
259
static void i8042_close(struct serio *port)
260
{
261
        struct i8042_values *values = port->driver;
262
 
263
        if (values->mux != -1)
264
                if (--i8042_mux_open)
265
                        return;
266
 
267
        i8042_ctr &= ~values->irqen;
268
 
269
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
270
                printk(KERN_ERR "i8042.c: Can't write CTR while closing %s.\n", values->name);
271
                return;
272
        }
273
 
274
        free_irq(values->irq, i8042_request_irq_cookie);
275
 
276
        i8042_flush();
277
}
278
 
279
/*
280
 * Structures for registering the devices in the serio.c module.
281
 */
282
 
283
static struct i8042_values i8042_kbd_values = {
284
        .irqen =        I8042_CTR_KBDINT,
285
        .disable =      I8042_CTR_KBDDIS,
286
        .name =         "KBD",
287
        .mux =          -1,
288
};
289
 
290
static struct serio i8042_kbd_port =
291
{
292
        .type =         SERIO_8042_XL,
293
        .write =        i8042_kbd_write,
294
        .open =         i8042_open,
295
        .close =        i8042_close,
296
        .driver =       &i8042_kbd_values,
297
        .name =         "i8042 Kbd Port",
298
        .phys =         I8042_KBD_PHYS_DESC,
299
};
300
 
301
static struct i8042_values i8042_aux_values = {
302
        .irqen =        I8042_CTR_AUXINT,
303
        .disable =      I8042_CTR_AUXDIS,
304
        .name =         "AUX",
305
        .mux =          -1,
306
};
307
 
308
static struct serio i8042_aux_port =
309
{
310
        .type =         SERIO_8042,
311
        .write =        i8042_aux_write,
312
        .open =         i8042_open,
313
        .close =        i8042_close,
314
        .driver =       &i8042_aux_values,
315
        .name =         "i8042 Aux Port",
316
        .phys =         I8042_AUX_PHYS_DESC,
317
};
318
 
319
static struct i8042_values i8042_mux_values[4];
320
static struct serio i8042_mux_port[4];
321
static char i8042_mux_names[4][32];
322
static char i8042_mux_short[4][16];
323
static char i8042_mux_phys[4][32];
324
 
325
/*
326
 * i8042_interrupt() is the most important function in this driver -
327
 * it handles the interrupts from the i8042, and sends incoming bytes
328
 * to the upper layers.
329
 */
330
 
331
static irqreturn_t i8042_interrupt(int irq, void *dev_id, struct pt_regs *regs)
332
{
333
        unsigned long flags;
334
        unsigned char str, data;
335
        unsigned int dfl;
336
        struct {
337
                int data;
338
                int str;
339
        } buffer[I8042_BUFFER_SIZE];
340
        int i, j = 0;
341
 
342
        spin_lock_irqsave(&i8042_lock, flags);
343
 
344
        while (j < I8042_BUFFER_SIZE &&
345
            (buffer[j].str = i8042_read_status()) & I8042_STR_OBF)
346
                buffer[j++].data = i8042_read_data();
347
 
348
        spin_unlock_irqrestore(&i8042_lock, flags);
349
 
350
        for (i = 0; i < j; i++) {
351
 
352
                str = buffer[i].str;
353
                data = buffer[i].data;
354
 
355
                dfl = ((str & I8042_STR_PARITY) ? SERIO_PARITY : 0) |
356
                      ((str & I8042_STR_TIMEOUT) ? SERIO_TIMEOUT : 0);
357
 
358
                if (i8042_mux_values[0].exists && (str & I8042_STR_AUXDATA)) {
359
 
360
                        if (str & I8042_STR_MUXERR) {
361
                                switch (data) {
362
                                        case 0xfd:
363
                                        case 0xfe: dfl = SERIO_TIMEOUT; break;
364
                                        case 0xff: dfl = SERIO_PARITY; break;
365
                                }
366
                                data = 0xfe;
367
                        } else dfl = 0;
368
 
369
                        dbg("%02x <- i8042 (interrupt, aux%d, %d%s%s)",
370
                                data, (str >> 6), irq,
371
                                dfl & SERIO_PARITY ? ", bad parity" : "",
372
                                dfl & SERIO_TIMEOUT ? ", timeout" : "");
373
 
374
                        serio_interrupt(i8042_mux_port + ((str >> 6) & 3), data, dfl, regs);
375
                        continue;
376
                }
377
 
378
                dbg("%02x <- i8042 (interrupt, %s, %d%s%s)",
379
                        data, (str & I8042_STR_AUXDATA) ? "aux" : "kbd", irq,
380
                        dfl & SERIO_PARITY ? ", bad parity" : "",
381
                        dfl & SERIO_TIMEOUT ? ", timeout" : "");
382
 
383
                if (i8042_aux_values.exists && (str & I8042_STR_AUXDATA)) {
384
                        serio_interrupt(&i8042_aux_port, data, dfl, regs);
385
                        continue;
386
                }
387
 
388
                if (!i8042_kbd_values.exists)
389
                        continue;
390
 
391
                serio_interrupt(&i8042_kbd_port, data, dfl, regs);
392
        }
393
 
394
        return IRQ_RETVAL(j);
395
}
396
 
397
/*
398
 * i8042_controller init initializes the i8042 controller, and,
399
 * most importantly, sets it into non-xlated mode if that's
400
 * desired.
401
 */
402
 
403
static int __init i8042_controller_init(void)
404
{
405
 
406
/*
407
 * Test the i8042. We need to know if it thinks it's working correctly
408
 * before doing anything else.
409
 */
410
 
411
        i8042_flush();
412
 
413
        if (i8042_reset) {
414
 
415
                unsigned char param;
416
 
417
                if (i8042_command(&param, I8042_CMD_CTL_TEST)) {
418
                        printk(KERN_ERR "i8042.c: i8042 controller self test timeout.\n");
419
                        return -1;
420
                }
421
 
422
                if (param != I8042_RET_CTL_TEST) {
423
                        printk(KERN_ERR "i8042.c: i8042 controller selftest failed. (%#x != %#x)\n",
424
                                 param, I8042_RET_CTL_TEST);
425
                        return -1;
426
                }
427
        }
428
 
429
/*
430
 * Save the CTR for restoral on unload / reboot.
431
 */
432
 
433
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_RCTR)) {
434
                printk(KERN_ERR "i8042.c: Can't read CTR while initializing i8042.\n");
435
                return -1;
436
        }
437
 
438
        i8042_initial_ctr = i8042_ctr;
439
 
440
/*
441
 * Disable the keyboard interface and interrupt.
442
 */
443
 
444
        i8042_ctr |= I8042_CTR_KBDDIS;
445
        i8042_ctr &= ~I8042_CTR_KBDINT;
446
 
447
/*
448
 * Handle keylock.
449
 */
450
 
451
        if (~i8042_read_status() & I8042_STR_KEYLOCK) {
452
                if (i8042_unlock)
453
                        i8042_ctr |= I8042_CTR_IGNKEYLOCK;
454
                 else
455
                        printk(KERN_WARNING "i8042.c: Warning: Keylock active.\n");
456
        }
457
 
458
/*
459
 * If the chip is configured into nontranslated mode by the BIOS, don't
460
 * bother enabling translating and be happy.
461
 */
462
 
463
        if (~i8042_ctr & I8042_CTR_XLATE)
464
                i8042_direct = 1;
465
 
466
/*
467
 * Set nontranslated mode for the kbd interface if requested by an option.
468
 * After this the kbd interface becomes a simple serial in/out, like the aux
469
 * interface is. We don't do this by default, since it can confuse notebook
470
 * BIOSes.
471
 */
472
 
473
        if (i8042_direct) {
474
                i8042_ctr &= ~I8042_CTR_XLATE;
475
                i8042_kbd_port.type = SERIO_8042;
476
        }
477
 
478
/*
479
 * Write CTR back.
480
 */
481
 
482
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
483
                printk(KERN_ERR "i8042.c: Can't write CTR while initializing i8042.\n");
484
                return -1;
485
        }
486
 
487
        return 0;
488
}
489
 
490
/*
491
 * Here we try to reset everything back to a state in which the BIOS will be
492
 * able to talk to the hardware when rebooting.
493
 */
494
 
495
void i8042_controller_cleanup(void)
496
{
497
        int i;
498
 
499
        i8042_flush();
500
 
501
/*
502
 * Reset anything that is connected to the ports.
503
 */
504
 
505
        if (i8042_kbd_values.exists)
506
                serio_cleanup(&i8042_kbd_port);
507
 
508
        if (i8042_aux_values.exists)
509
                serio_cleanup(&i8042_aux_port);
510
 
511
        for (i = 0; i < 4; i++)
512
                if (i8042_mux_values[i].exists)
513
                        serio_cleanup(i8042_mux_port + i);
514
 
515
/*
516
 * Reset the controller.
517
 */
518
 
519
        if (i8042_reset) {
520
                unsigned char param;
521
 
522
                if (i8042_command(&param, I8042_CMD_CTL_TEST))
523
                        printk(KERN_ERR "i8042.c: i8042 controller reset timeout.\n");
524
        }
525
 
526
/*
527
 * Restore the original control register setting.
528
 */
529
 
530
        i8042_ctr = i8042_initial_ctr;
531
 
532
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
533
                printk(KERN_WARNING "i8042.c: Can't restore CTR.\n");
534
 
535
}
536
 
537
/*
538
 * i8042_check_mux() checks whether the controller supports the PS/2 Active
539
 * Multiplexing specification by Synaptics, Phoenix, Insyde and
540
 * LCS/Telegraphics.
541
 */
542
 
543
static int __init i8042_check_mux(struct i8042_values *values)
544
{
545
        unsigned char param;
546
        static int i8042_check_mux_cookie;
547
        int i;
548
 
549
/*
550
 * Check if AUX irq is available.
551
 */
552
 
553
        if (request_irq(values->irq, i8042_interrupt, SA_SHIRQ,
554
                                "i8042", &i8042_check_mux_cookie))
555
                return -1;
556
        free_irq(values->irq, &i8042_check_mux_cookie);
557
 
558
/*
559
 * Get rid of bytes in the queue.
560
 */
561
 
562
        i8042_flush();
563
 
564
/*
565
 * Internal loopback test - send three bytes, they should come back from the
566
 * mouse interface, the last should be version. Note that we negate mouseport
567
 * command responses for the i8042_check_aux() routine.
568
 */
569
 
570
        param = 0xf0;
571
        if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0x0f)
572
                return -1;
573
        param = 0x56;
574
        if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xa9)
575
                return -1;
576
        param = 0xa4;
577
        if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param == 0x5b)
578
                return -1;
579
 
580
        printk(KERN_INFO "i8042.c: Detected active multiplexing controller, rev %d.%d.\n",
581
                (~param >> 4) & 0xf, ~param & 0xf);
582
 
583
/*
584
 * Disable all muxed ports by disabling AUX.
585
 */
586
 
587
        i8042_ctr |= I8042_CTR_AUXDIS;
588
        i8042_ctr &= ~I8042_CTR_AUXINT;
589
 
590
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
591
                return -1;
592
 
593
/*
594
 * Enable all muxed ports.
595
 */
596
 
597
        for (i = 0; i < 4; i++) {
598
                i8042_command(&param, I8042_CMD_MUX_PFX + i);
599
                i8042_command(&param, I8042_CMD_AUX_ENABLE);
600
        }
601
 
602
        return 0;
603
}
604
 
605
/*
606
 * i8042_check_aux() applies as much paranoia as it can at detecting
607
 * the presence of an AUX interface.
608
 */
609
 
610
static int __init i8042_check_aux(struct i8042_values *values)
611
{
612
        unsigned char param;
613
        static int i8042_check_aux_cookie;
614
 
615
/*
616
 * Check if AUX irq is available. If it isn't, then there is no point
617
 * in trying to detect AUX presence.
618
 */
619
 
620
        if (request_irq(values->irq, i8042_interrupt, SA_SHIRQ,
621
                                "i8042", &i8042_check_aux_cookie))
622
                return -1;
623
        free_irq(values->irq, &i8042_check_aux_cookie);
624
 
625
/*
626
 * Get rid of bytes in the queue.
627
 */
628
 
629
        i8042_flush();
630
 
631
/*
632
 * Internal loopback test - filters out AT-type i8042's. Unfortunately
633
 * SiS screwed up and their 5597 doesn't support the LOOP command even
634
 * though it has an AUX port.
635
 */
636
 
637
        param = 0x5a;
638
        if (i8042_command(&param, I8042_CMD_AUX_LOOP) || param != 0xa5) {
639
 
640
/*
641
 * External connection test - filters out AT-soldered PS/2 i8042's
642
 * 0x00 - no error, 0x01-0x03 - clock/data stuck, 0xff - general error
643
 * 0xfa - no error on some notebooks which ignore the spec
644
 * Because it's common for chipsets to return error on perfectly functioning
645
 * AUX ports, we test for this only when the LOOP command failed.
646
 */
647
 
648
                if (i8042_command(&param, I8042_CMD_AUX_TEST)
649
                        || (param && param != 0xfa && param != 0xff))
650
                                return -1;
651
        }
652
 
653
/*
654
 * Bit assignment test - filters out PS/2 i8042's in AT mode
655
 */
656
 
657
        if (i8042_command(&param, I8042_CMD_AUX_DISABLE))
658
                return -1;
659
        if (i8042_command(&param, I8042_CMD_CTL_RCTR) || (~param & I8042_CTR_AUXDIS))
660
                return -1;     
661
 
662
        if (i8042_command(&param, I8042_CMD_AUX_ENABLE))
663
                return -1;
664
        if (i8042_command(&param, I8042_CMD_CTL_RCTR) || (param & I8042_CTR_AUXDIS))
665
                return -1;     
666
 
667
/*
668
 * Disable the interface.
669
 */
670
 
671
        i8042_ctr |= I8042_CTR_AUXDIS;
672
        i8042_ctr &= ~I8042_CTR_AUXINT;
673
 
674
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR))
675
                return -1;
676
 
677
        return 0;
678
}
679
 
680
/*
681
 * i8042_port_register() marks the device as existing,
682
 * registers it, and reports to the user.
683
 */
684
 
685
static int __init i8042_port_register(struct i8042_values *values, struct serio *port)
686
{
687
        values->exists = 1;
688
 
689
        i8042_ctr &= ~values->disable;
690
 
691
        if (i8042_command(&i8042_ctr, I8042_CMD_CTL_WCTR)) {
692
                printk(KERN_WARNING "i8042.c: Can't write CTR while registering.\n");
693
                return -1;
694
        }
695
 
696
        serio_register_port(port);
697
 
523 mauro 698
        printk(KERN_INFO "serio: i8042 %s port at %#lx,%#lx irq %d\n",
494 giacomo 699
               values->name,
700
               (unsigned long) I8042_DATA_REG,
701
               (unsigned long) I8042_COMMAND_REG,
523 mauro 702
               values->irq);
494 giacomo 703
 
704
        return 0;
705
}
706
 
707
static void i8042_timer_func(unsigned long data)
708
{
709
        i8042_interrupt(0, NULL, NULL);
710
        mod_timer(&i8042_timer, jiffies26 + I8042_POLL_PERIOD);
711
}
712
 
713
#ifndef MODULE
714
static int __init i8042_setup_reset(char *str)
715
{
716
        i8042_reset = 1;
717
        return 1;
718
}
719
static int __init i8042_setup_noaux(char *str)
720
{
721
        i8042_noaux = 1;
722
        i8042_nomux = 1;
723
        return 1;
724
}
725
static int __init i8042_setup_nomux(char *str)
726
{
727
        i8042_nomux = 1;
728
        return 1;
729
}
730
static int __init i8042_setup_unlock(char *str)
731
{
732
        i8042_unlock = 1;
733
        return 1;
734
}
735
static int __init i8042_setup_direct(char *str)
736
{
737
        i8042_direct = 1;
738
        return 1;
739
}
740
static int __init i8042_setup_dumbkbd(char *str)
741
{
742
        i8042_dumbkbd = 1;
743
        return 1;
744
}
745
 
746
__setup("i8042_reset", i8042_setup_reset);
747
__setup("i8042_noaux", i8042_setup_noaux);
748
__setup("i8042_nomux", i8042_setup_nomux);
749
__setup("i8042_unlock", i8042_setup_unlock);
750
__setup("i8042_direct", i8042_setup_direct);
751
__setup("i8042_dumbkbd", i8042_setup_dumbkbd);
752
#endif
753
 
754
/*
755
 * We need to reset the 8042 back to original mode on system shutdown,
756
 * because otherwise BIOSes will be confused.
757
 */
523 mauro 758
/*
494 giacomo 759
static int i8042_notify_sys(struct notifier_block *this, unsigned long code,
760
                            void *unused)
761
{
762
        if (code==SYS_DOWN || code==SYS_HALT)
763
                i8042_controller_cleanup();
764
        return NOTIFY_DONE;
765
}
766
 
767
static struct notifier_block i8042_notifier=
768
{
769
        i8042_notify_sys,
770
        NULL,
771
 
772
};
523 mauro 773
*/
494 giacomo 774
static void __init i8042_init_mux_values(struct i8042_values *values, struct serio *port, int index)
775
{
776
        memcpy(port, &i8042_aux_port, sizeof(struct serio));
777
        memcpy(values, &i8042_aux_values, sizeof(struct i8042_values));
778
        sprintf26(i8042_mux_names[index], "i8042 Aux-%d Port", index);
779
        sprintf26(i8042_mux_phys[index], I8042_MUX_PHYS_DESC, index + 1);
780
        sprintf26(i8042_mux_short[index], "AUX%d", index);
781
        port->name = i8042_mux_names[index];
782
        port->phys = i8042_mux_phys[index];
783
        port->driver = values;
784
        values->name = i8042_mux_short[index];
785
        values->mux = index;
786
}
787
 
788
int __init i8042_init(void)
789
{
790
        int i;
791
 
792
        dbg_init();
793
 
794
        if (i8042_platform_init())
795
                return -EBUSY;
796
 
797
        i8042_aux_values.irq = I8042_AUX_IRQ;
798
        i8042_kbd_values.irq = I8042_KBD_IRQ;
799
 
800
        if (i8042_controller_init())
801
                return -ENODEV;
802
 
803
        if (i8042_dumbkbd)
804
                i8042_kbd_port.write = NULL;
805
 
806
        for (i = 0; i < 4; i++)
807
                i8042_init_mux_values(i8042_mux_values + i, i8042_mux_port + i, i);
808
 
809
        if (!i8042_nomux && !i8042_check_mux(&i8042_aux_values))
810
                for (i = 0; i < 4; i++)
811
                        i8042_port_register(i8042_mux_values + i, i8042_mux_port + i);
812
        else
813
                if (!i8042_noaux && !i8042_check_aux(&i8042_aux_values))
814
                        i8042_port_register(&i8042_aux_values, &i8042_aux_port);
815
 
816
        i8042_port_register(&i8042_kbd_values, &i8042_kbd_port);
817
 
818
        init_timer(&i8042_timer);
819
        i8042_timer.function = i8042_timer_func;
820
        mod_timer(&i8042_timer, jiffies26 + I8042_POLL_PERIOD);
821
 
822
        //!!!register_reboot_notifier(&i8042_notifier);
823
 
824
        return 0;
825
}
826
 
827
void __exit i8042_exit(void)
828
{
829
        int i;
830
 
831
        //!!!unregister_reboot_notifier(&i8042_notifier);
832
 
833
        del_timer(&i8042_timer);
834
 
835
        i8042_controller_cleanup();
836
 
837
        if (i8042_kbd_values.exists)
838
                serio_unregister_port(&i8042_kbd_port);
839
 
840
        if (i8042_aux_values.exists)
841
                serio_unregister_port(&i8042_aux_port);
842
 
843
        for (i = 0; i < 4; i++)
844
                if (i8042_mux_values[i].exists)
845
                        serio_unregister_port(i8042_mux_port + i);
846
 
847
        i8042_platform_exit();
848
}
849
 
850
module_init(i8042_init);
851
module_exit(i8042_exit);