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| Rev | Author | Line No. | Line |
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| 422 | giacomo | 1 | #ifndef __ASM_APICDEF_H |
| 2 | #define __ASM_APICDEF_H |
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| 3 | |||
| 4 | /* |
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| 5 | * Constants for various Intel APICs. (local APIC, IOAPIC, etc.) |
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| 6 | * |
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| 7 | * Alan Cox <Alan.Cox@linux.org>, 1995. |
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| 8 | * Ingo Molnar <mingo@redhat.com>, 1999, 2000 |
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| 9 | */ |
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| 10 | |||
| 11 | #define APIC_DEFAULT_PHYS_BASE 0xfee00000 |
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| 12 | |||
| 13 | #define APIC_ID 0x20 |
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| 14 | #define APIC_LVR 0x30 |
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| 15 | #define APIC_LVR_MASK 0xFF00FF |
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| 16 | #define GET_APIC_VERSION(x) ((x)&0xFF) |
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| 17 | #define GET_APIC_MAXLVT(x) (((x)>>16)&0xFF) |
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| 18 | #define APIC_INTEGRATED(x) ((x)&0xF0) |
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| 19 | #define APIC_TASKPRI 0x80 |
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| 20 | #define APIC_TPRI_MASK 0xFF |
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| 21 | #define APIC_ARBPRI 0x90 |
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| 22 | #define APIC_ARBPRI_MASK 0xFF |
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| 23 | #define APIC_PROCPRI 0xA0 |
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| 24 | #define APIC_EOI 0xB0 |
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| 25 | #define APIC_EIO_ACK 0x0 /* Write this to the EOI register */ |
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| 26 | #define APIC_RRR 0xC0 |
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| 27 | #define APIC_LDR 0xD0 |
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| 28 | #define APIC_LDR_MASK (0xFF<<24) |
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| 29 | #define GET_APIC_LOGICAL_ID(x) (((x)>>24)&0xFF) |
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| 30 | #define SET_APIC_LOGICAL_ID(x) (((x)<<24)) |
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| 31 | #define APIC_ALL_CPUS 0xFF |
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| 32 | #define APIC_DFR 0xE0 |
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| 33 | #define APIC_DFR_CLUSTER 0x0FFFFFFFul |
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| 34 | #define APIC_DFR_FLAT 0xFFFFFFFFul |
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| 35 | #define APIC_SPIV 0xF0 |
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| 36 | #define APIC_SPIV_FOCUS_DISABLED (1<<9) |
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| 37 | #define APIC_SPIV_APIC_ENABLED (1<<8) |
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| 38 | #define APIC_ISR 0x100 |
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| 39 | #define APIC_TMR 0x180 |
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| 40 | #define APIC_IRR 0x200 |
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| 41 | #define APIC_ESR 0x280 |
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| 42 | #define APIC_ESR_SEND_CS 0x00001 |
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| 43 | #define APIC_ESR_RECV_CS 0x00002 |
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| 44 | #define APIC_ESR_SEND_ACC 0x00004 |
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| 45 | #define APIC_ESR_RECV_ACC 0x00008 |
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| 46 | #define APIC_ESR_SENDILL 0x00020 |
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| 47 | #define APIC_ESR_RECVILL 0x00040 |
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| 48 | #define APIC_ESR_ILLREGA 0x00080 |
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| 49 | #define APIC_ICR 0x300 |
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| 50 | #define APIC_DEST_SELF 0x40000 |
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| 51 | #define APIC_DEST_ALLINC 0x80000 |
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| 52 | #define APIC_DEST_ALLBUT 0xC0000 |
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| 53 | #define APIC_ICR_RR_MASK 0x30000 |
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| 54 | #define APIC_ICR_RR_INVALID 0x00000 |
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| 55 | #define APIC_ICR_RR_INPROG 0x10000 |
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| 56 | #define APIC_ICR_RR_VALID 0x20000 |
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| 57 | #define APIC_INT_LEVELTRIG 0x08000 |
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| 58 | #define APIC_INT_ASSERT 0x04000 |
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| 59 | #define APIC_ICR_BUSY 0x01000 |
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| 60 | #define APIC_DEST_LOGICAL 0x00800 |
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| 61 | #define APIC_DM_FIXED 0x00000 |
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| 62 | #define APIC_DM_LOWEST 0x00100 |
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| 63 | #define APIC_DM_SMI 0x00200 |
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| 64 | #define APIC_DM_REMRD 0x00300 |
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| 65 | #define APIC_DM_NMI 0x00400 |
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| 66 | #define APIC_DM_INIT 0x00500 |
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| 67 | #define APIC_DM_STARTUP 0x00600 |
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| 68 | #define APIC_DM_EXTINT 0x00700 |
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| 69 | #define APIC_VECTOR_MASK 0x000FF |
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| 70 | #define APIC_ICR2 0x310 |
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| 71 | #define GET_APIC_DEST_FIELD(x) (((x)>>24)&0xFF) |
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| 72 | #define SET_APIC_DEST_FIELD(x) ((x)<<24) |
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| 73 | #define APIC_LVTT 0x320 |
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| 74 | #define APIC_LVTTHMR 0x330 |
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| 75 | #define APIC_LVTPC 0x340 |
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| 76 | #define APIC_LVT0 0x350 |
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| 77 | #define APIC_LVT_TIMER_BASE_MASK (0x3<<18) |
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| 78 | #define GET_APIC_TIMER_BASE(x) (((x)>>18)&0x3) |
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| 79 | #define SET_APIC_TIMER_BASE(x) (((x)<<18)) |
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| 80 | #define APIC_TIMER_BASE_CLKIN 0x0 |
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| 81 | #define APIC_TIMER_BASE_TMBASE 0x1 |
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| 82 | #define APIC_TIMER_BASE_DIV 0x2 |
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| 83 | #define APIC_LVT_TIMER_PERIODIC (1<<17) |
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| 84 | #define APIC_LVT_MASKED (1<<16) |
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| 85 | #define APIC_LVT_LEVEL_TRIGGER (1<<15) |
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| 86 | #define APIC_LVT_REMOTE_IRR (1<<14) |
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| 87 | #define APIC_INPUT_POLARITY (1<<13) |
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| 88 | #define APIC_SEND_PENDING (1<<12) |
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| 89 | #define GET_APIC_DELIVERY_MODE(x) (((x)>>8)&0x7) |
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| 90 | #define SET_APIC_DELIVERY_MODE(x,y) (((x)&~0x700)|((y)<<8)) |
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| 91 | #define APIC_MODE_FIXED 0x0 |
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| 92 | #define APIC_MODE_NMI 0x4 |
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| 93 | #define APIC_MODE_EXINT 0x7 |
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| 94 | #define APIC_LVT1 0x360 |
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| 95 | #define APIC_LVTERR 0x370 |
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| 96 | #define APIC_TMICT 0x380 |
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| 97 | #define APIC_TMCCT 0x390 |
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| 98 | #define APIC_TDCR 0x3E0 |
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| 99 | #define APIC_TDR_DIV_TMBASE (1<<2) |
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| 100 | #define APIC_TDR_DIV_1 0xB |
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| 101 | #define APIC_TDR_DIV_2 0x0 |
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| 102 | #define APIC_TDR_DIV_4 0x1 |
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| 103 | #define APIC_TDR_DIV_8 0x2 |
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| 104 | #define APIC_TDR_DIV_16 0x3 |
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| 105 | #define APIC_TDR_DIV_32 0x8 |
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| 106 | #define APIC_TDR_DIV_64 0x9 |
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| 107 | #define APIC_TDR_DIV_128 0xA |
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| 108 | |||
| 109 | #define APIC_BASE (fix_to_virt(FIX_APIC_BASE)) |
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| 110 | |||
| 111 | #ifdef CONFIG_NUMA |
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| 112 | #define MAX_IO_APICS 32 |
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| 113 | #else |
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| 114 | #define MAX_IO_APICS 8 |
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| 115 | #endif |
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| 116 | |||
| 117 | /* |
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| 118 | * the local APIC register structure, memory mapped. Not terribly well |
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| 119 | * tested, but we might eventually use this one in the future - the |
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| 120 | * problem why we cannot use it right now is the P5 APIC, it has an |
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| 121 | * errata which cannot take 8-bit reads and writes, only 32-bit ones ... |
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| 122 | */ |
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| 123 | #define u32 unsigned int |
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| 124 | |||
| 125 | #define lapic ((volatile struct local_apic *)APIC_BASE) |
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| 126 | |||
| 127 | struct local_apic { |
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| 128 | |||
| 129 | /*000*/ struct { u32 __reserved[4]; } __reserved_01; |
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| 130 | |||
| 131 | /*010*/ struct { u32 __reserved[4]; } __reserved_02; |
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| 132 | |||
| 133 | /*020*/ struct { /* APIC ID Register */ |
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| 134 | u32 __reserved_1 : 24, |
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| 135 | phys_apic_id : 4, |
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| 136 | __reserved_2 : 4; |
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| 137 | u32 __reserved[3]; |
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| 138 | } id; |
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| 139 | |||
| 140 | /*030*/ const |
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| 141 | struct { /* APIC Version Register */ |
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| 142 | u32 version : 8, |
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| 143 | __reserved_1 : 8, |
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| 144 | max_lvt : 8, |
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| 145 | __reserved_2 : 8; |
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| 146 | u32 __reserved[3]; |
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| 147 | } version; |
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| 148 | |||
| 149 | /*040*/ struct { u32 __reserved[4]; } __reserved_03; |
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| 150 | |||
| 151 | /*050*/ struct { u32 __reserved[4]; } __reserved_04; |
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| 152 | |||
| 153 | /*060*/ struct { u32 __reserved[4]; } __reserved_05; |
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| 154 | |||
| 155 | /*070*/ struct { u32 __reserved[4]; } __reserved_06; |
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| 156 | |||
| 157 | /*080*/ struct { /* Task Priority Register */ |
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| 158 | u32 priority : 8, |
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| 159 | __reserved_1 : 24; |
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| 160 | u32 __reserved_2[3]; |
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| 161 | } tpr; |
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| 162 | |||
| 163 | /*090*/ const |
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| 164 | struct { /* Arbitration Priority Register */ |
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| 165 | u32 priority : 8, |
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| 166 | __reserved_1 : 24; |
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| 167 | u32 __reserved_2[3]; |
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| 168 | } apr; |
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| 169 | |||
| 170 | /*0A0*/ const |
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| 171 | struct { /* Processor Priority Register */ |
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| 172 | u32 priority : 8, |
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| 173 | __reserved_1 : 24; |
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| 174 | u32 __reserved_2[3]; |
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| 175 | } ppr; |
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| 176 | |||
| 177 | /*0B0*/ struct { /* End Of Interrupt Register */ |
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| 178 | u32 eoi; |
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| 179 | u32 __reserved[3]; |
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| 180 | } eoi; |
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| 181 | |||
| 182 | /*0C0*/ struct { u32 __reserved[4]; } __reserved_07; |
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| 183 | |||
| 184 | /*0D0*/ struct { /* Logical Destination Register */ |
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| 185 | u32 __reserved_1 : 24, |
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| 186 | logical_dest : 8; |
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| 187 | u32 __reserved_2[3]; |
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| 188 | } ldr; |
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| 189 | |||
| 190 | /*0E0*/ struct { /* Destination Format Register */ |
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| 191 | u32 __reserved_1 : 28, |
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| 192 | model : 4; |
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| 193 | u32 __reserved_2[3]; |
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| 194 | } dfr; |
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| 195 | |||
| 196 | /*0F0*/ struct { /* Spurious Interrupt Vector Register */ |
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| 197 | u32 spurious_vector : 8, |
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| 198 | apic_enabled : 1, |
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| 199 | focus_cpu : 1, |
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| 200 | __reserved_2 : 22; |
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| 201 | u32 __reserved_3[3]; |
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| 202 | } svr; |
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| 203 | |||
| 204 | /*100*/ struct { /* In Service Register */ |
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| 205 | /*170*/ u32 bitfield; |
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| 206 | u32 __reserved[3]; |
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| 207 | } isr [8]; |
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| 208 | |||
| 209 | /*180*/ struct { /* Trigger Mode Register */ |
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| 210 | /*1F0*/ u32 bitfield; |
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| 211 | u32 __reserved[3]; |
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| 212 | } tmr [8]; |
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| 213 | |||
| 214 | /*200*/ struct { /* Interrupt Request Register */ |
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| 215 | /*270*/ u32 bitfield; |
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| 216 | u32 __reserved[3]; |
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| 217 | } irr [8]; |
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| 218 | |||
| 219 | /*280*/ union { /* Error Status Register */ |
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| 220 | struct { |
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| 221 | u32 send_cs_error : 1, |
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| 222 | receive_cs_error : 1, |
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| 223 | send_accept_error : 1, |
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| 224 | receive_accept_error : 1, |
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| 225 | __reserved_1 : 1, |
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| 226 | send_illegal_vector : 1, |
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| 227 | receive_illegal_vector : 1, |
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| 228 | illegal_register_address : 1, |
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| 229 | __reserved_2 : 24; |
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| 230 | u32 __reserved_3[3]; |
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| 231 | } error_bits; |
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| 232 | struct { |
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| 233 | u32 errors; |
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| 234 | u32 __reserved_3[3]; |
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| 235 | } all_errors; |
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| 236 | } esr; |
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| 237 | |||
| 238 | /*290*/ struct { u32 __reserved[4]; } __reserved_08; |
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| 239 | |||
| 240 | /*2A0*/ struct { u32 __reserved[4]; } __reserved_09; |
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| 241 | |||
| 242 | /*2B0*/ struct { u32 __reserved[4]; } __reserved_10; |
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| 243 | |||
| 244 | /*2C0*/ struct { u32 __reserved[4]; } __reserved_11; |
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| 245 | |||
| 246 | /*2D0*/ struct { u32 __reserved[4]; } __reserved_12; |
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| 247 | |||
| 248 | /*2E0*/ struct { u32 __reserved[4]; } __reserved_13; |
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| 249 | |||
| 250 | /*2F0*/ struct { u32 __reserved[4]; } __reserved_14; |
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| 251 | |||
| 252 | /*300*/ struct { /* Interrupt Command Register 1 */ |
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| 253 | u32 vector : 8, |
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| 254 | delivery_mode : 3, |
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| 255 | destination_mode : 1, |
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| 256 | delivery_status : 1, |
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| 257 | __reserved_1 : 1, |
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| 258 | level : 1, |
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| 259 | trigger : 1, |
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| 260 | __reserved_2 : 2, |
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| 261 | shorthand : 2, |
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| 262 | __reserved_3 : 12; |
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| 263 | u32 __reserved_4[3]; |
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| 264 | } icr1; |
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| 265 | |||
| 266 | /*310*/ struct { /* Interrupt Command Register 2 */ |
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| 267 | union { |
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| 268 | u32 __reserved_1 : 24, |
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| 269 | phys_dest : 4, |
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| 270 | __reserved_2 : 4; |
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| 271 | u32 __reserved_3 : 24, |
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| 272 | logical_dest : 8; |
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| 273 | } dest; |
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| 274 | u32 __reserved_4[3]; |
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| 275 | } icr2; |
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| 276 | |||
| 277 | /*320*/ struct { /* LVT - Timer */ |
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| 278 | u32 vector : 8, |
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| 279 | __reserved_1 : 4, |
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| 280 | delivery_status : 1, |
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| 281 | __reserved_2 : 3, |
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| 282 | mask : 1, |
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| 283 | timer_mode : 1, |
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| 284 | __reserved_3 : 14; |
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| 285 | u32 __reserved_4[3]; |
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| 286 | } lvt_timer; |
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| 287 | |||
| 288 | /*330*/ struct { /* LVT - Thermal Sensor */ |
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| 289 | u32 vector : 8, |
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| 290 | delivery_mode : 3, |
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| 291 | __reserved_1 : 1, |
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| 292 | delivery_status : 1, |
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| 293 | __reserved_2 : 3, |
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| 294 | mask : 1, |
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| 295 | __reserved_3 : 15; |
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| 296 | u32 __reserved_4[3]; |
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| 297 | } lvt_thermal; |
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| 298 | |||
| 299 | /*340*/ struct { /* LVT - Performance Counter */ |
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| 300 | u32 vector : 8, |
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| 301 | delivery_mode : 3, |
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| 302 | __reserved_1 : 1, |
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| 303 | delivery_status : 1, |
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| 304 | __reserved_2 : 3, |
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| 305 | mask : 1, |
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| 306 | __reserved_3 : 15; |
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| 307 | u32 __reserved_4[3]; |
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| 308 | } lvt_pc; |
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| 309 | |||
| 310 | /*350*/ struct { /* LVT - LINT0 */ |
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| 311 | u32 vector : 8, |
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| 312 | delivery_mode : 3, |
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| 313 | __reserved_1 : 1, |
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| 314 | delivery_status : 1, |
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| 315 | polarity : 1, |
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| 316 | remote_irr : 1, |
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| 317 | trigger : 1, |
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| 318 | mask : 1, |
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| 319 | __reserved_2 : 15; |
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| 320 | u32 __reserved_3[3]; |
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| 321 | } lvt_lint0; |
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| 322 | |||
| 323 | /*360*/ struct { /* LVT - LINT1 */ |
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| 324 | u32 vector : 8, |
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| 325 | delivery_mode : 3, |
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| 326 | __reserved_1 : 1, |
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| 327 | delivery_status : 1, |
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| 328 | polarity : 1, |
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| 329 | remote_irr : 1, |
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| 330 | trigger : 1, |
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| 331 | mask : 1, |
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| 332 | __reserved_2 : 15; |
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| 333 | u32 __reserved_3[3]; |
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| 334 | } lvt_lint1; |
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| 335 | |||
| 336 | /*370*/ struct { /* LVT - Error */ |
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| 337 | u32 vector : 8, |
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| 338 | __reserved_1 : 4, |
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| 339 | delivery_status : 1, |
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| 340 | __reserved_2 : 3, |
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| 341 | mask : 1, |
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| 342 | __reserved_3 : 15; |
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| 343 | u32 __reserved_4[3]; |
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| 344 | } lvt_error; |
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| 345 | |||
| 346 | /*380*/ struct { /* Timer Initial Count Register */ |
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| 347 | u32 initial_count; |
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| 348 | u32 __reserved_2[3]; |
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| 349 | } timer_icr; |
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| 350 | |||
| 351 | /*390*/ const |
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| 352 | struct { /* Timer Current Count Register */ |
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| 353 | u32 curr_count; |
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| 354 | u32 __reserved_2[3]; |
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| 355 | } timer_ccr; |
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| 356 | |||
| 357 | /*3A0*/ struct { u32 __reserved[4]; } __reserved_16; |
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| 358 | |||
| 359 | /*3B0*/ struct { u32 __reserved[4]; } __reserved_17; |
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| 360 | |||
| 361 | /*3C0*/ struct { u32 __reserved[4]; } __reserved_18; |
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| 362 | |||
| 363 | /*3D0*/ struct { u32 __reserved[4]; } __reserved_19; |
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| 364 | |||
| 365 | /*3E0*/ struct { /* Timer Divide Configuration Register */ |
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| 366 | u32 divisor : 4, |
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| 367 | __reserved_1 : 28; |
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| 368 | u32 __reserved_2[3]; |
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| 369 | } timer_dcr; |
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| 370 | |||
| 371 | /*3F0*/ struct { u32 __reserved[4]; } __reserved_20; |
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| 372 | |||
| 373 | } __attribute__ ((packed)); |
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| 374 | |||
| 375 | #undef u32 |
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| 376 | |||
| 377 | #endif |