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Rev | Author | Line No. | Line |
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424 | giacomo | 1 | #ifndef __ASM_MACH_APIC_H |
2 | #define __ASM_MACH_APIC_H |
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3 | #include <asm/smp.h> |
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4 | |||
5 | #define SEQUENTIAL_APICID |
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6 | #ifdef SEQUENTIAL_APICID |
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7 | #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\ |
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8 | ((phys_apic<<2) & (~0xf)) ) |
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9 | #elif CLUSTERED_APICID |
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10 | #define xapic_phys_to_log_apicid(phys_apic) ( (1ul << ((phys_apic) & 0x3)) |\ |
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11 | ((phys_apic) & (~0xf)) ) |
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12 | #endif |
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13 | |||
14 | #define NO_BALANCE_IRQ (1) |
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15 | #define esr_disable (1) |
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16 | |||
17 | #define NO_IOAPIC_CHECK (0) |
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18 | |||
19 | static inline int apic_id_registered(void) |
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20 | { |
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21 | return (1); |
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22 | } |
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23 | |||
24 | #define APIC_DFR_VALUE (APIC_DFR_CLUSTER) |
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25 | static inline cpumask_t target_cpus(void) |
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26 | { |
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27 | return cpu_online_map; |
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28 | } |
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29 | #define TARGET_CPUS (target_cpus()) |
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30 | |||
31 | #define INT_DELIVERY_MODE dest_LowestPrio |
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32 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ |
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33 | |||
34 | #define APIC_BROADCAST_ID (0xff) |
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35 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
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36 | { |
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37 | return 0; |
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38 | } |
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39 | |||
40 | static inline unsigned long check_apicid_present(int bit) |
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41 | { |
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42 | return physid_isset(bit, phys_cpu_present_map); |
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43 | } |
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44 | |||
45 | #define apicid_cluster(apicid) (apicid & 0xF0) |
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46 | |||
47 | static inline unsigned long calculate_ldr(unsigned long old) |
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48 | { |
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49 | unsigned long id; |
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50 | id = xapic_phys_to_log_apicid(hard_smp_processor_id()); |
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51 | return ((old & ~APIC_LDR_MASK) | SET_APIC_LOGICAL_ID(id)); |
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52 | } |
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53 | |||
54 | /* |
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55 | * Set up the logical destination ID. |
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56 | * |
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57 | * Intel recommends to set DFR, LDR and TPR before enabling |
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58 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
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59 | * document number 292116). So here it goes... |
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60 | */ |
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61 | static inline void init_apic_ldr(void) |
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62 | { |
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63 | unsigned long val; |
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64 | |||
65 | apic_write_around(APIC_DFR, APIC_DFR_VALUE); |
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66 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
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67 | val = calculate_ldr(val); |
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68 | apic_write_around(APIC_LDR, val); |
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69 | } |
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70 | |||
71 | static inline void clustered_apic_check(void) |
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72 | { |
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73 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
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74 | "Cluster", nr_ioapics); |
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75 | } |
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76 | |||
77 | static inline int multi_timer_check(int apic, int irq) |
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78 | { |
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79 | return 0; |
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80 | } |
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81 | |||
82 | static inline int apicid_to_node(int logical_apicid) |
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83 | { |
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84 | return 0; |
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85 | } |
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86 | |||
87 | extern u8 bios_cpu_apicid[]; |
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88 | |||
89 | static inline int cpu_present_to_apicid(int mps_cpu) |
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90 | { |
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91 | if (mps_cpu < NR_CPUS) |
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92 | return (int)bios_cpu_apicid[mps_cpu]; |
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93 | else |
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94 | return BAD_APICID; |
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95 | } |
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96 | |||
97 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) |
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98 | { |
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99 | return physid_mask_of_physid(phys_apicid); |
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100 | } |
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101 | |||
102 | extern u8 cpu_2_logical_apicid[]; |
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103 | /* Mapping from cpu number to logical apicid */ |
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104 | static inline int cpu_to_logical_apicid(int cpu) |
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105 | { |
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106 | if (cpu >= NR_CPUS) |
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107 | return BAD_APICID; |
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108 | return (int)cpu_2_logical_apicid[cpu]; |
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109 | } |
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110 | |||
111 | static inline int mpc_apic_id(struct mpc_config_processor *m, |
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112 | struct mpc_config_translation *translation_record) |
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113 | { |
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114 | printk("Processor #%d %ld:%ld APIC version %d\n", |
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115 | m->mpc_apicid, |
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116 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, |
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117 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, |
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118 | m->mpc_apicver); |
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119 | return m->mpc_apicid; |
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120 | } |
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121 | |||
122 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) |
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123 | { |
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124 | /* For clustered we don't have a good way to do this yet - hack */ |
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125 | return physids_promote(0xFUL); |
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126 | } |
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127 | |||
128 | #define WAKE_SECONDARY_VIA_INIT |
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129 | |||
130 | static inline void setup_portio_remap(void) |
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131 | { |
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132 | } |
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133 | |||
134 | static inline void enable_apic_mode(void) |
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135 | { |
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136 | } |
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137 | |||
138 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) |
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139 | { |
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140 | return (1); |
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141 | } |
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142 | |||
143 | static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask) |
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144 | { |
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145 | int num_bits_set; |
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146 | int cpus_found = 0; |
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147 | int cpu; |
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148 | int apicid; |
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149 | |||
150 | num_bits_set = cpus_weight_const(cpumask); |
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151 | /* Return id to all */ |
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152 | if (num_bits_set == NR_CPUS) |
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153 | return (int) 0xFF; |
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154 | /* |
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155 | * The cpus in the mask must all be on the apic cluster. If are not |
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156 | * on the same apicid cluster return default value of TARGET_CPUS. |
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157 | */ |
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158 | cpu = first_cpu_const(cpumask); |
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159 | apicid = cpu_to_logical_apicid(cpu); |
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160 | while (cpus_found < num_bits_set) { |
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161 | if (cpu_isset_const(cpu, cpumask)) { |
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162 | int new_apicid = cpu_to_logical_apicid(cpu); |
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163 | if (apicid_cluster(apicid) != |
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164 | apicid_cluster(new_apicid)){ |
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165 | printk ("%s: Not a valid mask!\n",__FUNCTION__); |
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166 | return 0xFF; |
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167 | } |
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168 | apicid = apicid | new_apicid; |
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169 | cpus_found++; |
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170 | } |
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171 | cpu++; |
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172 | } |
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173 | return apicid; |
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174 | } |
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175 | |||
176 | #endif /* __ASM_MACH_APIC_H */ |