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Rev | Author | Line No. | Line |
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424 | giacomo | 1 | #ifndef __ASM_MACH_APIC_H |
2 | #define __ASM_MACH_APIC_H |
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3 | |||
4 | #include <mach_apicdef.h> |
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5 | |||
6 | #define APIC_DFR_VALUE (APIC_DFR_FLAT) |
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7 | |||
8 | static inline cpumask_t target_cpus(void) |
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9 | { |
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10 | #ifdef CONFIG_SMP |
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11 | return cpu_online_map; |
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12 | #else |
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13 | return cpumask_of_cpu(0); |
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14 | #endif |
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15 | } |
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16 | #define TARGET_CPUS (target_cpus()) |
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17 | |||
18 | #define NO_BALANCE_IRQ (0) |
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19 | #define esr_disable (0) |
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20 | |||
21 | #define NO_IOAPIC_CHECK (0) |
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22 | |||
23 | #define INT_DELIVERY_MODE dest_LowestPrio |
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24 | #define INT_DEST_MODE 1 /* logical delivery broadcast to all procs */ |
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25 | |||
26 | /* |
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27 | * this isn't really broadcast, just a (potentially inaccurate) upper |
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28 | * bound for valid physical APIC id's |
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29 | */ |
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30 | #define APIC_BROADCAST_ID 0x0F |
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31 | |||
32 | static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid) |
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33 | { |
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34 | return physid_isset(apicid, bitmap); |
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35 | } |
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36 | |||
37 | static inline unsigned long check_apicid_present(int bit) |
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38 | { |
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39 | return physid_isset(bit, phys_cpu_present_map); |
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40 | } |
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41 | |||
42 | /* |
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43 | * Set up the logical destination ID. |
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44 | * |
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45 | * Intel recommends to set DFR, LDR and TPR before enabling |
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46 | * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel |
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47 | * document number 292116). So here it goes... |
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48 | */ |
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49 | static inline void init_apic_ldr(void) |
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50 | { |
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51 | unsigned long val; |
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52 | |||
53 | apic_write_around(APIC_DFR, APIC_DFR_VALUE); |
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54 | val = apic_read(APIC_LDR) & ~APIC_LDR_MASK; |
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55 | val |= SET_APIC_LOGICAL_ID(1UL << smp_processor_id()); |
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56 | apic_write_around(APIC_LDR, val); |
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57 | } |
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58 | |||
59 | static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_map) |
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60 | { |
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61 | return phys_map; |
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62 | } |
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63 | |||
64 | static inline void clustered_apic_check(void) |
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65 | { |
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66 | printk("Enabling APIC mode: %s. Using %d I/O APICs\n", |
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67 | "Flat", nr_ioapics); |
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68 | } |
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69 | |||
70 | static inline int multi_timer_check(int apic, int irq) |
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71 | { |
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72 | return 0; |
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73 | } |
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74 | |||
75 | static inline int apicid_to_node(int logical_apicid) |
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76 | { |
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77 | return 0; |
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78 | } |
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79 | |||
80 | /* Mapping from cpu number to logical apicid */ |
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81 | static inline int cpu_to_logical_apicid(int cpu) |
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82 | { |
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83 | return 1 << cpu; |
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84 | } |
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85 | |||
86 | static inline int cpu_present_to_apicid(int mps_cpu) |
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87 | { |
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88 | return mps_cpu; |
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89 | } |
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90 | |||
91 | static inline physid_mask_t apicid_to_cpu_present(int phys_apicid) |
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92 | { |
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93 | return physid_mask_of_physid(phys_apicid); |
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94 | } |
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95 | |||
96 | static inline int mpc_apic_id(struct mpc_config_processor *m, |
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97 | struct mpc_config_translation *translation_record) |
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98 | { |
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99 | printk("Processor #%d %ld:%ld APIC version %d\n", |
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100 | m->mpc_apicid, |
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101 | (m->mpc_cpufeature & CPU_FAMILY_MASK) >> 8, |
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102 | (m->mpc_cpufeature & CPU_MODEL_MASK) >> 4, |
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103 | m->mpc_apicver); |
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104 | return (m->mpc_apicid); |
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105 | } |
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106 | |||
107 | static inline void setup_portio_remap(void) |
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108 | { |
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109 | } |
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110 | |||
111 | static inline int check_phys_apicid_present(int boot_cpu_physical_apicid) |
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112 | { |
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113 | return physid_isset(boot_cpu_physical_apicid, phys_cpu_present_map); |
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114 | } |
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115 | |||
116 | static inline int apic_id_registered(void) |
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117 | { |
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118 | return physid_isset(GET_APIC_ID(apic_read(APIC_ID)), phys_cpu_present_map); |
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119 | } |
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120 | |||
121 | static inline unsigned int cpu_mask_to_apicid(cpumask_const_t cpumask) |
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122 | { |
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123 | return cpus_coerce_const(cpumask); |
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124 | } |
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125 | |||
126 | static inline void enable_apic_mode(void) |
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127 | { |
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128 | } |
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129 | |||
130 | #endif /* __ASM_MACH_APIC_H */ |