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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 424 | giacomo | 1 | #ifndef __I386_SGI_PIIX_H |
| 2 | #define __I386_SGI_PIIX_H |
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| 3 | |||
| 4 | /* |
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| 5 | * PIIX4 as used on SGI Visual Workstations |
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| 6 | */ |
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| 7 | |||
| 8 | #define PIIX_PM_START 0x0F80 |
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| 9 | |||
| 10 | #define SIO_GPIO_START 0x0FC0 |
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| 11 | |||
| 12 | #define SIO_PM_START 0x0FC8 |
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| 13 | |||
| 14 | #define PMBASE PIIX_PM_START |
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| 15 | #define GPIREG0 (PMBASE+0x30) |
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| 16 | #define GPIREG(x) (GPIREG0+((x)/8)) |
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| 17 | #define GPIBIT(x) (1 << ((x)%8)) |
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| 18 | |||
| 19 | #define PIIX_GPI_BD_ID1 18 |
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| 20 | #define PIIX_GPI_BD_ID2 19 |
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| 21 | #define PIIX_GPI_BD_ID3 20 |
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| 22 | #define PIIX_GPI_BD_ID4 21 |
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| 23 | #define PIIX_GPI_BD_REG GPIREG(PIIX_GPI_BD_ID1) |
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| 24 | #define PIIX_GPI_BD_MASK (GPIBIT(PIIX_GPI_BD_ID1) | \ |
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| 25 | GPIBIT(PIIX_GPI_BD_ID2) | \ |
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| 26 | GPIBIT(PIIX_GPI_BD_ID3) | \ |
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| 27 | GPIBIT(PIIX_GPI_BD_ID4) ) |
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| 28 | |||
| 29 | #define PIIX_GPI_BD_SHIFT (PIIX_GPI_BD_ID1 % 8) |
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| 30 | |||
| 31 | #define SIO_INDEX 0x2e |
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| 32 | #define SIO_DATA 0x2f |
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| 33 | |||
| 34 | #define SIO_DEV_SEL 0x7 |
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| 35 | #define SIO_DEV_ENB 0x30 |
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| 36 | #define SIO_DEV_MSB 0x60 |
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| 37 | #define SIO_DEV_LSB 0x61 |
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| 38 | |||
| 39 | #define SIO_GP_DEV 0x7 |
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| 40 | |||
| 41 | #define SIO_GP_BASE SIO_GPIO_START |
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| 42 | #define SIO_GP_MSB (SIO_GP_BASE>>8) |
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| 43 | #define SIO_GP_LSB (SIO_GP_BASE&0xff) |
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| 44 | |||
| 45 | #define SIO_GP_DATA1 (SIO_GP_BASE+0) |
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| 46 | |||
| 47 | #define SIO_PM_DEV 0x8 |
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| 48 | |||
| 49 | #define SIO_PM_BASE SIO_PM_START |
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| 50 | #define SIO_PM_MSB (SIO_PM_BASE>>8) |
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| 51 | #define SIO_PM_LSB (SIO_PM_BASE&0xff) |
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| 52 | #define SIO_PM_INDEX (SIO_PM_BASE+0) |
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| 53 | #define SIO_PM_DATA (SIO_PM_BASE+1) |
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| 54 | |||
| 55 | #define SIO_PM_FER2 0x1 |
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| 56 | |||
| 57 | #define SIO_PM_GP_EN 0x80 |
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| 58 | |||
| 59 | |||
| 60 | |||
| 61 | /* |
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| 62 | * This is the dev/reg where generating a config cycle will |
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| 63 | * result in a PCI special cycle. |
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| 64 | */ |
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| 65 | #define SPECIAL_DEV 0xff |
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| 66 | #define SPECIAL_REG 0x00 |
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| 67 | |||
| 68 | /* |
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| 69 | * PIIX4 needs to see a special cycle with the following data |
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| 70 | * to be convinced the processor has gone into the stop grant |
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| 71 | * state. PIIX4 insists on seeing this before it will power |
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| 72 | * down a system. |
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| 73 | */ |
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| 74 | #define PIIX_SPECIAL_STOP 0x00120002 |
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| 75 | |||
| 76 | #define PIIX4_RESET_PORT 0xcf9 |
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| 77 | #define PIIX4_RESET_VAL 0x6 |
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| 78 | |||
| 79 | #define PMSTS_PORT 0xf80 // 2 bytes PM Status |
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| 80 | #define PMEN_PORT 0xf82 // 2 bytes PM Enable |
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| 81 | #define PMCNTRL_PORT 0xf84 // 2 bytes PM Control |
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| 82 | |||
| 83 | #define PM_SUSPEND_ENABLE 0x2000 // start sequence to suspend state |
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| 84 | |||
| 85 | /* |
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| 86 | * PMSTS and PMEN I/O bit definitions. |
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| 87 | * (Bits are the same in both registers) |
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| 88 | */ |
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| 89 | #define PM_STS_RSM (1<<15) // Resume Status |
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| 90 | #define PM_STS_PWRBTNOR (1<<11) // Power Button Override |
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| 91 | #define PM_STS_RTC (1<<10) // RTC status |
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| 92 | #define PM_STS_PWRBTN (1<<8) // Power Button Pressed? |
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| 93 | #define PM_STS_GBL (1<<5) // Global Status |
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| 94 | #define PM_STS_BM (1<<4) // Bus Master Status |
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| 95 | #define PM_STS_TMROF (1<<0) // Timer Overflow Status. |
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| 96 | |||
| 97 | /* |
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| 98 | * Stop clock GPI register |
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| 99 | */ |
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| 100 | #define PIIX_GPIREG0 (0xf80 + 0x30) |
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| 101 | |||
| 102 | /* |
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| 103 | * Stop clock GPI bit in GPIREG0 |
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| 104 | */ |
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| 105 | #define PIIX_GPI_STPCLK 0x4 // STPCLK signal routed back in |
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| 106 | |||
| 107 | #endif |