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422 giacomo 1
/*
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 * linux/include/asm-i386/timex.h
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 *
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 * i386 architecture timex specifications
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 */
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#ifndef _ASMi386_TIMEX_H
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#define _ASMi386_TIMEX_H
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#include <linux/config.h>
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#include <asm/msr.h>
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#ifdef CONFIG_X86_PC9800
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   extern int CLOCK_TICK_RATE;
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#else
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#ifdef CONFIG_MELAN
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#  define CLOCK_TICK_RATE 1189200 /* AMD Elan has different frequency! */
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#else
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#  define CLOCK_TICK_RATE 1193182 /* Underlying HZ */
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#endif
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#endif
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#define CLOCK_TICK_FACTOR       20      /* Factor of both 1000000 and CLOCK_TICK_RATE */
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#define FINETUNE ((((((long)LATCH * HZ - CLOCK_TICK_RATE) << SHIFT_HZ) * \
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        (1000000/CLOCK_TICK_FACTOR) / (CLOCK_TICK_RATE/CLOCK_TICK_FACTOR)) \
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                << (SHIFT_SCALE-SHIFT_HZ)) / HZ)
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/*
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 * Standard way to access the cycle counter on i586+ CPUs.
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 * Currently only used on SMP.
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 *
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 * If you really have a SMP machine with i486 chips or older,
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 * compile for that, and this will just always return zero.
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 * That's ok, it just means that the nicer scheduling heuristics
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 * won't work for you.
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 *
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 * We only use the low 32 bits, and we'd simply better make sure
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 * that we reschedule before that wraps. Scheduling at least every
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 * four billion cycles just basically sounds like a good idea,
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 * regardless of how fast the machine is.
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 */
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typedef unsigned long long cycles_t;
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extern cycles_t cacheflush_time;
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static inline cycles_t get_cycles (void)
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{
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#ifndef CONFIG_X86_TSC
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        return 0;
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#else
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        unsigned long long ret;
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        rdtscll(ret);
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        return ret;
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#endif
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}
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extern unsigned long cpu_khz;
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#endif