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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | #ifndef _I386_TLBFLUSH_H |
| 2 | #define _I386_TLBFLUSH_H |
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| 3 | |||
| 4 | #include <linux/config.h> |
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| 5 | #include <linux/mm.h> |
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| 6 | #include <asm/processor.h> |
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| 7 | |||
| 8 | #define __flush_tlb() \ |
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| 9 | do { \ |
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| 10 | unsigned int tmpreg; \ |
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| 11 | \ |
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| 12 | __asm__ __volatile__( \ |
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| 13 | "movl %%cr3, %0; \n" \ |
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| 14 | "movl %0, %%cr3; # flush TLB \n" \ |
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| 15 | : "=r" (tmpreg) \ |
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| 16 | :: "memory"); \ |
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| 17 | } while (0) |
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| 18 | |||
| 19 | /* |
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| 20 | * Global pages have to be flushed a bit differently. Not a real |
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| 21 | * performance problem because this does not happen often. |
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| 22 | */ |
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| 23 | #define __flush_tlb_global() \ |
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| 24 | do { \ |
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| 25 | unsigned int tmpreg; \ |
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| 26 | \ |
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| 27 | __asm__ __volatile__( \ |
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| 28 | "movl %1, %%cr4; # turn off PGE \n" \ |
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| 29 | "movl %%cr3, %0; \n" \ |
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| 30 | "movl %0, %%cr3; # flush TLB \n" \ |
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| 31 | "movl %2, %%cr4; # turn PGE back on \n" \ |
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| 32 | : "=&r" (tmpreg) \ |
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| 33 | : "r" (mmu_cr4_features & ~X86_CR4_PGE), \ |
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| 34 | "r" (mmu_cr4_features) \ |
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| 35 | : "memory"); \ |
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| 36 | } while (0) |
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| 37 | |||
| 38 | extern unsigned long pgkern_mask; |
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| 39 | |||
| 40 | # define __flush_tlb_all() \ |
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| 41 | do { \ |
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| 42 | if (cpu_has_pge) \ |
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| 43 | __flush_tlb_global(); \ |
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| 44 | else \ |
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| 45 | __flush_tlb(); \ |
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| 46 | } while (0) |
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| 47 | |||
| 48 | #define cpu_has_invlpg (boot_cpu_data.x86 > 3) |
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| 49 | |||
| 50 | #define __flush_tlb_single(addr) \ |
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| 51 | __asm__ __volatile__("invlpg %0": :"m" (*(char *) addr)) |
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| 52 | |||
| 53 | #ifdef CONFIG_X86_INVLPG |
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| 54 | # define __flush_tlb_one(addr) __flush_tlb_single(addr) |
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| 55 | #else |
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| 56 | # define __flush_tlb_one(addr) \ |
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| 57 | do { \ |
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| 58 | if (cpu_has_invlpg) \ |
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| 59 | __flush_tlb_single(addr); \ |
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| 60 | else \ |
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| 61 | __flush_tlb(); \ |
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| 62 | } while (0) |
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| 63 | #endif |
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| 64 | |||
| 65 | /* |
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| 66 | * TLB flushing: |
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| 67 | * |
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| 68 | * - flush_tlb() flushes the current mm struct TLBs |
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| 69 | * - flush_tlb_all() flushes all processes TLBs |
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| 70 | * - flush_tlb_mm(mm) flushes the specified mm context TLB's |
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| 71 | * - flush_tlb_page(vma, vmaddr) flushes one page |
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| 72 | * - flush_tlb_range(vma, start, end) flushes a range of pages |
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| 73 | * - flush_tlb_kernel_range(start, end) flushes a range of kernel pages |
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| 74 | * - flush_tlb_pgtables(mm, start, end) flushes a range of page tables |
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| 75 | * |
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| 76 | * ..but the i386 has somewhat limited tlb flushing capabilities, |
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| 77 | * and page-granular flushes are available only on i486 and up. |
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| 78 | */ |
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| 79 | |||
| 80 | #ifndef CONFIG_SMP |
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| 81 | |||
| 82 | #define flush_tlb() __flush_tlb() |
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| 83 | #define flush_tlb_all() __flush_tlb_all() |
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| 84 | #define local_flush_tlb() __flush_tlb() |
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| 85 | |||
| 86 | static inline void flush_tlb_mm(struct mm_struct *mm) |
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| 87 | { |
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| 88 | if (mm == current->active_mm) |
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| 89 | __flush_tlb(); |
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| 90 | } |
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| 91 | |||
| 92 | static inline void flush_tlb_page(struct vm_area_struct *vma, |
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| 93 | unsigned long addr) |
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| 94 | { |
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| 95 | if (vma->vm_mm == current->active_mm) |
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| 96 | __flush_tlb_one(addr); |
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| 97 | } |
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| 98 | |||
| 99 | static inline void flush_tlb_range(struct vm_area_struct *vma, |
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| 100 | unsigned long start, unsigned long end) |
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| 101 | { |
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| 102 | if (vma->vm_mm == current->active_mm) |
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| 103 | __flush_tlb(); |
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| 104 | } |
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| 105 | |||
| 106 | #else |
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| 107 | |||
| 108 | #include <asm/smp.h> |
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| 109 | |||
| 110 | #define local_flush_tlb() \ |
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| 111 | __flush_tlb() |
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| 112 | |||
| 113 | extern void flush_tlb_all(void); |
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| 114 | extern void flush_tlb_current_task(void); |
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| 115 | extern void flush_tlb_mm(struct mm_struct *); |
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| 116 | extern void flush_tlb_page(struct vm_area_struct *, unsigned long); |
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| 117 | |||
| 118 | #define flush_tlb() flush_tlb_current_task() |
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| 119 | |||
| 120 | static inline void flush_tlb_range(struct vm_area_struct * vma, unsigned long start, unsigned long end) |
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| 121 | { |
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| 122 | flush_tlb_mm(vma->vm_mm); |
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| 123 | } |
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| 124 | |||
| 125 | #define TLBSTATE_OK 1 |
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| 126 | #define TLBSTATE_LAZY 2 |
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| 127 | |||
| 128 | struct tlb_state |
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| 129 | { |
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| 130 | struct mm_struct *active_mm; |
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| 131 | int state; |
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| 132 | char __cacheline_padding[L1_CACHE_BYTES-8]; |
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| 133 | }; |
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| 134 | extern struct tlb_state cpu_tlbstate[NR_CPUS]; |
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| 135 | |||
| 136 | |||
| 137 | #endif |
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| 138 | |||
| 139 | #define flush_tlb_kernel_range(start, end) flush_tlb_all() |
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| 140 | |||
| 141 | static inline void flush_tlb_pgtables(struct mm_struct *mm, |
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| 142 | unsigned long start, unsigned long end) |
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| 143 | { |
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| 144 | /* i386 does not keep any page table caches in TLB */ |
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| 145 | } |
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| 146 | |||
| 147 | #endif /* _I386_TLBFLUSH_H */ |