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Rev | Author | Line No. | Line |
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422 | giacomo | 1 | /* |
2 | * I2O kernel space accessible structures/APIs |
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3 | * |
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4 | * (c) Copyright 1999, 2000 Red Hat Software |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or |
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7 | * modify it under the terms of the GNU General Public License |
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8 | * as published by the Free Software Foundation; either version |
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9 | * 2 of the License, or (at your option) any later version. |
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10 | * |
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11 | ************************************************************************* |
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12 | * |
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13 | * This header file defined the I2O APIs/structures for use by |
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14 | * the I2O kernel modules. |
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15 | * |
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16 | */ |
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17 | |||
18 | #ifndef _I2O_H |
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19 | #define _I2O_H |
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20 | |||
21 | #ifdef __KERNEL__ /* This file to be included by kernel only */ |
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22 | |||
23 | #include <linux/i2o-dev.h> |
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24 | |||
25 | /* How many different OSM's are we allowing */ |
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26 | #define MAX_I2O_MODULES 4 |
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27 | |||
28 | /* How many OSMs can register themselves for device status updates? */ |
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29 | #define I2O_MAX_MANAGERS 4 |
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30 | |||
31 | #include <asm/semaphore.h> /* Needed for MUTEX init macros */ |
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32 | #include <linux/config.h> |
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33 | #include <linux/notifier.h> |
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34 | #include <asm/atomic.h> |
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35 | |||
36 | /* |
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37 | * Message structures |
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38 | */ |
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39 | struct i2o_message |
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40 | { |
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41 | u8 version_offset; |
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42 | u8 flags; |
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43 | u16 size; |
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44 | u32 target_tid:12; |
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45 | u32 init_tid:12; |
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46 | u32 function:8; |
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47 | u32 initiator_context; |
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48 | /* List follows */ |
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49 | }; |
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50 | |||
51 | /* |
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52 | * Each I2O device entity has one or more of these. There is one |
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53 | * per device. |
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54 | */ |
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55 | struct i2o_device |
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56 | { |
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57 | i2o_lct_entry lct_data; /* Device LCT information */ |
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58 | u32 flags; |
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59 | int i2oversion; /* I2O version supported. Actually |
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60 | * there should be high and low |
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61 | * version */ |
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62 | |||
63 | struct proc_dir_entry *proc_entry; /* /proc dir */ |
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64 | |||
65 | /* Primary user */ |
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66 | struct i2o_handler *owner; |
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67 | |||
68 | /* Management users */ |
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69 | struct i2o_handler *managers[I2O_MAX_MANAGERS]; |
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70 | int num_managers; |
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71 | |||
72 | struct i2o_controller *controller; /* Controlling IOP */ |
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73 | struct i2o_device *next; /* Chain */ |
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74 | struct i2o_device *prev; |
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75 | char dev_name[8]; /* linux /dev name if available */ |
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76 | }; |
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77 | |||
78 | /* |
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79 | * Each I2O controller has one of these objects |
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80 | */ |
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81 | struct i2o_controller |
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82 | { |
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83 | char name[16]; |
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84 | int unit; |
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85 | int type; |
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86 | int enabled; |
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87 | |||
88 | struct pci_dev *pdev; /* PCI device */ |
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89 | int irq; |
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90 | int short_req:1; /* Use small block sizes */ |
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91 | int dpt:1; /* Don't quiesce */ |
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92 | int promise:1; /* Promise controller */ |
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93 | #ifdef CONFIG_MTRR |
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94 | int mtrr_reg0; |
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95 | int mtrr_reg1; |
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96 | #endif |
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97 | |||
98 | struct notifier_block *event_notifer; /* Events */ |
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99 | atomic_t users; |
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100 | struct i2o_device *devices; /* I2O device chain */ |
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101 | struct i2o_controller *next; /* Controller chain */ |
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102 | unsigned long post_port; /* Inbout port address */ |
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103 | unsigned long reply_port; /* Outbound port address */ |
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104 | unsigned long irq_mask; /* Interrupt register address */ |
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105 | |||
106 | /* Dynamic LCT related data */ |
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107 | struct semaphore lct_sem; |
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108 | int lct_pid; |
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109 | int lct_running; |
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110 | |||
111 | i2o_status_block *status_block; /* IOP status block */ |
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112 | dma_addr_t status_block_phys; |
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113 | i2o_lct *lct; /* Logical Config Table */ |
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114 | dma_addr_t lct_phys; |
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115 | i2o_lct *dlct; /* Temp LCT */ |
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116 | dma_addr_t dlct_phys; |
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117 | i2o_hrt *hrt; /* HW Resource Table */ |
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118 | dma_addr_t hrt_phys; |
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119 | u32 hrt_len; |
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120 | |||
121 | unsigned long mem_offset; /* MFA offset */ |
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122 | unsigned long mem_phys; /* MFA physical */ |
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123 | |||
124 | int battery:1; /* Has a battery backup */ |
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125 | int io_alloc:1; /* An I/O resource was allocated */ |
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126 | int mem_alloc:1; /* A memory resource was allocated */ |
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127 | |||
128 | struct resource io_resource; /* I/O resource allocated to the IOP */ |
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129 | struct resource mem_resource; /* Mem resource allocated to the IOP */ |
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130 | |||
131 | struct proc_dir_entry *proc_entry; /* /proc dir */ |
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132 | |||
133 | |||
134 | void *page_frame; /* Message buffers */ |
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135 | dma_addr_t page_frame_map; /* Cache map */ |
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136 | }; |
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137 | |||
138 | /* |
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139 | * OSM resgistration block |
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140 | * |
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141 | * Each OSM creates at least one of these and registers it with the |
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142 | * I2O core through i2o_register_handler. An OSM may want to |
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143 | * register more than one if it wants a fast path to a reply |
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144 | * handler by having a separate initiator context for each |
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145 | * class function. |
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146 | */ |
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147 | struct i2o_handler |
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148 | { |
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149 | /* Message reply handler */ |
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150 | void (*reply)(struct i2o_handler *, struct i2o_controller *, |
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151 | struct i2o_message *); |
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152 | |||
153 | /* New device notification handler */ |
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154 | void (*new_dev_notify)(struct i2o_controller *, struct i2o_device *); |
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155 | |||
156 | /* Device deltion handler */ |
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157 | void (*dev_del_notify)(struct i2o_controller *, struct i2o_device *); |
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158 | |||
159 | /* Reboot notification handler */ |
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160 | void (*reboot_notify)(void); |
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161 | |||
162 | char *name; /* OSM name */ |
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163 | int context; /* Low 8 bits of the transaction info */ |
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164 | u32 class; /* I2O classes that this driver handles */ |
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165 | /* User data follows */ |
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166 | }; |
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167 | |||
168 | #ifdef MODULE |
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169 | /* |
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170 | * Used by bus specific modules to communicate with the core |
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171 | * |
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172 | * This is needed because the bus modules cannot make direct |
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173 | * calls to the core as this results in the i2o_bus_specific_module |
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174 | * being dependent on the core, not the otherway around. |
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175 | * In that case, a 'modprobe i2o_lan' loads i2o_core & i2o_lan, |
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176 | * but _not_ i2o_pci...which makes the whole thing pretty useless :) |
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177 | * |
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178 | */ |
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179 | struct i2o_core_func_table |
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180 | { |
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181 | int (*install)(struct i2o_controller *); |
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182 | int (*activate)(struct i2o_controller *); |
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183 | struct i2o_controller *(*find)(int); |
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184 | void (*unlock)(struct i2o_controller *); |
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185 | void (*run_queue)(struct i2o_controller * c); |
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186 | int (*delete)(struct i2o_controller *); |
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187 | }; |
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188 | #endif /* MODULE */ |
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189 | |||
190 | /* |
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191 | * I2O System table entry |
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192 | * |
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193 | * The system table contains information about all the IOPs in the |
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194 | * system. It is sent to all IOPs so that they can create peer2peer |
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195 | * connections between them. |
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196 | */ |
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197 | struct i2o_sys_tbl_entry |
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198 | { |
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199 | u16 org_id; |
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200 | u16 reserved1; |
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201 | u32 iop_id:12; |
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202 | u32 reserved2:20; |
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203 | u16 seg_num:12; |
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204 | u16 i2o_version:4; |
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205 | u8 iop_state; |
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206 | u8 msg_type; |
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207 | u16 frame_size; |
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208 | u16 reserved3; |
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209 | u32 last_changed; |
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210 | u32 iop_capabilities; |
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211 | u32 inbound_low; |
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212 | u32 inbound_high; |
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213 | }; |
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214 | |||
215 | struct i2o_sys_tbl |
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216 | { |
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217 | u8 num_entries; |
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218 | u8 version; |
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219 | u16 reserved1; |
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220 | u32 change_ind; |
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221 | u32 reserved2; |
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222 | u32 reserved3; |
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223 | struct i2o_sys_tbl_entry iops[0]; |
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224 | }; |
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225 | |||
226 | /* |
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227 | * Messenger inlines |
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228 | */ |
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229 | static inline u32 I2O_POST_READ32(struct i2o_controller *c) |
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230 | { |
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231 | return readl(c->post_port); |
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232 | } |
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233 | |||
234 | static inline void I2O_POST_WRITE32(struct i2o_controller *c, u32 val) |
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235 | { |
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236 | writel(val, c->post_port); |
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237 | } |
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238 | |||
239 | |||
240 | static inline u32 I2O_REPLY_READ32(struct i2o_controller *c) |
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241 | { |
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242 | return readl(c->reply_port); |
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243 | } |
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244 | |||
245 | static inline void I2O_REPLY_WRITE32(struct i2o_controller *c, u32 val) |
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246 | { |
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247 | writel(val, c->reply_port); |
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248 | } |
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249 | |||
250 | |||
251 | static inline u32 I2O_IRQ_READ32(struct i2o_controller *c) |
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252 | { |
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253 | return readl(c->irq_mask); |
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254 | } |
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255 | |||
256 | static inline void I2O_IRQ_WRITE32(struct i2o_controller *c, u32 val) |
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257 | { |
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258 | writel(val, c->irq_mask); |
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259 | } |
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260 | |||
261 | |||
262 | static inline void i2o_post_message(struct i2o_controller *c, u32 m) |
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263 | { |
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264 | /* The second line isnt spurious - thats forcing PCI posting */ |
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265 | I2O_POST_WRITE32(c, m); |
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266 | (void) I2O_IRQ_READ32(c); |
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267 | } |
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268 | |||
269 | static inline void i2o_flush_reply(struct i2o_controller *c, u32 m) |
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270 | { |
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271 | I2O_REPLY_WRITE32(c, m); |
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272 | } |
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273 | |||
274 | /* |
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275 | * Endian handling wrapped into the macro - keeps the core code |
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276 | * cleaner. |
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277 | */ |
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278 | |||
279 | #define i2o_raw_writel(val, mem) __raw_writel(cpu_to_le32(val), mem) |
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280 | |||
281 | extern struct i2o_controller *i2o_find_controller(int); |
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282 | extern void i2o_unlock_controller(struct i2o_controller *); |
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283 | extern struct i2o_controller *i2o_controller_chain; |
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284 | extern int i2o_num_controllers; |
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285 | extern int i2o_status_get(struct i2o_controller *); |
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286 | |||
287 | extern int i2o_install_handler(struct i2o_handler *); |
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288 | extern int i2o_remove_handler(struct i2o_handler *); |
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289 | |||
290 | extern int i2o_claim_device(struct i2o_device *, struct i2o_handler *); |
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291 | extern int i2o_release_device(struct i2o_device *, struct i2o_handler *); |
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292 | extern int i2o_device_notify_on(struct i2o_device *, struct i2o_handler *); |
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293 | extern int i2o_device_notify_off(struct i2o_device *, |
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294 | struct i2o_handler *); |
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295 | |||
296 | extern int i2o_post_this(struct i2o_controller *, u32 *, int); |
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297 | extern int i2o_post_wait(struct i2o_controller *, u32 *, int, int); |
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298 | extern int i2o_post_wait_mem(struct i2o_controller *, u32 *, int, int, |
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299 | void *, void *, dma_addr_t, dma_addr_t, int, int); |
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300 | |||
301 | extern int i2o_query_scalar(struct i2o_controller *, int, int, int, void *, |
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302 | int); |
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303 | extern int i2o_set_scalar(struct i2o_controller *, int, int, int, void *, |
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304 | int); |
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305 | extern int i2o_query_table(int, struct i2o_controller *, int, int, int, |
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306 | void *, int, void *, int); |
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307 | extern int i2o_clear_table(struct i2o_controller *, int, int); |
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308 | extern int i2o_row_add_table(struct i2o_controller *, int, int, int, |
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309 | void *, int); |
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310 | extern int i2o_issue_params(int, struct i2o_controller *, int, void *, int, |
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311 | void *, int); |
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312 | |||
313 | extern int i2o_event_register(struct i2o_controller *, u32, u32, u32, u32); |
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314 | extern int i2o_event_ack(struct i2o_controller *, u32 *); |
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315 | |||
316 | extern void i2o_report_status(const char *, const char *, u32 *); |
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317 | extern void i2o_dump_message(u32 *); |
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318 | extern const char *i2o_get_class_name(int); |
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319 | |||
320 | extern int i2o_install_controller(struct i2o_controller *); |
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321 | extern int i2o_activate_controller(struct i2o_controller *); |
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322 | extern void i2o_run_queue(struct i2o_controller *); |
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323 | extern int i2o_delete_controller(struct i2o_controller *); |
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324 | |||
325 | /* |
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326 | * Cache strategies |
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327 | */ |
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328 | |||
329 | |||
330 | /* The NULL strategy leaves everything up to the controller. This tends to be a |
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331 | * pessimal but functional choice. |
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332 | */ |
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333 | #define CACHE_NULL 0 |
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334 | /* Prefetch data when reading. We continually attempt to load the next 32 sectors |
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335 | * into the controller cache. |
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336 | */ |
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337 | #define CACHE_PREFETCH 1 |
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338 | /* Prefetch data when reading. We sometimes attempt to load the next 32 sectors |
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339 | * into the controller cache. When an I/O is less <= 8K we assume its probably |
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340 | * not sequential and don't prefetch (default) |
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341 | */ |
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342 | #define CACHE_SMARTFETCH 2 |
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343 | /* Data is written to the cache and then out on to the disk. The I/O must be |
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344 | * physically on the medium before the write is acknowledged (default without |
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345 | * NVRAM) |
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346 | */ |
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347 | #define CACHE_WRITETHROUGH 17 |
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348 | /* Data is written to the cache and then out on to the disk. The controller |
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349 | * is permitted to write back the cache any way it wants. (default if battery |
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350 | * backed NVRAM is present). It can be useful to set this for swap regardless of |
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351 | * battery state. |
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352 | */ |
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353 | #define CACHE_WRITEBACK 18 |
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354 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We |
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355 | * write large I/O's directly to disk bypassing the cache to avoid the extra |
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356 | * memory copy hits. Small writes are writeback cached |
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357 | */ |
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358 | #define CACHE_SMARTBACK 19 |
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359 | /* Optimise for under powered controllers, especially on RAID1 and RAID0. We |
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360 | * write large I/O's directly to disk bypassing the cache to avoid the extra |
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361 | * memory copy hits. Small writes are writethrough cached. Suitable for devices |
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362 | * lacking battery backup |
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363 | */ |
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364 | #define CACHE_SMARTTHROUGH 20 |
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365 | |||
366 | /* |
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367 | * Ioctl structures |
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368 | */ |
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369 | |||
370 | |||
371 | #define BLKI2OGRSTRAT _IOR('2', 1, int) |
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372 | #define BLKI2OGWSTRAT _IOR('2', 2, int) |
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373 | #define BLKI2OSRSTRAT _IOW('2', 3, int) |
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374 | #define BLKI2OSWSTRAT _IOW('2', 4, int) |
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375 | |||
376 | |||
377 | |||
378 | |||
379 | /* |
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380 | * I2O Function codes |
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381 | */ |
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382 | |||
383 | /* |
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384 | * Executive Class |
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385 | */ |
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386 | #define I2O_CMD_ADAPTER_ASSIGN 0xB3 |
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387 | #define I2O_CMD_ADAPTER_READ 0xB2 |
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388 | #define I2O_CMD_ADAPTER_RELEASE 0xB5 |
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389 | #define I2O_CMD_BIOS_INFO_SET 0xA5 |
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390 | #define I2O_CMD_BOOT_DEVICE_SET 0xA7 |
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391 | #define I2O_CMD_CONFIG_VALIDATE 0xBB |
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392 | #define I2O_CMD_CONN_SETUP 0xCA |
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393 | #define I2O_CMD_DDM_DESTROY 0xB1 |
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394 | #define I2O_CMD_DDM_ENABLE 0xD5 |
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395 | #define I2O_CMD_DDM_QUIESCE 0xC7 |
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396 | #define I2O_CMD_DDM_RESET 0xD9 |
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397 | #define I2O_CMD_DDM_SUSPEND 0xAF |
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398 | #define I2O_CMD_DEVICE_ASSIGN 0xB7 |
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399 | #define I2O_CMD_DEVICE_RELEASE 0xB9 |
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400 | #define I2O_CMD_HRT_GET 0xA8 |
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401 | #define I2O_CMD_ADAPTER_CLEAR 0xBE |
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402 | #define I2O_CMD_ADAPTER_CONNECT 0xC9 |
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403 | #define I2O_CMD_ADAPTER_RESET 0xBD |
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404 | #define I2O_CMD_LCT_NOTIFY 0xA2 |
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405 | #define I2O_CMD_OUTBOUND_INIT 0xA1 |
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406 | #define I2O_CMD_PATH_ENABLE 0xD3 |
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407 | #define I2O_CMD_PATH_QUIESCE 0xC5 |
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408 | #define I2O_CMD_PATH_RESET 0xD7 |
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409 | #define I2O_CMD_STATIC_MF_CREATE 0xDD |
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410 | #define I2O_CMD_STATIC_MF_RELEASE 0xDF |
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411 | #define I2O_CMD_STATUS_GET 0xA0 |
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412 | #define I2O_CMD_SW_DOWNLOAD 0xA9 |
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413 | #define I2O_CMD_SW_UPLOAD 0xAB |
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414 | #define I2O_CMD_SW_REMOVE 0xAD |
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415 | #define I2O_CMD_SYS_ENABLE 0xD1 |
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416 | #define I2O_CMD_SYS_MODIFY 0xC1 |
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417 | #define I2O_CMD_SYS_QUIESCE 0xC3 |
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418 | #define I2O_CMD_SYS_TAB_SET 0xA3 |
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419 | |||
420 | /* |
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421 | * Utility Class |
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422 | */ |
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423 | #define I2O_CMD_UTIL_NOP 0x00 |
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424 | #define I2O_CMD_UTIL_ABORT 0x01 |
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425 | #define I2O_CMD_UTIL_CLAIM 0x09 |
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426 | #define I2O_CMD_UTIL_RELEASE 0x0B |
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427 | #define I2O_CMD_UTIL_PARAMS_GET 0x06 |
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428 | #define I2O_CMD_UTIL_PARAMS_SET 0x05 |
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429 | #define I2O_CMD_UTIL_EVT_REGISTER 0x13 |
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430 | #define I2O_CMD_UTIL_EVT_ACK 0x14 |
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431 | #define I2O_CMD_UTIL_CONFIG_DIALOG 0x10 |
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432 | #define I2O_CMD_UTIL_DEVICE_RESERVE 0x0D |
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433 | #define I2O_CMD_UTIL_DEVICE_RELEASE 0x0F |
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434 | #define I2O_CMD_UTIL_LOCK 0x17 |
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435 | #define I2O_CMD_UTIL_LOCK_RELEASE 0x19 |
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436 | #define I2O_CMD_UTIL_REPLY_FAULT_NOTIFY 0x15 |
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437 | |||
438 | /* |
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439 | * SCSI Host Bus Adapter Class |
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440 | */ |
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441 | #define I2O_CMD_SCSI_EXEC 0x81 |
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442 | #define I2O_CMD_SCSI_ABORT 0x83 |
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443 | #define I2O_CMD_SCSI_BUSRESET 0x27 |
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444 | |||
445 | /* |
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446 | * Random Block Storage Class |
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447 | */ |
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448 | #define I2O_CMD_BLOCK_READ 0x30 |
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449 | #define I2O_CMD_BLOCK_WRITE 0x31 |
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450 | #define I2O_CMD_BLOCK_CFLUSH 0x37 |
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451 | #define I2O_CMD_BLOCK_MLOCK 0x49 |
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452 | #define I2O_CMD_BLOCK_MUNLOCK 0x4B |
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453 | #define I2O_CMD_BLOCK_MMOUNT 0x41 |
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454 | #define I2O_CMD_BLOCK_MEJECT 0x43 |
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455 | #define I2O_CMD_BLOCK_POWER 0x70 |
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456 | |||
457 | #define I2O_PRIVATE_MSG 0xFF |
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458 | |||
459 | /* Command status values */ |
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460 | |||
461 | #define I2O_CMD_IN_PROGRESS 0x01 |
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462 | #define I2O_CMD_REJECTED 0x02 |
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463 | #define I2O_CMD_FAILED 0x03 |
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464 | #define I2O_CMD_COMPLETED 0x04 |
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465 | |||
466 | /* I2O API function return values */ |
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467 | |||
468 | #define I2O_RTN_NO_ERROR 0 |
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469 | #define I2O_RTN_NOT_INIT 1 |
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470 | #define I2O_RTN_FREE_Q_EMPTY 2 |
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471 | #define I2O_RTN_TCB_ERROR 3 |
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472 | #define I2O_RTN_TRANSACTION_ERROR 4 |
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473 | #define I2O_RTN_ADAPTER_ALREADY_INIT 5 |
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474 | #define I2O_RTN_MALLOC_ERROR 6 |
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475 | #define I2O_RTN_ADPTR_NOT_REGISTERED 7 |
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476 | #define I2O_RTN_MSG_REPLY_TIMEOUT 8 |
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477 | #define I2O_RTN_NO_STATUS 9 |
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478 | #define I2O_RTN_NO_FIRM_VER 10 |
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479 | #define I2O_RTN_NO_LINK_SPEED 11 |
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480 | |||
481 | /* Reply message status defines for all messages */ |
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482 | |||
483 | #define I2O_REPLY_STATUS_SUCCESS 0x00 |
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484 | #define I2O_REPLY_STATUS_ABORT_DIRTY 0x01 |
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485 | #define I2O_REPLY_STATUS_ABORT_NO_DATA_TRANSFER 0x02 |
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486 | #define I2O_REPLY_STATUS_ABORT_PARTIAL_TRANSFER 0x03 |
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487 | #define I2O_REPLY_STATUS_ERROR_DIRTY 0x04 |
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488 | #define I2O_REPLY_STATUS_ERROR_NO_DATA_TRANSFER 0x05 |
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489 | #define I2O_REPLY_STATUS_ERROR_PARTIAL_TRANSFER 0x06 |
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490 | #define I2O_REPLY_STATUS_PROCESS_ABORT_DIRTY 0x08 |
||
491 | #define I2O_REPLY_STATUS_PROCESS_ABORT_NO_DATA_TRANSFER 0x09 |
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492 | #define I2O_REPLY_STATUS_PROCESS_ABORT_PARTIAL_TRANSFER 0x0A |
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493 | #define I2O_REPLY_STATUS_TRANSACTION_ERROR 0x0B |
||
494 | #define I2O_REPLY_STATUS_PROGRESS_REPORT 0x80 |
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495 | |||
496 | /* Status codes and Error Information for Parameter functions */ |
||
497 | |||
498 | #define I2O_PARAMS_STATUS_SUCCESS 0x00 |
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499 | #define I2O_PARAMS_STATUS_BAD_KEY_ABORT 0x01 |
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500 | #define I2O_PARAMS_STATUS_BAD_KEY_CONTINUE 0x02 |
||
501 | #define I2O_PARAMS_STATUS_BUFFER_FULL 0x03 |
||
502 | #define I2O_PARAMS_STATUS_BUFFER_TOO_SMALL 0x04 |
||
503 | #define I2O_PARAMS_STATUS_FIELD_UNREADABLE 0x05 |
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504 | #define I2O_PARAMS_STATUS_FIELD_UNWRITEABLE 0x06 |
||
505 | #define I2O_PARAMS_STATUS_INSUFFICIENT_FIELDS 0x07 |
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506 | #define I2O_PARAMS_STATUS_INVALID_GROUP_ID 0x08 |
||
507 | #define I2O_PARAMS_STATUS_INVALID_OPERATION 0x09 |
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508 | #define I2O_PARAMS_STATUS_NO_KEY_FIELD 0x0A |
||
509 | #define I2O_PARAMS_STATUS_NO_SUCH_FIELD 0x0B |
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510 | #define I2O_PARAMS_STATUS_NON_DYNAMIC_GROUP 0x0C |
||
511 | #define I2O_PARAMS_STATUS_OPERATION_ERROR 0x0D |
||
512 | #define I2O_PARAMS_STATUS_SCALAR_ERROR 0x0E |
||
513 | #define I2O_PARAMS_STATUS_TABLE_ERROR 0x0F |
||
514 | #define I2O_PARAMS_STATUS_WRONG_GROUP_TYPE 0x10 |
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515 | |||
516 | /* DetailedStatusCode defines for Executive, DDM, Util and Transaction error |
||
517 | * messages: Table 3-2 Detailed Status Codes.*/ |
||
518 | |||
519 | #define I2O_DSC_SUCCESS 0x0000 |
||
520 | #define I2O_DSC_BAD_KEY 0x0002 |
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521 | #define I2O_DSC_TCL_ERROR 0x0003 |
||
522 | #define I2O_DSC_REPLY_BUFFER_FULL 0x0004 |
||
523 | #define I2O_DSC_NO_SUCH_PAGE 0x0005 |
||
524 | #define I2O_DSC_INSUFFICIENT_RESOURCE_SOFT 0x0006 |
||
525 | #define I2O_DSC_INSUFFICIENT_RESOURCE_HARD 0x0007 |
||
526 | #define I2O_DSC_CHAIN_BUFFER_TOO_LARGE 0x0009 |
||
527 | #define I2O_DSC_UNSUPPORTED_FUNCTION 0x000A |
||
528 | #define I2O_DSC_DEVICE_LOCKED 0x000B |
||
529 | #define I2O_DSC_DEVICE_RESET 0x000C |
||
530 | #define I2O_DSC_INAPPROPRIATE_FUNCTION 0x000D |
||
531 | #define I2O_DSC_INVALID_INITIATOR_ADDRESS 0x000E |
||
532 | #define I2O_DSC_INVALID_MESSAGE_FLAGS 0x000F |
||
533 | #define I2O_DSC_INVALID_OFFSET 0x0010 |
||
534 | #define I2O_DSC_INVALID_PARAMETER 0x0011 |
||
535 | #define I2O_DSC_INVALID_REQUEST 0x0012 |
||
536 | #define I2O_DSC_INVALID_TARGET_ADDRESS 0x0013 |
||
537 | #define I2O_DSC_MESSAGE_TOO_LARGE 0x0014 |
||
538 | #define I2O_DSC_MESSAGE_TOO_SMALL 0x0015 |
||
539 | #define I2O_DSC_MISSING_PARAMETER 0x0016 |
||
540 | #define I2O_DSC_TIMEOUT 0x0017 |
||
541 | #define I2O_DSC_UNKNOWN_ERROR 0x0018 |
||
542 | #define I2O_DSC_UNKNOWN_FUNCTION 0x0019 |
||
543 | #define I2O_DSC_UNSUPPORTED_VERSION 0x001A |
||
544 | #define I2O_DSC_DEVICE_BUSY 0x001B |
||
545 | #define I2O_DSC_DEVICE_NOT_AVAILABLE 0x001C |
||
546 | |||
547 | /* FailureStatusCodes, Table 3-3 Message Failure Codes */ |
||
548 | |||
549 | #define I2O_FSC_TRANSPORT_SERVICE_SUSPENDED 0x81 |
||
550 | #define I2O_FSC_TRANSPORT_SERVICE_TERMINATED 0x82 |
||
551 | #define I2O_FSC_TRANSPORT_CONGESTION 0x83 |
||
552 | #define I2O_FSC_TRANSPORT_FAILURE 0x84 |
||
553 | #define I2O_FSC_TRANSPORT_STATE_ERROR 0x85 |
||
554 | #define I2O_FSC_TRANSPORT_TIME_OUT 0x86 |
||
555 | #define I2O_FSC_TRANSPORT_ROUTING_FAILURE 0x87 |
||
556 | #define I2O_FSC_TRANSPORT_INVALID_VERSION 0x88 |
||
557 | #define I2O_FSC_TRANSPORT_INVALID_OFFSET 0x89 |
||
558 | #define I2O_FSC_TRANSPORT_INVALID_MSG_FLAGS 0x8A |
||
559 | #define I2O_FSC_TRANSPORT_FRAME_TOO_SMALL 0x8B |
||
560 | #define I2O_FSC_TRANSPORT_FRAME_TOO_LARGE 0x8C |
||
561 | #define I2O_FSC_TRANSPORT_INVALID_TARGET_ID 0x8D |
||
562 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_ID 0x8E |
||
563 | #define I2O_FSC_TRANSPORT_INVALID_INITIATOR_CONTEXT 0x8F |
||
564 | #define I2O_FSC_TRANSPORT_UNKNOWN_FAILURE 0xFF |
||
565 | |||
566 | /* Device Claim Types */ |
||
567 | #define I2O_CLAIM_PRIMARY 0x01000000 |
||
568 | #define I2O_CLAIM_MANAGEMENT 0x02000000 |
||
569 | #define I2O_CLAIM_AUTHORIZED 0x03000000 |
||
570 | #define I2O_CLAIM_SECONDARY 0x04000000 |
||
571 | |||
572 | /* Message header defines for VersionOffset */ |
||
573 | #define I2OVER15 0x0001 |
||
574 | #define I2OVER20 0x0002 |
||
575 | |||
576 | /* Default is 1.5, FIXME: Need support for both 1.5 and 2.0 */ |
||
577 | #define I2OVERSION I2OVER15 |
||
578 | |||
579 | #define SGL_OFFSET_0 I2OVERSION |
||
580 | #define SGL_OFFSET_4 (0x0040 | I2OVERSION) |
||
581 | #define SGL_OFFSET_5 (0x0050 | I2OVERSION) |
||
582 | #define SGL_OFFSET_6 (0x0060 | I2OVERSION) |
||
583 | #define SGL_OFFSET_7 (0x0070 | I2OVERSION) |
||
584 | #define SGL_OFFSET_8 (0x0080 | I2OVERSION) |
||
585 | #define SGL_OFFSET_9 (0x0090 | I2OVERSION) |
||
586 | #define SGL_OFFSET_10 (0x00A0 | I2OVERSION) |
||
587 | |||
588 | #define TRL_OFFSET_5 (0x0050 | I2OVERSION) |
||
589 | #define TRL_OFFSET_6 (0x0060 | I2OVERSION) |
||
590 | |||
591 | /* Transaction Reply Lists (TRL) Control Word structure */ |
||
592 | #define TRL_SINGLE_FIXED_LENGTH 0x00 |
||
593 | #define TRL_SINGLE_VARIABLE_LENGTH 0x40 |
||
594 | #define TRL_MULTIPLE_FIXED_LENGTH 0x80 |
||
595 | |||
596 | |||
597 | /* msg header defines for MsgFlags */ |
||
598 | #define MSG_STATIC 0x0100 |
||
599 | #define MSG_64BIT_CNTXT 0x0200 |
||
600 | #define MSG_MULTI_TRANS 0x1000 |
||
601 | #define MSG_FAIL 0x2000 |
||
602 | #define MSG_FINAL 0x4000 |
||
603 | #define MSG_REPLY 0x8000 |
||
604 | |||
605 | /* minimum size msg */ |
||
606 | #define THREE_WORD_MSG_SIZE 0x00030000 |
||
607 | #define FOUR_WORD_MSG_SIZE 0x00040000 |
||
608 | #define FIVE_WORD_MSG_SIZE 0x00050000 |
||
609 | #define SIX_WORD_MSG_SIZE 0x00060000 |
||
610 | #define SEVEN_WORD_MSG_SIZE 0x00070000 |
||
611 | #define EIGHT_WORD_MSG_SIZE 0x00080000 |
||
612 | #define NINE_WORD_MSG_SIZE 0x00090000 |
||
613 | #define TEN_WORD_MSG_SIZE 0x000A0000 |
||
614 | #define ELEVEN_WORD_MSG_SIZE 0x000B0000 |
||
615 | #define I2O_MESSAGE_SIZE(x) ((x)<<16) |
||
616 | |||
617 | |||
618 | /* Special TID Assignments */ |
||
619 | |||
620 | #define ADAPTER_TID 0 |
||
621 | #define HOST_TID 1 |
||
622 | |||
623 | #define MSG_FRAME_SIZE 64 /* i2o_scsi assumes >= 32 */ |
||
624 | #define NMBR_MSG_FRAMES 128 |
||
625 | |||
626 | #define MSG_POOL_SIZE (MSG_FRAME_SIZE*NMBR_MSG_FRAMES*sizeof(u32)) |
||
627 | |||
628 | #define I2O_POST_WAIT_OK 0 |
||
629 | #define I2O_POST_WAIT_TIMEOUT -ETIMEDOUT |
||
630 | |||
631 | #endif /* __KERNEL__ */ |
||
632 | #endif /* _I2O_H */ |