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#ifndef __LINUX_IBMTR_H__
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#define __LINUX_IBMTR_H__
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/* Definitions for an IBM Token Ring card. */
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/* This file is distributed under the GNU GPL   */
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/* ported to the Alpha architecture 02/20/96 (just used the HZ macro) */
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#define TR_RETRY_INTERVAL       (30*HZ) /* 500 on PC = 5 s */
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#define TR_RST_TIME             (HZ/20) /* 5 on PC = 50 ms */
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#define TR_BUSY_INTERVAL        (HZ/5)  /* 5 on PC = 200 ms */
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#define TR_SPIN_INTERVAL        (3*HZ)  /* 3 seconds before init timeout */
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#define TR_ISA 1
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#define TR_MCA 2
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#define TR_ISAPNP 3
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#define NOTOK 0
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#define IBMTR_SHARED_RAM_SIZE 0x10000
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#define IBMTR_IO_EXTENT 4
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#define IBMTR_MAX_ADAPTERS 4
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#define CHANNEL_ID      0X1F30
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#define AIP             0X1F00
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#define AIPADAPTYPE     0X1FA0
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#define AIPDATARATE     0X1FA2
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#define AIPEARLYTOKEN   0X1FA4
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#define AIPAVAILSHRAM   0X1FA6
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#define AIPSHRAMPAGE    0X1FA8
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#define AIP4MBDHB       0X1FAA
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#define AIP16MBDHB      0X1FAC
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#define AIPFID          0X1FBA
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#define ADAPTRESET      0x1     /* Control Adapter reset (add to base) */
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#define ADAPTRESETREL   0x2     /* Release Adapter from reset ( """)  */
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#define ADAPTINTREL     0x3     /* Adapter interrupt release */
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#define GLOBAL_INT_ENABLE 0x02f0
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/* MMIO bits 0-4 select register */
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#define RRR_EVEN       0x00 /* Shared RAM relocation registers - even and odd */
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/* Used to set the starting address of shared RAM  */
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/* Bits 1 through 7 of this register map to bits 13 through 19 of the shared
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   RAM address.*/
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/* ie: 0x02 sets RAM address to ...ato!  issy su wazzoo !! GODZILLA!!! */
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#define RRR_ODD         0x01
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/* Bits 2 and 3 of this register can be read to determine shared RAM size */
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/* 00 for 8k, 01 for 16k, 10 for 32k, 11 for 64k  */
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#define WRBR_EVEN       0x02    /* Write region base registers - even and odd */
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#define WRBR_ODD        0x03
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#define WWOR_EVEN       0x04    /* Write window open registers - even and odd */
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#define WWOR_ODD        0x05
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#define WWCR_EVEN       0x06   /* Write window close registers - even and odd */
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#define WWCR_ODD        0x07
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/* Interrupt status registers - PC system  - even and odd */
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#define ISRP_EVEN       0x08
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#define TCR_INT    0x10    /* Bit 4 - Timer interrupt.  The TVR_EVEN timer has
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                                                                   expired. */
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#define ERR_INT    0x08    /* Bit 3 - Error interrupt.  The adapter has had an
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                                                            internal error. */
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#define ACCESS_INT 0x04    /* Bit 2 - Access interrupt.  You have attempted to
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                                      write to an invalid area of shared RAM
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                                      or an invalid register within the MMIO. */
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/* In addition, the following bits within ISRP_EVEN can be turned on or off   */
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/* by you to control the interrupt processing:   */
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#define INT_ENABLE 0x40 /* Bit 6 - Interrupt enable.  If 0, no interrupts will
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                                   occur.  If 1, interrupts will occur normally.
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                                                         Normally set to 1.  */
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/* Bit 0 - Primary or alternate adapter.  Set to zero if this adapter is the
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                primary adapter, 1 if this adapter is the alternate adapter. */
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#define ISRP_ODD        0x09
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#define ADAP_CHK_INT 0x40 /* Bit 6 - Adapter check.  the adapter has
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                             encountered a serious problem and has closed
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                             itself.  Whoa.  */
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#define SRB_RESP_INT 0x20 /* Bit 5 - SRB response.  The adapter has accepted
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                             an SRB request and set the return code within
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                             the SRB. */
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#define ASB_FREE_INT 0x10 /* Bit 4 - ASB free.  The adapter has read the ASB
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                             and this area can be safely reused. This interrupt
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                             is only used if your application has set the ASB
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                             free request bit in ISRA_ODD or if an error was
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                             detected in your response. */
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#define ARB_CMD_INT  0x08 /* Bit 3 - ARB command.  The adapter has given you a
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                             command for action.  The command is located in the
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                             ARB area of shared memory. */
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#define SSB_RESP_INT 0x04 /* Bit 2 - SSB response.  The adapter has posted a
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                             response to your SRB (the response is located in
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                             the SSB area of shared memory). */
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/* Bit 1 - Bridge frame forward complete. */
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#define ISRA_EVEN 0x0A /*Interrupt status registers - adapter  - even and odd */
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/* Bit 7 - Internal parity error (on adapter's internal bus) */
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/* Bit 6 - Timer interrupt pending */
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/* Bit 5 - Access interrupt (attempt by adapter to access illegal address) */
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/* Bit 4 - Adapter microcode problem (microcode dead-man timer expired) */
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/* Bit 3 - Adapter processor check status */
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/* Bit 2 - Reserved */
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/* Bit 1 - Adapter hardware interrupt mask (prevents internal interrupts) */
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/* Bit 0 - Adapter software interrupt mask (prevents internal software ints) */
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#define ISRA_ODD        0x0B
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#define CMD_IN_SRB  0x20 /* Bit 5  - Indicates that you have placed a new
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                           command in the SRB and are ready for the adapter to
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                           process the command. */
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#define RESP_IN_ASB 0x10 /* Bit 4 - Indicates that you have placed a response
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                            (an ASB) in the shared RAM which is available for
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                            the adapter's use. */
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/* Bit 3 - Indicates that you are ready to put an SRB in the shared RAM, but
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        that a previous command is still pending.  The adapter will then
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        interrupt you when the previous command is completed */
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/* Bit 2 - Indicates that you are ready to put an ASB in the shared RAM, but
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        that a previous ASB is still pending.  The adapter will then interrupt
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        you when the previous ASB is copied.  */
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#define ARB_FREE 0x2
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#define SSB_FREE 0x1
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#define TCR_EVEN        0x0C    /* Timer control registers - even and odd */
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#define TCR_ODD         0x0D
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#define TVR_EVEN        0x0E    /* Timer value registers - even and odd */
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#define TVR_ODD         0x0F
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#define SRPR_EVEN       0x18    /* Shared RAM paging registers - even and odd */
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#define SRPR_ENABLE_PAGING 0xc0
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#define SRPR_ODD        0x19    /* Not used. */
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#define TOKREAD         0x60
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#define TOKOR           0x40
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#define TOKAND          0x20
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#define TOKWRITE        0x00
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/* MMIO bits 5-6 select operation */
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/* 00 is used to write to a register */
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/* 01 is used to bitwise AND a byte with a register */
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/* 10 is used to bitwise OR a byte with a register  */
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/* 11 is used to read from a register */
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/* MMIO bits 7-8 select area of interest.. see below */
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/* 00 selects attachment control area. */
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/* 01 is reserved. */
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/* 10 selects adapter identification area A containing the adapter encoded
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        address. */
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/* 11 selects the adapter identification area B containing test patterns. */
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#define PCCHANNELID 5049434F3631313039393020
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#define MCCHANNELID 4D4152533633583435313820
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#define ACA_OFFSET 0x1e00
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#define ACA_SET 0x40
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#define ACA_RESET 0x20
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#define ACA_RW 0x00
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#ifdef ENABLE_PAGING
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#define SET_PAGE(x) (writeb((x), ti->mmio + ACA_OFFSET+ ACA_RW + SRPR_EVEN))
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#else
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#define SET_PAGE(x)
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#endif
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/* do_tok_int possible values */
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#define FIRST_INT 1
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#define NOT_FIRST 2
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typedef enum {  CLOSED, OPEN } open_state;
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//staic const char *printstate[] = { "CLOSED","OPEN"};
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struct tok_info {
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        unsigned char irq;
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        void *mmio;
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        unsigned char hw_address[32];
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        unsigned char adapter_type;
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        unsigned char data_rate;
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        unsigned char token_release;
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        unsigned char avail_shared_ram;
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        unsigned char shared_ram_paging;
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        unsigned char turbo;
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        unsigned short dhb_size4mb;
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        unsigned short rbuf_len4;
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        unsigned short rbuf_cnt4;
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        unsigned short maxmtu4;
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        unsigned short dhb_size16mb;
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        unsigned short rbuf_len16;
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        unsigned short rbuf_cnt16;
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        unsigned short maxmtu16;
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        /* Additions by David Morris       */
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        unsigned char do_tok_int;
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        wait_queue_head_t wait_for_reset;
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        unsigned char sram_base;
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        /* Additions by Peter De Schrijver */
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        unsigned char page_mask;          /* mask to select RAM page to Map*/
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        unsigned char mapped_ram_size;    /* size of RAM page */
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        __u32 sram_virt;                  /* Shared memory base address */
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        __u32 init_srb;               /* Initial System Request Block address */
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        __u32 srb;                        /* System Request Block address */
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        __u32 ssb;                        /* System Status Block address */
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        __u32 arb;                        /* Adapter Request Block address */
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        __u32 asb;                        /* Adapter Status Block address */
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        __u8  init_srb_page;
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        __u8  srb_page;
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        __u8  ssb_page;
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        __u8  arb_page;
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        __u8  asb_page;
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        unsigned short exsap_station_id;
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        unsigned short global_int_enable;
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        struct sk_buff *current_skb;
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        struct net_device_stats tr_stats;
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        unsigned char auto_speedsave;
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        open_state                      open_status, sap_status;
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        enum {MANUAL, AUTOMATIC}        open_mode;
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        enum {FAIL, RESTART, REOPEN}    open_action;
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        enum {NO, YES}                  open_failure;
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        unsigned char readlog_pending;
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        unsigned short adapter_int_enable; /* Adapter-specific int enable */
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        struct timer_list tr_timer;
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        unsigned char ring_speed;
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        spinlock_t lock;                /* SMP protection */
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};
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/* token ring adapter commands */
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#define DIR_INTERRUPT           0x00 /* struct srb_interrupt */
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#define DIR_MOD_OPEN_PARAMS     0x01
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#define DIR_OPEN_ADAPTER        0x03 /* struct dir_open_adapter */
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#define DIR_CLOSE_ADAPTER       0x04
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#define DIR_SET_GRP_ADDR        0x06
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#define DIR_SET_FUNC_ADDR       0x07 /* struct srb_set_funct_addr */
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#define DIR_READ_LOG            0x08 /* struct srb_read_log */
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#define DLC_OPEN_SAP            0x15 /* struct dlc_open_sap */
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#define DLC_CLOSE_SAP           0x16
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#define DATA_LOST               0x20 /* struct asb_rec */
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#define REC_DATA                0x81 /* struct arb_rec_req */
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#define XMIT_DATA_REQ           0x82 /* struct arb_xmit_req */
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#define DLC_STATUS              0x83 /* struct arb_dlc_status */
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#define RING_STAT_CHANGE        0x84 /* struct dlc_open_sap ??? */
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/* DIR_OPEN_ADAPTER options */
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#define OPEN_PASS_BCON_MAC 0x0100
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#define NUM_RCV_BUF 2
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#define RCV_BUF_LEN 1024
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#define DHB_LENGTH 2048
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#define NUM_DHB 2
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#define DLC_MAX_SAP 2
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#define DLC_MAX_STA 1
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/* DLC_OPEN_SAP options */
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#define MAX_I_FIELD 0x0088
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#define SAP_OPEN_IND_SAP 0x04
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#define SAP_OPEN_PRIORITY 0x20
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#define SAP_OPEN_STATION_CNT 0x1
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#define XMIT_DIR_FRAME 0x0A
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#define XMIT_UI_FRAME  0x0d
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#define XMIT_XID_CMD   0x0e
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#define XMIT_TEST_CMD  0x11
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/* srb close return code */
258
#define SIGNAL_LOSS  0x8000
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#define HARD_ERROR   0x4000
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#define XMIT_BEACON  0x1000
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#define LOBE_FAULT   0x0800
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#define AUTO_REMOVAL 0x0400
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#define REMOVE_RECV  0x0100
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#define LOG_OVERFLOW 0x0080
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#define RING_RECOVER 0x0020
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267
struct srb_init_response {
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        unsigned char command;
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        unsigned char init_status;
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        unsigned char init_status_2;
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        unsigned char reserved[3];
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        __u16 bring_up_code;
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        __u16 encoded_address;
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        __u16 level_address;
275
        __u16 adapter_address;
276
        __u16 parms_address;
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        __u16 mac_address;
278
};
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280
struct dir_open_adapter {
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        unsigned char command;
282
        char reserved[7];
283
        __u16 open_options;
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        unsigned char node_address[6];
285
        unsigned char group_address[4];
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        unsigned char funct_address[4];
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        __u16 num_rcv_buf;
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        __u16 rcv_buf_len;
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        __u16 dhb_length;
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        unsigned char num_dhb;
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        char reserved2;
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        unsigned char dlc_max_sap;
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        unsigned char dlc_max_sta;
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        unsigned char dlc_max_gsap;
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        unsigned char dlc_max_gmem;
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        unsigned char dlc_t1_tick_1;
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        unsigned char dlc_t2_tick_1;
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        unsigned char dlc_ti_tick_1;
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        unsigned char dlc_t1_tick_2;
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        unsigned char dlc_t2_tick_2;
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        unsigned char dlc_ti_tick_2;
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        unsigned char product_id[18];
303
};
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305
struct dlc_open_sap {
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        unsigned char command;
307
        unsigned char reserved1;
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        unsigned char ret_code;
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        unsigned char reserved2;
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        __u16 station_id;
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        unsigned char timer_t1;
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        unsigned char timer_t2;
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        unsigned char timer_ti;
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        unsigned char maxout;
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        unsigned char maxin;
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        unsigned char maxout_incr;
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        unsigned char max_retry_count;
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        unsigned char gsap_max_mem;
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        __u16 max_i_field;
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        unsigned char sap_value;
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        unsigned char sap_options;
322
        unsigned char station_count;
323
        unsigned char sap_gsap_mem;
324
        unsigned char gsap[0];
325
};
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327
struct srb_xmit {
328
        unsigned char command;
329
        unsigned char cmd_corr;
330
        unsigned char ret_code;
331
        unsigned char reserved1;
332
        __u16 station_id;
333
};
334
 
335
struct arb_rec_req {
336
        unsigned char command;
337
        unsigned char reserved1[3];
338
        __u16 station_id;
339
        __u16 rec_buf_addr;
340
        unsigned char lan_hdr_len;
341
        unsigned char dlc_hdr_len;
342
        __u16 frame_len;
343
        unsigned char msg_type;
344
};
345
 
346
struct asb_rec {
347
        unsigned char command;
348
        unsigned char reserved1;
349
        unsigned char ret_code;
350
        unsigned char reserved2;
351
        __u16 station_id;
352
        __u16 rec_buf_addr;
353
};
354
 
355
struct rec_buf {
356
        unsigned char reserved1[2];
357
        __u16 buf_ptr;
358
        unsigned char reserved2;
359
        unsigned char receive_fs;
360
        __u16 buf_len;
361
        unsigned char data[0];
362
};
363
 
364
struct srb_set_funct_addr {
365
        unsigned char command;
366
        unsigned char reserved1;
367
        unsigned char ret_code;
368
        unsigned char reserved2[3];
369
        unsigned char funct_address[4];
370
};
371
 
372
#endif