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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 422 | giacomo | 1 | /* $Id: scc.h,v 1.1 2004-01-28 15:26:31 giacomo Exp $ */ |
| 2 | |||
| 3 | #ifndef _SCC_H |
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| 4 | #define _SCC_H |
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| 5 | |||
| 6 | #include <linux/config.h> |
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| 7 | |||
| 8 | /* selection of hardware types */ |
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| 9 | |||
| 10 | #define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */ |
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| 11 | #define EAGLE 0x01 /* hardware type for EAGLE card */ |
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| 12 | #define PC100 0x02 /* hardware type for PC100 card */ |
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| 13 | #define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */ |
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| 14 | #define DRSI 0x08 /* hardware type for DRSI PC*Packet card */ |
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| 15 | #define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */ |
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| 16 | |||
| 17 | /* DEV ioctl() commands */ |
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| 18 | |||
| 19 | enum SCC_ioctl_cmds { |
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| 20 | SIOCSCCRESERVED = SIOCDEVPRIVATE, |
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| 21 | SIOCSCCCFG, |
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| 22 | SIOCSCCINI, |
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| 23 | SIOCSCCCHANINI, |
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| 24 | SIOCSCCSMEM, |
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| 25 | SIOCSCCGKISS, |
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| 26 | SIOCSCCSKISS, |
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| 27 | SIOCSCCGSTAT, |
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| 28 | SIOCSCCCAL |
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| 29 | }; |
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| 30 | |||
| 31 | /* Device parameter control (from WAMPES) */ |
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| 32 | |||
| 33 | enum L1_params { |
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| 34 | PARAM_DATA, |
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| 35 | PARAM_TXDELAY, |
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| 36 | PARAM_PERSIST, |
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| 37 | PARAM_SLOTTIME, |
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| 38 | PARAM_TXTAIL, |
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| 39 | PARAM_FULLDUP, |
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| 40 | PARAM_SOFTDCD, /* was: PARAM_HW */ |
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| 41 | PARAM_MUTE, /* ??? */ |
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| 42 | PARAM_DTR, |
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| 43 | PARAM_RTS, |
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| 44 | PARAM_SPEED, |
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| 45 | PARAM_ENDDELAY, /* ??? */ |
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| 46 | PARAM_GROUP, |
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| 47 | PARAM_IDLE, |
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| 48 | PARAM_MIN, |
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| 49 | PARAM_MAXKEY, |
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| 50 | PARAM_WAIT, |
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| 51 | PARAM_MAXDEFER, |
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| 52 | PARAM_TX, |
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| 53 | PARAM_HWEVENT = 31, |
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| 54 | PARAM_RETURN = 255 /* reset kiss mode */ |
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| 55 | }; |
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| 56 | |||
| 57 | /* fulldup parameter */ |
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| 58 | |||
| 59 | enum FULLDUP_modes { |
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| 60 | KISS_DUPLEX_HALF, /* normal CSMA operation */ |
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| 61 | KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */ |
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| 62 | KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */ |
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| 63 | KISS_DUPLEX_OPTIMA /* fullduplex, let the protocol layer control the hw */ |
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| 64 | }; |
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| 65 | |||
| 66 | /* misc. parameters */ |
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| 67 | |||
| 68 | #define TIMER_OFF 65535U /* to switch off timers */ |
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| 69 | #define NO_SUCH_PARAM 65534U /* param not implemented */ |
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| 70 | |||
| 71 | /* HWEVENT parameter */ |
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| 72 | |||
| 73 | enum HWEVENT_opts { |
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| 74 | HWEV_DCD_ON, |
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| 75 | HWEV_DCD_OFF, |
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| 76 | HWEV_ALL_SENT |
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| 77 | }; |
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| 78 | |||
| 79 | /* channel grouping */ |
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| 80 | |||
| 81 | #define RXGROUP 0100 /* if set, only tx when all channels clear */ |
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| 82 | #define TXGROUP 0200 /* if set, don't transmit simultaneously */ |
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| 83 | |||
| 84 | /* Tx/Rx clock sources */ |
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| 85 | |||
| 86 | enum CLOCK_sources { |
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| 87 | CLK_DPLL, /* normal halfduplex operation */ |
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| 88 | CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */ |
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| 89 | CLK_DIVIDER, /* Rx = DPLL, Tx = divider (fullduplex with */ |
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| 90 | /* modems without clock regeneration */ |
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| 91 | CLK_BRG /* experimental fullduplex mode with DPLL/BRG for */ |
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| 92 | /* MODEMs without clock recovery */ |
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| 93 | }; |
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| 94 | |||
| 95 | /* Tx state */ |
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| 96 | |||
| 97 | enum TX_state { |
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| 98 | TXS_IDLE, /* Transmitter off, no data pending */ |
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| 99 | TXS_BUSY, /* waiting for permission to send / tailtime */ |
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| 100 | TXS_ACTIVE, /* Transmitter on, sending data */ |
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| 101 | TXS_NEWFRAME, /* reset CRC and send (next) frame */ |
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| 102 | TXS_IDLE2, /* Transmitter on, no data pending */ |
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| 103 | TXS_WAIT, /* Waiting for Mintime to expire */ |
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| 104 | TXS_TIMEOUT /* We had a transmission timeout */ |
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| 105 | }; |
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| 106 | |||
| 107 | typedef unsigned long io_port; /* type definition for an 'io port address' */ |
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| 108 | |||
| 109 | /* SCC statistical information */ |
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| 110 | |||
| 111 | struct scc_stat { |
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| 112 | long rxints; /* Receiver interrupts */ |
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| 113 | long txints; /* Transmitter interrupts */ |
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| 114 | long exints; /* External/status interrupts */ |
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| 115 | long spints; /* Special receiver interrupts */ |
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| 116 | |||
| 117 | long txframes; /* Packets sent */ |
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| 118 | long rxframes; /* Number of Frames Actually Received */ |
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| 119 | long rxerrs; /* CRC Errors */ |
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| 120 | long txerrs; /* KISS errors */ |
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| 121 | |||
| 122 | unsigned int nospace; /* "Out of buffers" */ |
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| 123 | unsigned int rx_over; /* Receiver Overruns */ |
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| 124 | unsigned int tx_under; /* Transmitter Underruns */ |
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| 125 | |||
| 126 | unsigned int tx_state; /* Transmitter state */ |
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| 127 | int tx_queued; /* tx frames enqueued */ |
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| 128 | |||
| 129 | unsigned int maxqueue; /* allocated tx_buffers */ |
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| 130 | unsigned int bufsize; /* used buffersize */ |
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| 131 | }; |
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| 132 | |||
| 133 | struct scc_modem { |
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| 134 | long speed; /* Line speed, bps */ |
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| 135 | char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */ |
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| 136 | char nrz; /* NRZ instead of NRZI */ |
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| 137 | }; |
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| 138 | |||
| 139 | struct scc_kiss_cmd { |
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| 140 | int command; /* one of the KISS-Commands defined above */ |
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| 141 | unsigned param; /* KISS-Param */ |
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| 142 | }; |
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| 143 | |||
| 144 | struct scc_hw_config { |
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| 145 | io_port data_a; /* data port channel A */ |
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| 146 | io_port ctrl_a; /* control port channel A */ |
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| 147 | io_port data_b; /* data port channel B */ |
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| 148 | io_port ctrl_b; /* control port channel B */ |
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| 149 | io_port vector_latch; /* INTACK-Latch (#) */ |
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| 150 | io_port special; /* special function port */ |
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| 151 | |||
| 152 | int irq; /* irq */ |
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| 153 | long clock; /* clock */ |
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| 154 | char option; /* command for function port */ |
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| 155 | |||
| 156 | char brand; /* hardware type */ |
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| 157 | char escc; /* use ext. features of a 8580/85180/85280 */ |
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| 158 | }; |
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| 159 | |||
| 160 | /* (#) only one INTACK latch allowed. */ |
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| 161 | |||
| 162 | |||
| 163 | struct scc_mem_config { |
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| 164 | unsigned int dummy; |
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| 165 | unsigned int bufsize; |
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| 166 | }; |
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| 167 | |||
| 168 | struct scc_calibrate { |
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| 169 | unsigned int time; |
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| 170 | unsigned char pattern; |
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| 171 | }; |
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| 172 | |||
| 173 | #ifdef __KERNEL__ |
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| 174 | |||
| 175 | enum {TX_OFF, TX_ON}; /* command for scc_key_trx() */ |
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| 176 | |||
| 177 | /* Vector masks in RR2B */ |
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| 178 | |||
| 179 | #define VECTOR_MASK 0x06 |
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| 180 | #define TXINT 0x00 |
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| 181 | #define EXINT 0x02 |
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| 182 | #define RXINT 0x04 |
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| 183 | #define SPINT 0x06 |
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| 184 | |||
| 185 | #ifdef CONFIG_SCC_DELAY |
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| 186 | #define Inb(port) inb_p(port) |
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| 187 | #define Outb(port, val) outb_p(val, port) |
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| 188 | #else |
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| 189 | #define Inb(port) inb(port) |
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| 190 | #define Outb(port, val) outb(val, port) |
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| 191 | #endif |
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| 192 | |||
| 193 | /* SCC channel control structure for KISS */ |
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| 194 | |||
| 195 | struct scc_kiss { |
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| 196 | unsigned char txdelay; /* Transmit Delay 10 ms/cnt */ |
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| 197 | unsigned char persist; /* Persistence (0-255) as a % */ |
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| 198 | unsigned char slottime; /* Delay to wait on persistence hit */ |
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| 199 | unsigned char tailtime; /* Delay after last byte written */ |
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| 200 | unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */ |
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| 201 | unsigned char waittime; /* Waittime before any transmit attempt */ |
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| 202 | unsigned int maxkeyup; /* Maximum time to transmit (seconds) */ |
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| 203 | unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */ |
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| 204 | unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */ |
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| 205 | unsigned int maxdefer; /* Timer for CSMA channel busy limit */ |
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| 206 | unsigned char tx_inhibit; /* Transmit is not allowed when set */ |
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| 207 | unsigned char group; /* Group ID for AX.25 TX interlocking */ |
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| 208 | unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */ |
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| 209 | unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */ |
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| 210 | }; |
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| 211 | |||
| 212 | |||
| 213 | /* SCC channel structure */ |
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| 214 | |||
| 215 | struct scc_channel { |
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| 216 | int init; /* channel exists? */ |
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| 217 | |||
| 218 | struct net_device *dev; /* link to device control structure */ |
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| 219 | struct net_device_stats dev_stat;/* device statistics */ |
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| 220 | |||
| 221 | char brand; /* manufacturer of the board */ |
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| 222 | long clock; /* used clock */ |
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| 223 | |||
| 224 | io_port ctrl; /* I/O address of CONTROL register */ |
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| 225 | io_port data; /* I/O address of DATA register */ |
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| 226 | io_port special; /* I/O address of special function port */ |
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| 227 | int irq; /* Number of Interrupt */ |
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| 228 | |||
| 229 | char option; |
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| 230 | char enhanced; /* Enhanced SCC support */ |
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| 231 | |||
| 232 | unsigned char wreg[16]; /* Copy of last written value in WRx */ |
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| 233 | unsigned char status; /* Copy of R0 at last external interrupt */ |
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| 234 | unsigned char dcd; /* DCD status */ |
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| 235 | |||
| 236 | struct scc_kiss kiss; /* control structure for KISS params */ |
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| 237 | struct scc_stat stat; /* statistical information */ |
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| 238 | struct scc_modem modem; /* modem information */ |
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| 239 | |||
| 240 | struct sk_buff_head tx_queue; /* next tx buffer */ |
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| 241 | struct sk_buff *rx_buff; /* pointer to frame currently received */ |
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| 242 | struct sk_buff *tx_buff; /* pointer to frame currently transmitted */ |
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| 243 | |||
| 244 | /* Timer */ |
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| 245 | struct timer_list tx_t; /* tx timer for this channel */ |
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| 246 | struct timer_list tx_wdog; /* tx watchdogs */ |
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| 247 | |||
| 248 | /* Channel lock */ |
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| 249 | spinlock_t lock; /* Channel guard lock */ |
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| 250 | }; |
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| 251 | |||
| 252 | #endif /* defined(__KERNEL__) */ |
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| 253 | #endif /* defined(_SCC_H) */ |