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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 467 | giacomo | 1 | /* |
| 2 | * drivers/video/clgenfb.h - Cirrus Logic chipset constants |
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| 3 | * |
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| 4 | * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> |
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| 5 | * |
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| 6 | * Original clgenfb author: Frank Neumann |
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| 7 | * |
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| 8 | * Based on retz3fb.c and clgen.c: |
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| 9 | * Copyright (C) 1997 Jes Sorensen |
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| 10 | * Copyright (C) 1996 Frank Neumann |
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| 11 | * |
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| 12 | *************************************************************** |
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| 13 | * |
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| 14 | * Format this code with GNU indent '-kr -i8 -pcs' options. |
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| 15 | * |
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| 16 | * This file is subject to the terms and conditions of the GNU General Public |
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| 17 | * License. See the file COPYING in the main directory of this archive |
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| 18 | * for more details. |
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| 19 | * |
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| 20 | */ |
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| 21 | |||
| 22 | #ifndef __CLGENFB_H__ |
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| 23 | #define __CLGENFB_H__ |
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| 24 | |||
| 25 | /* OLD COMMENT: definitions for Piccolo/SD64 VGA controller chip */ |
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| 26 | /* OLD COMMENT: these definitions might most of the time also work */ |
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| 27 | /* OLD COMMENT: for other CL-GD542x/543x based boards.. */ |
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| 28 | |||
| 29 | /*** External/General Registers ***/ |
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| 30 | #define CL_POS102 0x102 /* POS102 register */ |
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| 31 | #define CL_VSSM 0x46e8 /* Adapter Sleep */ |
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| 32 | #define CL_VSSM2 0x3c3 /* Motherboard Sleep */ |
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| 33 | |||
| 34 | /*** VGA Sequencer Registers ***/ |
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| 35 | #define CL_SEQR0 0x0 /* Reset */ |
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| 36 | /* the following are from the "extension registers" group */ |
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| 37 | #define CL_SEQR6 0x6 /* Unlock ALL Extensions */ |
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| 38 | #define CL_SEQR7 0x7 /* Extended Sequencer Mode */ |
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| 39 | #define CL_SEQR8 0x8 /* EEPROM Control */ |
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| 40 | #define CL_SEQR9 0x9 /* Scratch Pad 0 (do not access!) */ |
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| 41 | #define CL_SEQRA 0xa /* Scratch Pad 1 (do not access!) */ |
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| 42 | #define CL_SEQRB 0xb /* VCLK0 Numerator */ |
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| 43 | #define CL_SEQRC 0xc /* VCLK1 Numerator */ |
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| 44 | #define CL_SEQRD 0xd /* VCLK2 Numerator */ |
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| 45 | #define CL_SEQRE 0xe /* VCLK3 Numerator */ |
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| 46 | #define CL_SEQRF 0xf /* DRAM Control */ |
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| 47 | #define CL_SEQR10 0x10 /* Graphics Cursor X Position */ |
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| 48 | #define CL_SEQR11 0x11 /* Graphics Cursor Y Position */ |
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| 49 | #define CL_SEQR12 0x12 /* Graphics Cursor Attributes */ |
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| 50 | #define CL_SEQR13 0x13 /* Graphics Cursor Pattern Address Offset */ |
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| 51 | #define CL_SEQR14 0x14 /* Scratch Pad 2 (CL-GD5426/'28 Only) (do not access!) */ |
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| 52 | #define CL_SEQR15 0x15 /* Scratch Pad 3 (CL-GD5426/'28 Only) (do not access!) */ |
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| 53 | #define CL_SEQR16 0x16 /* Performance Tuning (CL-GD5424/'26/'28 Only) */ |
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| 54 | #define CL_SEQR17 0x17 /* Configuration ReadBack and Extended Control (CL-GF5428 Only) */ |
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| 55 | #define CL_SEQR18 0x18 /* Signature Generator Control (Not CL-GD5420) */ |
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| 56 | #define CL_SEQR19 0x19 /* Signature Generator Result Low Byte (Not CL-GD5420) */ |
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| 57 | #define CL_SEQR1A 0x1a /* Signature Generator Result High Byte (Not CL-GD5420) */ |
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| 58 | #define CL_SEQR1B 0x1b /* VCLK0 Denominator and Post-Scalar Value */ |
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| 59 | #define CL_SEQR1C 0x1c /* VCLK1 Denominator and Post-Scalar Value */ |
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| 60 | #define CL_SEQR1D 0x1d /* VCLK2 Denominator and Post-Scalar Value */ |
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| 61 | #define CL_SEQR1E 0x1e /* VCLK3 Denominator and Post-Scalar Value */ |
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| 62 | #define CL_SEQR1F 0x1f /* BIOS ROM write enable and MCLK Select */ |
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| 63 | |||
| 64 | /*** CRT Controller Registers ***/ |
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| 65 | #define CL_CRT22 0x22 /* Graphics Data Latches ReadBack */ |
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| 66 | #define CL_CRT24 0x24 /* Attribute Controller Toggle ReadBack */ |
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| 67 | #define CL_CRT26 0x26 /* Attribute Controller Index ReadBack */ |
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| 68 | /* the following are from the "extension registers" group */ |
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| 69 | #define CL_CRT19 0x19 /* Interlace End */ |
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| 70 | #define CL_CRT1A 0x1a /* Interlace Control */ |
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| 71 | #define CL_CRT1B 0x1b /* Extended Display Controls */ |
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| 72 | #define CL_CRT1C 0x1c /* Sync adjust and genlock register */ |
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| 73 | #define CL_CRT1D 0x1d /* Overlay Extended Control register */ |
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| 74 | #define CL_CRT25 0x25 /* Part Status Register */ |
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| 75 | #define CL_CRT27 0x27 /* ID Register */ |
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| 76 | #define CL_CRT51 0x51 /* P4 disable "flicker fixer" */ |
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| 77 | |||
| 78 | /*** Graphics Controller Registers ***/ |
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| 79 | /* the following are from the "extension registers" group */ |
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| 80 | #define CL_GR9 0x9 /* Offset Register 0 */ |
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| 81 | #define CL_GRA 0xa /* Offset Register 1 */ |
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| 82 | #define CL_GRB 0xb /* Graphics Controller Mode Extensions */ |
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| 83 | #define CL_GRC 0xc /* Color Key (CL-GD5424/'26/'28 Only) */ |
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| 84 | #define CL_GRD 0xd /* Color Key Mask (CL-GD5424/'26/'28 Only) */ |
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| 85 | #define CL_GRE 0xe /* Miscellaneous Control (Cl-GD5428 Only) */ |
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| 86 | #define CL_GRF 0xf /* Display Compression Control register */ |
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| 87 | #define CL_GR10 0x10 /* 16-bit Pixel BG Color High Byte (Not CL-GD5420) */ |
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| 88 | #define CL_GR11 0x11 /* 16-bit Pixel FG Color High Byte (Not CL-GD5420) */ |
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| 89 | #define CL_GR12 0x12 /* Background Color Byte 2 Register */ |
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| 90 | #define CL_GR13 0x13 /* Foreground Color Byte 2 Register */ |
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| 91 | #define CL_GR14 0x14 /* Background Color Byte 3 Register */ |
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| 92 | #define CL_GR15 0x15 /* Foreground Color Byte 3 Register */ |
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| 93 | /* the following are CL-GD5426/'28 specific blitter registers */ |
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| 94 | #define CL_GR20 0x20 /* BLT Width Low */ |
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| 95 | #define CL_GR21 0x21 /* BLT Width High */ |
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| 96 | #define CL_GR22 0x22 /* BLT Height Low */ |
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| 97 | #define CL_GR23 0x23 /* BLT Height High */ |
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| 98 | #define CL_GR24 0x24 /* BLT Destination Pitch Low */ |
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| 99 | #define CL_GR25 0x25 /* BLT Destination Pitch High */ |
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| 100 | #define CL_GR26 0x26 /* BLT Source Pitch Low */ |
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| 101 | #define CL_GR27 0x27 /* BLT Source Pitch High */ |
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| 102 | #define CL_GR28 0x28 /* BLT Destination Start Low */ |
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| 103 | #define CL_GR29 0x29 /* BLT Destination Start Mid */ |
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| 104 | #define CL_GR2A 0x2a /* BLT Destination Start High */ |
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| 105 | #define CL_GR2C 0x2c /* BLT Source Start Low */ |
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| 106 | #define CL_GR2D 0x2d /* BLT Source Start Mid */ |
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| 107 | #define CL_GR2E 0x2e /* BLT Source Start High */ |
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| 108 | #define CL_GR2F 0x2f /* Picasso IV Blitter compat mode..? */ |
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| 109 | #define CL_GR30 0x30 /* BLT Mode */ |
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| 110 | #define CL_GR31 0x31 /* BLT Start/Status */ |
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| 111 | #define CL_GR32 0x32 /* BLT Raster Operation */ |
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| 112 | #define CL_GR33 0x33 /* another P4 "compat" register.. */ |
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| 113 | #define CL_GR34 0x34 /* Transparent Color Select Low */ |
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| 114 | #define CL_GR35 0x35 /* Transparent Color Select High */ |
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| 115 | #define CL_GR38 0x38 /* Source Transparent Color Mask Low */ |
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| 116 | #define CL_GR39 0x39 /* Source Transparent Color Mask High */ |
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| 117 | |||
| 118 | /*** Attribute Controller Registers ***/ |
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| 119 | #define CL_AR33 0x33 /* The "real" Pixel Panning register (?) */ |
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| 120 | #define CL_AR34 0x34 /* TEST */ |
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| 121 | |||
| 122 | #endif /* __CLGENFB_H__ */ |