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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 467 | giacomo | 1 | /* |
| 2 | * linux/include/video/tx3912.h |
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| 3 | * |
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| 4 | * Copyright (C) 2001 Steven Hill (sjhill@realitydiluted.com) |
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| 5 | * |
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| 6 | * This file is subject to the terms and conditions of the GNU General Public |
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| 7 | * License. See the file COPYING in the main directory of this archive for |
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| 8 | * more details. |
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| 9 | * |
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| 10 | * Includes for TMPR3912/05 and PR31700 LCD controller registers |
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| 11 | */ |
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| 12 | #include <asm/tx3912.h> |
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| 13 | |||
| 14 | #define VidCtrl1 REG_AT(0x028) |
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| 15 | #define VidCtrl2 REG_AT(0x02C) |
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| 16 | #define VidCtrl3 REG_AT(0x030) |
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| 17 | #define VidCtrl4 REG_AT(0x034) |
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| 18 | #define VidCtrl5 REG_AT(0x038) |
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| 19 | #define VidCtrl6 REG_AT(0x03C) |
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| 20 | #define VidCtrl7 REG_AT(0x040) |
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| 21 | #define VidCtrl8 REG_AT(0x044) |
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| 22 | #define VidCtrl9 REG_AT(0x048) |
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| 23 | #define VidCtrl10 REG_AT(0x04C) |
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| 24 | #define VidCtrl11 REG_AT(0x050) |
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| 25 | #define VidCtrl12 REG_AT(0x054) |
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| 26 | #define VidCtrl13 REG_AT(0x058) |
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| 27 | #define VidCtrl14 REG_AT(0x05C) |
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| 28 | |||
| 29 | /* Video Control 1 Register */ |
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| 30 | #define LINECNT 0xffc00000 |
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| 31 | #define LINECNT_SHIFT 22 |
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| 32 | #define LOADDLY BIT(21) |
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| 33 | #define BAUDVAL (BIT(20) | BIT(19) | BIT(18) | BIT(17) | BIT(16)) |
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| 34 | #define BAUDVAL_SHIFT 16 |
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| 35 | #define VIDDONEVAL (BIT(15) | BIT(14) | BIT(13) | BIT(12) | BIT(11) | BIT(10) | BIT(9)) |
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| 36 | #define VIDDONEVAL_SHIFT 9 |
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| 37 | #define ENFREEZEFRAME BIT(8) |
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| 38 | #define TX3912_VIDCTRL1_BITSEL_MASK 0x000000c0 |
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| 39 | #define TX3912_VIDCTRL1_2BIT_GRAY 0x00000040 |
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| 40 | #define TX3912_VIDCTRL1_4BIT_GRAY 0x00000080 |
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| 41 | #define TX3912_VIDCTRL1_8BIT_COLOR 0x000000c0 |
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| 42 | #define BITSEL_SHIFT 6 |
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| 43 | #define DISPSPLIT BIT(5) |
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| 44 | #define DISP8 BIT(4) |
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| 45 | #define DFMODE BIT(3) |
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| 46 | #define INVVID BIT(2) |
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| 47 | #define DISPON BIT(1) |
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| 48 | #define ENVID BIT(0) |
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| 49 | |||
| 50 | /* Video Control 2 Register */ |
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| 51 | #define VIDRATE_MASK 0xffc00000 |
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| 52 | #define VIDRATE_SHIFT 22 |
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| 53 | #define HORZVAL_MASK 0x001ff000 |
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| 54 | #define HORZVAL_SHIFT 12 |
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| 55 | #define LINEVAL_MASK 0x000001ff |
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| 56 | |||
| 57 | /* Video Control 3 Register */ |
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| 58 | #define TX3912_VIDCTRL3_VIDBANK_MASK 0xfff00000 |
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| 59 | #define TX3912_VIDCTRL3_VIDBASEHI_MASK 0x000ffff0 |
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| 60 | |||
| 61 | /* Video Control 4 Register */ |
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| 62 | #define TX3912_VIDCTRL4_VIDBASELO_MASK 0x000ffff0 |