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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 467 | giacomo | 1 | /* |
| 2 | * linux/include/video/vga.h -- standard VGA chipset interaction |
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| 3 | * |
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| 4 | * Copyright 1999 Jeff Garzik <jgarzik@pobox.com> |
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| 5 | * |
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| 6 | * Copyright history from vga16fb.c: |
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| 7 | * Copyright 1999 Ben Pfaff and Petr Vandrovec |
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| 8 | * Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm |
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| 9 | * Based on VESA framebuffer (c) 1998 Gerd Knorr |
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| 10 | * |
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| 11 | * This file is subject to the terms and conditions of the GNU General |
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| 12 | * Public License. See the file COPYING in the main directory of this |
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| 13 | * archive for more details. |
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| 14 | * |
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| 15 | */ |
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| 16 | |||
| 17 | #ifndef __linux_video_vga_h__ |
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| 18 | #define __linux_video_vga_h__ |
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| 19 | |||
| 20 | #include <linux/config.h> |
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| 21 | #include <linux/types.h> |
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| 22 | #include <asm/io.h> |
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| 23 | #ifndef CONFIG_AMIGA |
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| 24 | #include <asm/vga.h> |
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| 25 | #else |
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| 26 | /* |
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| 27 | * FIXME |
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| 28 | * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space |
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| 29 | * for MMIO accesses. This should make clgenfb work again on Amiga |
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| 30 | */ |
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| 31 | #define inb_p(port) 0 |
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| 32 | #define inw_p(port) 0 |
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| 33 | #define outb_p(port, val) do { } while (0) |
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| 34 | #define outw(port, val) do { } while (0) |
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| 35 | #define readb z_readb |
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| 36 | #define writeb z_writeb |
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| 37 | #define writew z_writew |
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| 38 | #endif |
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| 39 | #include <asm/byteorder.h> |
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| 40 | |||
| 41 | |||
| 42 | /* Some of the code below is taken from SVGAlib. The original, |
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| 43 | unmodified copyright notice for that code is below. */ |
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| 44 | /* VGAlib version 1.2 - (c) 1993 Tommy Frandsen */ |
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| 45 | /* */ |
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| 46 | /* This library is free software; you can redistribute it and/or */ |
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| 47 | /* modify it without any restrictions. This library is distributed */ |
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| 48 | /* in the hope that it will be useful, but without any warranty. */ |
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| 49 | |||
| 50 | /* Multi-chipset support Copyright 1993 Harm Hanemaayer */ |
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| 51 | /* partially copyrighted (C) 1993 by Hartmut Schirmer */ |
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| 52 | |||
| 53 | /* VGA data register ports */ |
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| 54 | #define VGA_CRT_DC 0x3D5 /* CRT Controller Data Register - color emulation */ |
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| 55 | #define VGA_CRT_DM 0x3B5 /* CRT Controller Data Register - mono emulation */ |
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| 56 | #define VGA_ATT_R 0x3C1 /* Attribute Controller Data Read Register */ |
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| 57 | #define VGA_ATT_W 0x3C0 /* Attribute Controller Data Write Register */ |
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| 58 | #define VGA_GFX_D 0x3CF /* Graphics Controller Data Register */ |
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| 59 | #define VGA_SEQ_D 0x3C5 /* Sequencer Data Register */ |
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| 60 | #define VGA_MIS_R 0x3CC /* Misc Output Read Register */ |
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| 61 | #define VGA_MIS_W 0x3C2 /* Misc Output Write Register */ |
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| 62 | #define VGA_FTC_R 0x3CA /* Feature Control Read Register */ |
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| 63 | #define VGA_IS1_RC 0x3DA /* Input Status Register 1 - color emulation */ |
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| 64 | #define VGA_IS1_RM 0x3BA /* Input Status Register 1 - mono emulation */ |
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| 65 | #define VGA_PEL_D 0x3C9 /* PEL Data Register */ |
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| 66 | #define VGA_PEL_MSK 0x3C6 /* PEL mask register */ |
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| 67 | |||
| 68 | /* EGA-specific registers */ |
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| 69 | #define EGA_GFX_E0 0x3CC /* Graphics enable processor 0 */ |
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| 70 | #define EGA_GFX_E1 0x3CA /* Graphics enable processor 1 */ |
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| 71 | |||
| 72 | /* VGA index register ports */ |
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| 73 | #define VGA_CRT_IC 0x3D4 /* CRT Controller Index - color emulation */ |
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| 74 | #define VGA_CRT_IM 0x3B4 /* CRT Controller Index - mono emulation */ |
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| 75 | #define VGA_ATT_IW 0x3C0 /* Attribute Controller Index & Data Write Register */ |
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| 76 | #define VGA_GFX_I 0x3CE /* Graphics Controller Index */ |
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| 77 | #define VGA_SEQ_I 0x3C4 /* Sequencer Index */ |
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| 78 | #define VGA_PEL_IW 0x3C8 /* PEL Write Index */ |
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| 79 | #define VGA_PEL_IR 0x3C7 /* PEL Read Index */ |
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| 80 | |||
| 81 | /* standard VGA indexes max counts */ |
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| 82 | #define VGA_CRT_C 0x19 /* Number of CRT Controller Registers */ |
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| 83 | #define VGA_ATT_C 0x15 /* Number of Attribute Controller Registers */ |
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| 84 | #define VGA_GFX_C 0x09 /* Number of Graphics Controller Registers */ |
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| 85 | #define VGA_SEQ_C 0x05 /* Number of Sequencer Registers */ |
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| 86 | #define VGA_MIS_C 0x01 /* Number of Misc Output Register */ |
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| 87 | |||
| 88 | /* VGA misc register bit masks */ |
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| 89 | #define VGA_MIS_COLOR 0x01 |
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| 90 | #define VGA_MIS_ENB_MEM_ACCESS 0x02 |
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| 91 | #define VGA_MIS_DCLK_28322_720 0x04 |
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| 92 | #define VGA_MIS_ENB_PLL_LOAD (0x04 | 0x08) |
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| 93 | #define VGA_MIS_SEL_HIGH_PAGE 0x20 |
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| 94 | |||
| 95 | /* VGA CRT controller register indices */ |
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| 96 | #define VGA_CRTC_H_TOTAL 0 |
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| 97 | #define VGA_CRTC_H_DISP 1 |
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| 98 | #define VGA_CRTC_H_BLANK_START 2 |
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| 99 | #define VGA_CRTC_H_BLANK_END 3 |
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| 100 | #define VGA_CRTC_H_SYNC_START 4 |
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| 101 | #define VGA_CRTC_H_SYNC_END 5 |
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| 102 | #define VGA_CRTC_V_TOTAL 6 |
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| 103 | #define VGA_CRTC_OVERFLOW 7 |
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| 104 | #define VGA_CRTC_PRESET_ROW 8 |
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| 105 | #define VGA_CRTC_MAX_SCAN 9 |
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| 106 | #define VGA_CRTC_CURSOR_START 0x0A |
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| 107 | #define VGA_CRTC_CURSOR_END 0x0B |
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| 108 | #define VGA_CRTC_START_HI 0x0C |
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| 109 | #define VGA_CRTC_START_LO 0x0D |
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| 110 | #define VGA_CRTC_CURSOR_HI 0x0E |
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| 111 | #define VGA_CRTC_CURSOR_LO 0x0F |
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| 112 | #define VGA_CRTC_V_SYNC_START 0x10 |
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| 113 | #define VGA_CRTC_V_SYNC_END 0x11 |
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| 114 | #define VGA_CRTC_V_DISP_END 0x12 |
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| 115 | #define VGA_CRTC_OFFSET 0x13 |
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| 116 | #define VGA_CRTC_UNDERLINE 0x14 |
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| 117 | #define VGA_CRTC_V_BLANK_START 0x15 |
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| 118 | #define VGA_CRTC_V_BLANK_END 0x16 |
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| 119 | #define VGA_CRTC_MODE 0x17 |
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| 120 | #define VGA_CRTC_LINE_COMPARE 0x18 |
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| 121 | #define VGA_CRTC_REGS VGA_CRT_C |
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| 122 | |||
| 123 | /* VGA CRT controller bit masks */ |
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| 124 | #define VGA_CR11_LOCK_CR0_CR7 0x80 /* lock writes to CR0 - CR7 */ |
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| 125 | #define VGA_CR17_H_V_SIGNALS_ENABLED 0x80 |
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| 126 | |||
| 127 | /* VGA attribute controller register indices */ |
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| 128 | #define VGA_ATC_PALETTE0 0x00 |
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| 129 | #define VGA_ATC_PALETTE1 0x01 |
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| 130 | #define VGA_ATC_PALETTE2 0x02 |
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| 131 | #define VGA_ATC_PALETTE3 0x03 |
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| 132 | #define VGA_ATC_PALETTE4 0x04 |
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| 133 | #define VGA_ATC_PALETTE5 0x05 |
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| 134 | #define VGA_ATC_PALETTE6 0x06 |
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| 135 | #define VGA_ATC_PALETTE7 0x07 |
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| 136 | #define VGA_ATC_PALETTE8 0x08 |
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| 137 | #define VGA_ATC_PALETTE9 0x09 |
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| 138 | #define VGA_ATC_PALETTEA 0x0A |
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| 139 | #define VGA_ATC_PALETTEB 0x0B |
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| 140 | #define VGA_ATC_PALETTEC 0x0C |
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| 141 | #define VGA_ATC_PALETTED 0x0D |
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| 142 | #define VGA_ATC_PALETTEE 0x0E |
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| 143 | #define VGA_ATC_PALETTEF 0x0F |
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| 144 | #define VGA_ATC_MODE 0x10 |
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| 145 | #define VGA_ATC_OVERSCAN 0x11 |
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| 146 | #define VGA_ATC_PLANE_ENABLE 0x12 |
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| 147 | #define VGA_ATC_PEL 0x13 |
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| 148 | #define VGA_ATC_COLOR_PAGE 0x14 |
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| 149 | |||
| 150 | #define VGA_AR_ENABLE_DISPLAY 0x20 |
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| 151 | |||
| 152 | /* VGA sequencer register indices */ |
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| 153 | #define VGA_SEQ_RESET 0x00 |
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| 154 | #define VGA_SEQ_CLOCK_MODE 0x01 |
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| 155 | #define VGA_SEQ_PLANE_WRITE 0x02 |
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| 156 | #define VGA_SEQ_CHARACTER_MAP 0x03 |
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| 157 | #define VGA_SEQ_MEMORY_MODE 0x04 |
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| 158 | |||
| 159 | /* VGA sequencer register bit masks */ |
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| 160 | #define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */ |
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| 161 | #define VGA_SR01_SCREEN_OFF 0x20 /* bit 5: Screen is off */ |
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| 162 | #define VGA_SR02_ALL_PLANES 0x0F /* bits 3-0: enable access to all planes */ |
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| 163 | #define VGA_SR04_EXT_MEM 0x02 /* bit 1: allows complete mem access to 256K */ |
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| 164 | #define VGA_SR04_SEQ_MODE 0x04 /* bit 2: directs system to use a sequential addressing mode */ |
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| 165 | #define VGA_SR04_CHN_4M 0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */ |
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| 166 | |||
| 167 | /* VGA graphics controller register indices */ |
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| 168 | #define VGA_GFX_SR_VALUE 0x00 |
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| 169 | #define VGA_GFX_SR_ENABLE 0x01 |
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| 170 | #define VGA_GFX_COMPARE_VALUE 0x02 |
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| 171 | #define VGA_GFX_DATA_ROTATE 0x03 |
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| 172 | #define VGA_GFX_PLANE_READ 0x04 |
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| 173 | #define VGA_GFX_MODE 0x05 |
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| 174 | #define VGA_GFX_MISC 0x06 |
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| 175 | #define VGA_GFX_COMPARE_MASK 0x07 |
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| 176 | #define VGA_GFX_BIT_MASK 0x08 |
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| 177 | |||
| 178 | /* VGA graphics controller bit masks */ |
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| 179 | #define VGA_GR06_GRAPHICS_MODE 0x01 |
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| 180 | |||
| 181 | /* macro for composing an 8-bit VGA register index and value |
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| 182 | * into a single 16-bit quantity */ |
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| 183 | #define VGA_OUT16VAL(v, r) (((v) << 8) | (r)) |
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| 184 | |||
| 185 | /* decide whether we should enable the faster 16-bit VGA register writes */ |
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| 186 | #ifdef __LITTLE_ENDIAN |
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| 187 | #define VGA_OUTW_WRITE |
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| 188 | #endif |
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| 189 | |||
| 190 | /* VGA State Save and Restore */ |
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| 191 | #define VGA_SAVE_FONT0 1 /* save/restore plane 2 fonts */ |
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| 192 | #define VGA_SAVE_FONT1 2 /* save/restore plane 3 fonts */ |
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| 193 | #define VGA_SAVE_TEXT 4 /* save/restore plane 0/1 fonts */ |
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| 194 | #define VGA_SAVE_FONTS 7 /* save/restore all fonts */ |
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| 195 | #define VGA_SAVE_MODE 8 /* save/restore video mode */ |
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| 196 | #define VGA_SAVE_CMAP 16 /* save/restore color map/DAC */ |
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| 197 | |||
| 198 | struct vgastate { |
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| 199 | caddr_t vgabase; /* mmio base, if supported */ |
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| 200 | unsigned long membase; /* VGA window base, 0 for default - 0xA000 */ |
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| 201 | __u32 memsize; /* VGA window size, 0 for default 64K */ |
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| 202 | __u32 flags; /* what state[s] to save (see VGA_SAVE_*) */ |
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| 203 | __u32 depth; /* current fb depth, not important */ |
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| 204 | __u32 num_attr; /* number of att registers, 0 for default */ |
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| 205 | __u32 num_crtc; /* number of crt registers, 0 for default */ |
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| 206 | __u32 num_gfx; /* number of gfx registers, 0 for default */ |
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| 207 | __u32 num_seq; /* number of seq registers, 0 for default */ |
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| 208 | void *vidstate; |
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| 209 | }; |
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| 210 | |||
| 211 | extern int save_vga(struct vgastate *state); |
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| 212 | extern int restore_vga(struct vgastate *state); |
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| 213 | |||
| 214 | /* |
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| 215 | * generic VGA port read/write |
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| 216 | */ |
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| 217 | |||
| 218 | static inline unsigned char vga_io_r (unsigned short port) |
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| 219 | { |
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| 220 | return inb_p(port); |
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| 221 | } |
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| 222 | |||
| 223 | static inline void vga_io_w (unsigned short port, unsigned char val) |
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| 224 | { |
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| 225 | outb_p(val, port); |
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| 226 | } |
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| 227 | |||
| 228 | static inline void vga_io_w_fast (unsigned short port, unsigned char reg, |
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| 229 | unsigned char val) |
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| 230 | { |
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| 231 | outw(VGA_OUT16VAL (val, reg), port); |
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| 232 | } |
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| 233 | |||
| 234 | static inline unsigned char vga_mm_r (caddr_t regbase, unsigned short port) |
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| 235 | { |
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| 236 | return readb (regbase + port); |
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| 237 | } |
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| 238 | |||
| 239 | static inline void vga_mm_w (caddr_t regbase, unsigned short port, unsigned char val) |
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| 240 | { |
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| 241 | writeb (val, regbase + port); |
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| 242 | } |
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| 243 | |||
| 244 | static inline void vga_mm_w_fast (caddr_t regbase, unsigned short port, |
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| 245 | unsigned char reg, unsigned char val) |
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| 246 | { |
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| 247 | writew (VGA_OUT16VAL (val, reg), regbase + port); |
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| 248 | } |
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| 249 | |||
| 250 | static inline unsigned char vga_r (caddr_t regbase, unsigned short port) |
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| 251 | { |
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| 252 | if (regbase) |
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| 253 | return vga_mm_r (regbase, port); |
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| 254 | else |
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| 255 | return vga_io_r (port); |
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| 256 | } |
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| 257 | |||
| 258 | static inline void vga_w (caddr_t regbase, unsigned short port, unsigned char val) |
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| 259 | { |
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| 260 | if (regbase) |
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| 261 | vga_mm_w (regbase, port, val); |
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| 262 | else |
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| 263 | vga_io_w (port, val); |
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| 264 | } |
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| 265 | |||
| 266 | |||
| 267 | static inline void vga_w_fast (caddr_t regbase, unsigned short port, |
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| 268 | unsigned char reg, unsigned char val) |
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| 269 | { |
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| 270 | if (regbase) |
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| 271 | vga_mm_w_fast (regbase, port, reg, val); |
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| 272 | else |
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| 273 | vga_io_w_fast (port, reg, val); |
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| 274 | } |
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| 275 | |||
| 276 | |||
| 277 | /* |
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| 278 | * VGA CRTC register read/write |
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| 279 | */ |
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| 280 | |||
| 281 | static inline unsigned char vga_rcrt (caddr_t regbase, unsigned char reg) |
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| 282 | { |
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| 283 | vga_w (regbase, VGA_CRT_IC, reg); |
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| 284 | return vga_r (regbase, VGA_CRT_DC); |
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| 285 | } |
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| 286 | |||
| 287 | static inline void vga_wcrt (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 288 | { |
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| 289 | #ifdef VGA_OUTW_WRITE |
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| 290 | vga_w_fast (regbase, VGA_CRT_IC, reg, val); |
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| 291 | #else |
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| 292 | vga_w (regbase, VGA_CRT_IC, reg); |
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| 293 | vga_w (regbase, VGA_CRT_DC, val); |
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| 294 | #endif /* VGA_OUTW_WRITE */ |
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| 295 | } |
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| 296 | |||
| 297 | static inline unsigned char vga_io_rcrt (unsigned char reg) |
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| 298 | { |
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| 299 | vga_io_w (VGA_CRT_IC, reg); |
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| 300 | return vga_io_r (VGA_CRT_DC); |
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| 301 | } |
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| 302 | |||
| 303 | static inline void vga_io_wcrt (unsigned char reg, unsigned char val) |
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| 304 | { |
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| 305 | #ifdef VGA_OUTW_WRITE |
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| 306 | vga_io_w_fast (VGA_CRT_IC, reg, val); |
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| 307 | #else |
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| 308 | vga_io_w (VGA_CRT_IC, reg); |
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| 309 | vga_io_w (VGA_CRT_DC, val); |
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| 310 | #endif /* VGA_OUTW_WRITE */ |
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| 311 | } |
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| 312 | |||
| 313 | static inline unsigned char vga_mm_rcrt (caddr_t regbase, unsigned char reg) |
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| 314 | { |
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| 315 | vga_mm_w (regbase, VGA_CRT_IC, reg); |
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| 316 | return vga_mm_r (regbase, VGA_CRT_DC); |
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| 317 | } |
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| 318 | |||
| 319 | static inline void vga_mm_wcrt (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 320 | { |
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| 321 | #ifdef VGA_OUTW_WRITE |
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| 322 | vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val); |
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| 323 | #else |
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| 324 | vga_mm_w (regbase, VGA_CRT_IC, reg); |
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| 325 | vga_mm_w (regbase, VGA_CRT_DC, val); |
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| 326 | #endif /* VGA_OUTW_WRITE */ |
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| 327 | } |
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| 328 | |||
| 329 | |||
| 330 | /* |
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| 331 | * VGA sequencer register read/write |
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| 332 | */ |
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| 333 | |||
| 334 | static inline unsigned char vga_rseq (caddr_t regbase, unsigned char reg) |
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| 335 | { |
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| 336 | vga_w (regbase, VGA_SEQ_I, reg); |
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| 337 | return vga_r (regbase, VGA_SEQ_D); |
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| 338 | } |
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| 339 | |||
| 340 | static inline void vga_wseq (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 341 | { |
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| 342 | #ifdef VGA_OUTW_WRITE |
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| 343 | vga_w_fast (regbase, VGA_SEQ_I, reg, val); |
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| 344 | #else |
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| 345 | vga_w (regbase, VGA_SEQ_I, reg); |
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| 346 | vga_w (regbase, VGA_SEQ_D, val); |
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| 347 | #endif /* VGA_OUTW_WRITE */ |
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| 348 | } |
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| 349 | |||
| 350 | static inline unsigned char vga_io_rseq (unsigned char reg) |
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| 351 | { |
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| 352 | vga_io_w (VGA_SEQ_I, reg); |
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| 353 | return vga_io_r (VGA_SEQ_D); |
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| 354 | } |
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| 355 | |||
| 356 | static inline void vga_io_wseq (unsigned char reg, unsigned char val) |
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| 357 | { |
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| 358 | #ifdef VGA_OUTW_WRITE |
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| 359 | vga_io_w_fast (VGA_SEQ_I, reg, val); |
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| 360 | #else |
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| 361 | vga_io_w (VGA_SEQ_I, reg); |
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| 362 | vga_io_w (VGA_SEQ_D, val); |
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| 363 | #endif /* VGA_OUTW_WRITE */ |
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| 364 | } |
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| 365 | |||
| 366 | static inline unsigned char vga_mm_rseq (caddr_t regbase, unsigned char reg) |
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| 367 | { |
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| 368 | vga_mm_w (regbase, VGA_SEQ_I, reg); |
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| 369 | return vga_mm_r (regbase, VGA_SEQ_D); |
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| 370 | } |
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| 371 | |||
| 372 | static inline void vga_mm_wseq (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 373 | { |
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| 374 | #ifdef VGA_OUTW_WRITE |
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| 375 | vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val); |
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| 376 | #else |
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| 377 | vga_mm_w (regbase, VGA_SEQ_I, reg); |
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| 378 | vga_mm_w (regbase, VGA_SEQ_D, val); |
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| 379 | #endif /* VGA_OUTW_WRITE */ |
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| 380 | } |
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| 381 | |||
| 382 | /* |
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| 383 | * VGA graphics controller register read/write |
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| 384 | */ |
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| 385 | |||
| 386 | static inline unsigned char vga_rgfx (caddr_t regbase, unsigned char reg) |
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| 387 | { |
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| 388 | vga_w (regbase, VGA_GFX_I, reg); |
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| 389 | return vga_r (regbase, VGA_GFX_D); |
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| 390 | } |
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| 391 | |||
| 392 | static inline void vga_wgfx (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 393 | { |
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| 394 | #ifdef VGA_OUTW_WRITE |
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| 395 | vga_w_fast (regbase, VGA_GFX_I, reg, val); |
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| 396 | #else |
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| 397 | vga_w (regbase, VGA_GFX_I, reg); |
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| 398 | vga_w (regbase, VGA_GFX_D, val); |
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| 399 | #endif /* VGA_OUTW_WRITE */ |
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| 400 | } |
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| 401 | |||
| 402 | static inline unsigned char vga_io_rgfx (unsigned char reg) |
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| 403 | { |
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| 404 | vga_io_w (VGA_GFX_I, reg); |
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| 405 | return vga_io_r (VGA_GFX_D); |
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| 406 | } |
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| 407 | |||
| 408 | static inline void vga_io_wgfx (unsigned char reg, unsigned char val) |
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| 409 | { |
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| 410 | #ifdef VGA_OUTW_WRITE |
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| 411 | vga_io_w_fast (VGA_GFX_I, reg, val); |
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| 412 | #else |
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| 413 | vga_io_w (VGA_GFX_I, reg); |
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| 414 | vga_io_w (VGA_GFX_D, val); |
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| 415 | #endif /* VGA_OUTW_WRITE */ |
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| 416 | } |
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| 417 | |||
| 418 | static inline unsigned char vga_mm_rgfx (caddr_t regbase, unsigned char reg) |
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| 419 | { |
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| 420 | vga_mm_w (regbase, VGA_GFX_I, reg); |
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| 421 | return vga_mm_r (regbase, VGA_GFX_D); |
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| 422 | } |
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| 423 | |||
| 424 | static inline void vga_mm_wgfx (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 425 | { |
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| 426 | #ifdef VGA_OUTW_WRITE |
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| 427 | vga_mm_w_fast (regbase, VGA_GFX_I, reg, val); |
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| 428 | #else |
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| 429 | vga_mm_w (regbase, VGA_GFX_I, reg); |
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| 430 | vga_mm_w (regbase, VGA_GFX_D, val); |
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| 431 | #endif /* VGA_OUTW_WRITE */ |
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| 432 | } |
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| 433 | |||
| 434 | |||
| 435 | /* |
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| 436 | * VGA attribute controller register read/write |
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| 437 | */ |
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| 438 | |||
| 439 | static inline unsigned char vga_rattr (caddr_t regbase, unsigned char reg) |
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| 440 | { |
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| 441 | vga_w (regbase, VGA_ATT_IW, reg); |
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| 442 | return vga_r (regbase, VGA_ATT_R); |
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| 443 | } |
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| 444 | |||
| 445 | static inline void vga_wattr (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 446 | { |
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| 447 | vga_w (regbase, VGA_ATT_IW, reg); |
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| 448 | vga_w (regbase, VGA_ATT_W, val); |
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| 449 | } |
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| 450 | |||
| 451 | static inline unsigned char vga_io_rattr (unsigned char reg) |
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| 452 | { |
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| 453 | vga_io_w (VGA_ATT_IW, reg); |
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| 454 | return vga_io_r (VGA_ATT_R); |
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| 455 | } |
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| 456 | |||
| 457 | static inline void vga_io_wattr (unsigned char reg, unsigned char val) |
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| 458 | { |
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| 459 | vga_io_w (VGA_ATT_IW, reg); |
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| 460 | vga_io_w (VGA_ATT_W, val); |
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| 461 | } |
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| 462 | |||
| 463 | static inline unsigned char vga_mm_rattr (caddr_t regbase, unsigned char reg) |
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| 464 | { |
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| 465 | vga_mm_w (regbase, VGA_ATT_IW, reg); |
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| 466 | return vga_mm_r (regbase, VGA_ATT_R); |
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| 467 | } |
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| 468 | |||
| 469 | static inline void vga_mm_wattr (caddr_t regbase, unsigned char reg, unsigned char val) |
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| 470 | { |
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| 471 | vga_mm_w (regbase, VGA_ATT_IW, reg); |
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| 472 | vga_mm_w (regbase, VGA_ATT_W, val); |
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| 473 | } |
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| 474 | |||
| 475 | #endif /* __linux_video_vga_h__ */ |