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467 giacomo 1
/*
2
 * linux/include/video/vga.h -- standard VGA chipset interaction
3
 *
4
 * Copyright 1999 Jeff Garzik <jgarzik@pobox.com>
5
 *
6
 * Copyright history from vga16fb.c:
7
 *      Copyright 1999 Ben Pfaff and Petr Vandrovec
8
 *      Based on VGA info at http://www.goodnet.com/~tinara/FreeVGA/home.htm
9
 *      Based on VESA framebuffer (c) 1998 Gerd Knorr
10
 *
11
 * This file is subject to the terms and conditions of the GNU General
12
 * Public License.  See the file COPYING in the main directory of this
13
 * archive for more details.  
14
 *
15
 */
16
 
17
#ifndef __linux_video_vga_h__
18
#define __linux_video_vga_h__
19
 
20
#include <linux/config.h>
21
#include <linux/types.h>
22
#include <asm/io.h>
23
#ifndef CONFIG_AMIGA
24
#include <asm/vga.h>
25
#else
26
/*
27
 * FIXME
28
 * Ugh, we don't have PCI space, so map readb() and friends to use Zorro space
29
 * for MMIO accesses. This should make clgenfb work again on Amiga
30
 */
31
#define inb_p(port)     0
32
#define inw_p(port)     0
33
#define outb_p(port, val)       do { } while (0)
34
#define outw(port, val)         do { } while (0)
35
#define readb           z_readb
36
#define writeb          z_writeb
37
#define writew          z_writew
38
#endif
39
#include <asm/byteorder.h>
40
 
41
 
42
/* Some of the code below is taken from SVGAlib.  The original,
43
   unmodified copyright notice for that code is below. */
44
/* VGAlib version 1.2 - (c) 1993 Tommy Frandsen                    */
45
/*                                                                 */
46
/* This library is free software; you can redistribute it and/or   */
47
/* modify it without any restrictions. This library is distributed */
48
/* in the hope that it will be useful, but without any warranty.   */
49
 
50
/* Multi-chipset support Copyright 1993 Harm Hanemaayer */
51
/* partially copyrighted (C) 1993 by Hartmut Schirmer */
52
 
53
/* VGA data register ports */
54
#define VGA_CRT_DC      0x3D5   /* CRT Controller Data Register - color emulation */
55
#define VGA_CRT_DM      0x3B5   /* CRT Controller Data Register - mono emulation */
56
#define VGA_ATT_R       0x3C1   /* Attribute Controller Data Read Register */
57
#define VGA_ATT_W       0x3C0   /* Attribute Controller Data Write Register */
58
#define VGA_GFX_D       0x3CF   /* Graphics Controller Data Register */
59
#define VGA_SEQ_D       0x3C5   /* Sequencer Data Register */
60
#define VGA_MIS_R       0x3CC   /* Misc Output Read Register */
61
#define VGA_MIS_W       0x3C2   /* Misc Output Write Register */
62
#define VGA_FTC_R       0x3CA   /* Feature Control Read Register */
63
#define VGA_IS1_RC      0x3DA   /* Input Status Register 1 - color emulation */
64
#define VGA_IS1_RM      0x3BA   /* Input Status Register 1 - mono emulation */
65
#define VGA_PEL_D       0x3C9   /* PEL Data Register */
66
#define VGA_PEL_MSK     0x3C6   /* PEL mask register */
67
 
68
/* EGA-specific registers */
69
#define EGA_GFX_E0      0x3CC   /* Graphics enable processor 0 */
70
#define EGA_GFX_E1      0x3CA   /* Graphics enable processor 1 */
71
 
72
/* VGA index register ports */
73
#define VGA_CRT_IC      0x3D4   /* CRT Controller Index - color emulation */
74
#define VGA_CRT_IM      0x3B4   /* CRT Controller Index - mono emulation */
75
#define VGA_ATT_IW      0x3C0   /* Attribute Controller Index & Data Write Register */
76
#define VGA_GFX_I       0x3CE   /* Graphics Controller Index */
77
#define VGA_SEQ_I       0x3C4   /* Sequencer Index */
78
#define VGA_PEL_IW      0x3C8   /* PEL Write Index */
79
#define VGA_PEL_IR      0x3C7   /* PEL Read Index */
80
 
81
/* standard VGA indexes max counts */
82
#define VGA_CRT_C       0x19    /* Number of CRT Controller Registers */
83
#define VGA_ATT_C       0x15    /* Number of Attribute Controller Registers */
84
#define VGA_GFX_C       0x09    /* Number of Graphics Controller Registers */
85
#define VGA_SEQ_C       0x05    /* Number of Sequencer Registers */
86
#define VGA_MIS_C       0x01    /* Number of Misc Output Register */
87
 
88
/* VGA misc register bit masks */
89
#define VGA_MIS_COLOR           0x01
90
#define VGA_MIS_ENB_MEM_ACCESS  0x02
91
#define VGA_MIS_DCLK_28322_720  0x04
92
#define VGA_MIS_ENB_PLL_LOAD    (0x04 | 0x08)
93
#define VGA_MIS_SEL_HIGH_PAGE   0x20
94
 
95
/* VGA CRT controller register indices */
96
#define VGA_CRTC_H_TOTAL        0
97
#define VGA_CRTC_H_DISP         1
98
#define VGA_CRTC_H_BLANK_START  2
99
#define VGA_CRTC_H_BLANK_END    3
100
#define VGA_CRTC_H_SYNC_START   4
101
#define VGA_CRTC_H_SYNC_END     5
102
#define VGA_CRTC_V_TOTAL        6
103
#define VGA_CRTC_OVERFLOW       7
104
#define VGA_CRTC_PRESET_ROW     8
105
#define VGA_CRTC_MAX_SCAN       9
106
#define VGA_CRTC_CURSOR_START   0x0A
107
#define VGA_CRTC_CURSOR_END     0x0B
108
#define VGA_CRTC_START_HI       0x0C
109
#define VGA_CRTC_START_LO       0x0D
110
#define VGA_CRTC_CURSOR_HI      0x0E
111
#define VGA_CRTC_CURSOR_LO      0x0F
112
#define VGA_CRTC_V_SYNC_START   0x10
113
#define VGA_CRTC_V_SYNC_END     0x11
114
#define VGA_CRTC_V_DISP_END     0x12
115
#define VGA_CRTC_OFFSET         0x13
116
#define VGA_CRTC_UNDERLINE      0x14
117
#define VGA_CRTC_V_BLANK_START  0x15
118
#define VGA_CRTC_V_BLANK_END    0x16
119
#define VGA_CRTC_MODE           0x17
120
#define VGA_CRTC_LINE_COMPARE   0x18
121
#define VGA_CRTC_REGS           VGA_CRT_C
122
 
123
/* VGA CRT controller bit masks */
124
#define VGA_CR11_LOCK_CR0_CR7   0x80 /* lock writes to CR0 - CR7 */
125
#define VGA_CR17_H_V_SIGNALS_ENABLED 0x80
126
 
127
/* VGA attribute controller register indices */
128
#define VGA_ATC_PALETTE0        0x00
129
#define VGA_ATC_PALETTE1        0x01
130
#define VGA_ATC_PALETTE2        0x02
131
#define VGA_ATC_PALETTE3        0x03
132
#define VGA_ATC_PALETTE4        0x04
133
#define VGA_ATC_PALETTE5        0x05
134
#define VGA_ATC_PALETTE6        0x06
135
#define VGA_ATC_PALETTE7        0x07
136
#define VGA_ATC_PALETTE8        0x08
137
#define VGA_ATC_PALETTE9        0x09
138
#define VGA_ATC_PALETTEA        0x0A
139
#define VGA_ATC_PALETTEB        0x0B
140
#define VGA_ATC_PALETTEC        0x0C
141
#define VGA_ATC_PALETTED        0x0D
142
#define VGA_ATC_PALETTEE        0x0E
143
#define VGA_ATC_PALETTEF        0x0F
144
#define VGA_ATC_MODE            0x10
145
#define VGA_ATC_OVERSCAN        0x11
146
#define VGA_ATC_PLANE_ENABLE    0x12
147
#define VGA_ATC_PEL             0x13
148
#define VGA_ATC_COLOR_PAGE      0x14
149
 
150
#define VGA_AR_ENABLE_DISPLAY   0x20
151
 
152
/* VGA sequencer register indices */
153
#define VGA_SEQ_RESET           0x00
154
#define VGA_SEQ_CLOCK_MODE      0x01
155
#define VGA_SEQ_PLANE_WRITE     0x02
156
#define VGA_SEQ_CHARACTER_MAP   0x03
157
#define VGA_SEQ_MEMORY_MODE     0x04
158
 
159
/* VGA sequencer register bit masks */
160
#define VGA_SR01_CHAR_CLK_8DOTS 0x01 /* bit 0: character clocks 8 dots wide are generated */
161
#define VGA_SR01_SCREEN_OFF     0x20 /* bit 5: Screen is off */
162
#define VGA_SR02_ALL_PLANES     0x0F /* bits 3-0: enable access to all planes */
163
#define VGA_SR04_EXT_MEM        0x02 /* bit 1: allows complete mem access to 256K */
164
#define VGA_SR04_SEQ_MODE       0x04 /* bit 2: directs system to use a sequential addressing mode */
165
#define VGA_SR04_CHN_4M         0x08 /* bit 3: selects modulo 4 addressing for CPU access to display memory */
166
 
167
/* VGA graphics controller register indices */
168
#define VGA_GFX_SR_VALUE        0x00
169
#define VGA_GFX_SR_ENABLE       0x01
170
#define VGA_GFX_COMPARE_VALUE   0x02
171
#define VGA_GFX_DATA_ROTATE     0x03
172
#define VGA_GFX_PLANE_READ      0x04
173
#define VGA_GFX_MODE            0x05
174
#define VGA_GFX_MISC            0x06
175
#define VGA_GFX_COMPARE_MASK    0x07
176
#define VGA_GFX_BIT_MASK        0x08
177
 
178
/* VGA graphics controller bit masks */
179
#define VGA_GR06_GRAPHICS_MODE  0x01
180
 
181
/* macro for composing an 8-bit VGA register index and value
182
 * into a single 16-bit quantity */
183
#define VGA_OUT16VAL(v, r)       (((v) << 8) | (r))
184
 
185
/* decide whether we should enable the faster 16-bit VGA register writes */
186
#ifdef __LITTLE_ENDIAN
187
#define VGA_OUTW_WRITE
188
#endif
189
 
190
/* VGA State Save and Restore */
191
#define VGA_SAVE_FONT0 1  /* save/restore plane 2 fonts   */
192
#define VGA_SAVE_FONT1 2  /* save/restore plane 3 fonts   */
193
#define VGA_SAVE_TEXT  4  /* save/restore plane 0/1 fonts */
194
#define VGA_SAVE_FONTS 7  /* save/restore all fonts       */
195
#define VGA_SAVE_MODE  8  /* save/restore video mode      */
196
#define VGA_SAVE_CMAP  16 /* save/restore color map/DAC   */
197
 
198
struct vgastate {
199
        caddr_t vgabase;        /* mmio base, if supported                 */
200
        unsigned long membase;  /* VGA window base, 0 for default - 0xA000 */
201
        __u32 memsize;          /* VGA window size, 0 for default 64K      */
202
        __u32 flags;            /* what state[s] to save (see VGA_SAVE_*)  */
203
        __u32 depth;            /* current fb depth, not important         */
204
        __u32 num_attr;         /* number of att registers, 0 for default  */
205
        __u32 num_crtc;         /* number of crt registers, 0 for default  */
206
        __u32 num_gfx;          /* number of gfx registers, 0 for default  */
207
        __u32 num_seq;          /* number of seq registers, 0 for default  */
208
        void *vidstate;
209
};     
210
 
211
extern int save_vga(struct vgastate *state);
212
extern int restore_vga(struct vgastate *state);
213
 
214
/*
215
 * generic VGA port read/write
216
 */
217
 
218
static inline unsigned char vga_io_r (unsigned short port)
219
{
220
        return inb_p(port);
221
}
222
 
223
static inline void vga_io_w (unsigned short port, unsigned char val)
224
{
225
        outb_p(val, port);
226
}
227
 
228
static inline void vga_io_w_fast (unsigned short port, unsigned char reg,
229
                                  unsigned char val)
230
{
231
        outw(VGA_OUT16VAL (val, reg), port);
232
}
233
 
234
static inline unsigned char vga_mm_r (caddr_t regbase, unsigned short port)
235
{
236
        return readb (regbase + port);
237
}
238
 
239
static inline void vga_mm_w (caddr_t regbase, unsigned short port, unsigned char val)
240
{
241
        writeb (val, regbase + port);
242
}
243
 
244
static inline void vga_mm_w_fast (caddr_t regbase, unsigned short port,
245
                                  unsigned char reg, unsigned char val)
246
{
247
        writew (VGA_OUT16VAL (val, reg), regbase + port);
248
}
249
 
250
static inline unsigned char vga_r (caddr_t regbase, unsigned short port)
251
{
252
        if (regbase)
253
                return vga_mm_r (regbase, port);
254
        else
255
                return vga_io_r (port);
256
}
257
 
258
static inline void vga_w (caddr_t regbase, unsigned short port, unsigned char val)
259
{
260
        if (regbase)
261
                vga_mm_w (regbase, port, val);
262
        else
263
                vga_io_w (port, val);
264
}
265
 
266
 
267
static inline void vga_w_fast (caddr_t regbase, unsigned short port,
268
                               unsigned char reg, unsigned char val)
269
{
270
        if (regbase)
271
                vga_mm_w_fast (regbase, port, reg, val);
272
        else
273
                vga_io_w_fast (port, reg, val);
274
}
275
 
276
 
277
/*
278
 * VGA CRTC register read/write
279
 */
280
 
281
static inline unsigned char vga_rcrt (caddr_t regbase, unsigned char reg)
282
{
283
        vga_w (regbase, VGA_CRT_IC, reg);
284
        return vga_r (regbase, VGA_CRT_DC);
285
}
286
 
287
static inline void vga_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
288
{
289
#ifdef VGA_OUTW_WRITE
290
        vga_w_fast (regbase, VGA_CRT_IC, reg, val);
291
#else
292
        vga_w (regbase, VGA_CRT_IC, reg);
293
        vga_w (regbase, VGA_CRT_DC, val);
294
#endif /* VGA_OUTW_WRITE */
295
}
296
 
297
static inline unsigned char vga_io_rcrt (unsigned char reg)
298
{
299
        vga_io_w (VGA_CRT_IC, reg);
300
        return vga_io_r (VGA_CRT_DC);
301
}
302
 
303
static inline void vga_io_wcrt (unsigned char reg, unsigned char val)
304
{
305
#ifdef VGA_OUTW_WRITE
306
        vga_io_w_fast (VGA_CRT_IC, reg, val);
307
#else
308
        vga_io_w (VGA_CRT_IC, reg);
309
        vga_io_w (VGA_CRT_DC, val);
310
#endif /* VGA_OUTW_WRITE */
311
}
312
 
313
static inline unsigned char vga_mm_rcrt (caddr_t regbase, unsigned char reg)
314
{
315
        vga_mm_w (regbase, VGA_CRT_IC, reg);
316
        return vga_mm_r (regbase, VGA_CRT_DC);
317
}
318
 
319
static inline void vga_mm_wcrt (caddr_t regbase, unsigned char reg, unsigned char val)
320
{
321
#ifdef VGA_OUTW_WRITE
322
        vga_mm_w_fast (regbase, VGA_CRT_IC, reg, val);
323
#else
324
        vga_mm_w (regbase, VGA_CRT_IC, reg);
325
        vga_mm_w (regbase, VGA_CRT_DC, val);
326
#endif /* VGA_OUTW_WRITE */
327
}
328
 
329
 
330
/*
331
 * VGA sequencer register read/write
332
 */
333
 
334
static inline unsigned char vga_rseq (caddr_t regbase, unsigned char reg)
335
{
336
        vga_w (regbase, VGA_SEQ_I, reg);
337
        return vga_r (regbase, VGA_SEQ_D);
338
}
339
 
340
static inline void vga_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
341
{
342
#ifdef VGA_OUTW_WRITE
343
        vga_w_fast (regbase, VGA_SEQ_I, reg, val);
344
#else
345
        vga_w (regbase, VGA_SEQ_I, reg);
346
        vga_w (regbase, VGA_SEQ_D, val);
347
#endif /* VGA_OUTW_WRITE */
348
}
349
 
350
static inline unsigned char vga_io_rseq (unsigned char reg)
351
{
352
        vga_io_w (VGA_SEQ_I, reg);
353
        return vga_io_r (VGA_SEQ_D);
354
}
355
 
356
static inline void vga_io_wseq (unsigned char reg, unsigned char val)
357
{
358
#ifdef VGA_OUTW_WRITE
359
        vga_io_w_fast (VGA_SEQ_I, reg, val);
360
#else
361
        vga_io_w (VGA_SEQ_I, reg);
362
        vga_io_w (VGA_SEQ_D, val);
363
#endif /* VGA_OUTW_WRITE */
364
}
365
 
366
static inline unsigned char vga_mm_rseq (caddr_t regbase, unsigned char reg)
367
{
368
        vga_mm_w (regbase, VGA_SEQ_I, reg);
369
        return vga_mm_r (regbase, VGA_SEQ_D);
370
}
371
 
372
static inline void vga_mm_wseq (caddr_t regbase, unsigned char reg, unsigned char val)
373
{
374
#ifdef VGA_OUTW_WRITE
375
        vga_mm_w_fast (regbase, VGA_SEQ_I, reg, val);
376
#else
377
        vga_mm_w (regbase, VGA_SEQ_I, reg);
378
        vga_mm_w (regbase, VGA_SEQ_D, val);
379
#endif /* VGA_OUTW_WRITE */
380
}
381
 
382
/*
383
 * VGA graphics controller register read/write
384
 */
385
 
386
static inline unsigned char vga_rgfx (caddr_t regbase, unsigned char reg)
387
{
388
        vga_w (regbase, VGA_GFX_I, reg);
389
        return vga_r (regbase, VGA_GFX_D);
390
}
391
 
392
static inline void vga_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
393
{
394
#ifdef VGA_OUTW_WRITE
395
        vga_w_fast (regbase, VGA_GFX_I, reg, val);
396
#else
397
        vga_w (regbase, VGA_GFX_I, reg);
398
        vga_w (regbase, VGA_GFX_D, val);
399
#endif /* VGA_OUTW_WRITE */
400
}
401
 
402
static inline unsigned char vga_io_rgfx (unsigned char reg)
403
{
404
        vga_io_w (VGA_GFX_I, reg);
405
        return vga_io_r (VGA_GFX_D);
406
}
407
 
408
static inline void vga_io_wgfx (unsigned char reg, unsigned char val)
409
{
410
#ifdef VGA_OUTW_WRITE
411
        vga_io_w_fast (VGA_GFX_I, reg, val);
412
#else
413
        vga_io_w (VGA_GFX_I, reg);
414
        vga_io_w (VGA_GFX_D, val);
415
#endif /* VGA_OUTW_WRITE */
416
}
417
 
418
static inline unsigned char vga_mm_rgfx (caddr_t regbase, unsigned char reg)
419
{
420
        vga_mm_w (regbase, VGA_GFX_I, reg);
421
        return vga_mm_r (regbase, VGA_GFX_D);
422
}
423
 
424
static inline void vga_mm_wgfx (caddr_t regbase, unsigned char reg, unsigned char val)
425
{
426
#ifdef VGA_OUTW_WRITE
427
        vga_mm_w_fast (regbase, VGA_GFX_I, reg, val);
428
#else
429
        vga_mm_w (regbase, VGA_GFX_I, reg);
430
        vga_mm_w (regbase, VGA_GFX_D, val);
431
#endif /* VGA_OUTW_WRITE */
432
}
433
 
434
 
435
/*
436
 * VGA attribute controller register read/write
437
 */
438
 
439
static inline unsigned char vga_rattr (caddr_t regbase, unsigned char reg)
440
{
441
        vga_w (regbase, VGA_ATT_IW, reg);
442
        return vga_r (regbase, VGA_ATT_R);
443
}
444
 
445
static inline void vga_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
446
{
447
        vga_w (regbase, VGA_ATT_IW, reg);
448
        vga_w (regbase, VGA_ATT_W, val);
449
}
450
 
451
static inline unsigned char vga_io_rattr (unsigned char reg)
452
{
453
        vga_io_w (VGA_ATT_IW, reg);
454
        return vga_io_r (VGA_ATT_R);
455
}
456
 
457
static inline void vga_io_wattr (unsigned char reg, unsigned char val)
458
{
459
        vga_io_w (VGA_ATT_IW, reg);
460
        vga_io_w (VGA_ATT_W, val);
461
}
462
 
463
static inline unsigned char vga_mm_rattr (caddr_t regbase, unsigned char reg)
464
{
465
        vga_mm_w (regbase, VGA_ATT_IW, reg);
466
        return vga_mm_r (regbase, VGA_ATT_R);
467
}
468
 
469
static inline void vga_mm_wattr (caddr_t regbase, unsigned char reg, unsigned char val)
470
{
471
        vga_mm_w (regbase, VGA_ATT_IW, reg);
472
        vga_mm_w (regbase, VGA_ATT_W, val);
473
}
474
 
475
#endif /* __linux_video_vga_h__ */