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Rev | Author | Line No. | Line |
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2 | pj | 1 | /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */ |
2 | /* |
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3 | Written 1996-1998 by Donald Becker. |
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4 | |||
5 | This software may be used and distributed according to the terms |
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6 | of the GNU Public License, incorporated herein by reference. |
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7 | |||
8 | This driver is for the 3Com "Vortex" and "Boomerang" series ethercards. |
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9 | Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597 |
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10 | and the EtherLink XL 3c900 and 3c905 cards. |
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11 | |||
12 | The author may be reached as becker@CESDIS.gsfc.nasa.gov, or C/O |
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13 | Center of Excellence in Space Data and Information Sciences |
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14 | Code 930.5, Goddard Space Flight Center, Greenbelt MD 20771 |
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15 | */ |
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16 | |||
17 | static char *version = |
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18 | "3c59x.c:v0.99H 11/17/98 Donald Becker http://cesdis.gsfc.nasa.gov/linux/drivers/vortex.html\n"; |
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19 | |||
20 | /* "Knobs" that adjust features and parameters. */ |
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21 | /* Set the copy breakpoint for the copy-only-tiny-frames scheme. |
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22 | Setting to > 1512 effectively disables this feature. */ |
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23 | static const int rx_copybreak = 200; |
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24 | /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */ |
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25 | static const int mtu = 1500; |
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26 | /* Maximum events (Rx packets, etc.) to handle at each interrupt. */ |
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27 | static int max_interrupt_work = 20; |
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28 | |||
29 | /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */ |
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30 | #define vortex_debug debug |
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31 | #ifdef VORTEX_DEBUG |
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32 | static int vortex_debug = VORTEX_DEBUG; |
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33 | #else |
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34 | static int vortex_debug = 1; |
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35 | #endif |
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36 | |||
37 | /* Some values here only for performance evaluation and path-coverage |
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38 | debugging. */ |
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39 | static int rx_nocopy = 0, rx_copy = 0, queued_packet = 0, rx_csumhits; |
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40 | |||
41 | /* A few values that may be tweaked. */ |
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42 | /* Time in jiffies before concluding the transmitter is hung. */ |
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43 | #define TX_TIMEOUT ((400*HZ)/1000) |
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44 | |||
45 | /* Keep the ring sizes a power of two for efficiency. */ |
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46 | #define TX_RING_SIZE 16 |
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47 | #define RX_RING_SIZE 32 |
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48 | #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ |
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49 | |||
50 | #include <linux/config.h> |
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51 | #include <linux/version.h> |
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52 | #ifdef MODULE |
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53 | #ifdef MODVERSIONS |
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54 | #include <linux/modversions.h> |
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55 | #endif |
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56 | #include <linux/module.h> |
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57 | #else |
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58 | #define MOD_INC_USE_COUNT |
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59 | #define MOD_DEC_USE_COUNT |
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60 | #endif |
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61 | |||
62 | #include <linux/kernel.h> |
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63 | #include <linux/sched.h> |
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64 | #include <linux/string.h> |
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65 | #include <linux/timer.h> |
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66 | #include <linux/errno.h> |
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67 | #include <linux/in.h> |
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68 | #include <linux/ioport.h> |
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69 | #include <linux/malloc.h> |
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70 | #include <linux/interrupt.h> |
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71 | #include <linux/pci.h> |
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72 | #include <linux/netdevice.h> |
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73 | #include <linux/etherdevice.h> |
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74 | #include <linux/skbuff.h> |
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75 | #if LINUX_VERSION_CODE < 0x20155 || defined(CARDBUS) |
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76 | #include <linux/bios32.h> |
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77 | #endif |
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78 | #include <asm/irq.h> /* For NR_IRQS only. */ |
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79 | #include <asm/bitops.h> |
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80 | #include <asm/io.h> |
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81 | |||
82 | /* Kernel compatibility defines, some common to David Hinds' PCMCIA package. |
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83 | This is only in the support-all-kernels source code. */ |
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84 | |||
85 | #define RUN_AT(x) (jiffies + (x)) |
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86 | |||
87 | #include <linux/delay.h> |
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88 | |||
89 | #if (LINUX_VERSION_CODE <= 0x20100) |
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90 | #ifndef __alpha__ |
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91 | #define ioremap(a,b) \ |
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92 | (((a)<0x100000) ? (void *)((u_long)(a)) : vremap(a,b)) |
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93 | #define iounmap(v) \ |
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94 | do { if ((u_long)(v) > 0x100000) vfree(v); } while (0) |
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95 | #endif |
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96 | #endif |
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97 | #if LINUX_VERSION_CODE <= 0x20139 |
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98 | #define net_device_stats enet_statistics |
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99 | #define NETSTATS_VER2 |
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100 | #endif |
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101 | #if LINUX_VERSION_CODE < 0x20138 |
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102 | #define test_and_set_bit(val, addr) set_bit(val, addr) |
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103 | #define le32_to_cpu(val) (val) |
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104 | #define cpu_to_le32(val) (val) |
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105 | #endif |
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106 | #if LINUX_VERSION_CODE < 0x20155 |
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107 | #define PCI_SUPPORT_VER1 |
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108 | #else |
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109 | #define PCI_SUPPORT_VER2 |
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110 | #endif |
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111 | #if LINUX_VERSION_CODE < 0x20159 |
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112 | #define DEV_FREE_SKB(skb) dev_kfree_skb (skb, FREE_WRITE); |
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113 | #else /* Grrr, unneeded incompatible change. */ |
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114 | #define DEV_FREE_SKB(skb) dev_kfree_skb(skb); |
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115 | #endif |
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116 | |||
117 | #if defined(MODULE) && LINUX_VERSION_CODE > 0x20115 |
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118 | MODULE_AUTHOR("Donald Becker <becker@cesdis.gsfc.nasa.gov>"); |
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119 | MODULE_DESCRIPTION("3Com 3c590/3c900 series Vortex/Boomerang driver"); |
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120 | MODULE_PARM(debug, "i"); |
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121 | MODULE_PARM(options, "1-" __MODULE_STRING(8) "i"); |
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122 | MODULE_PARM(full_duplex, "1-" __MODULE_STRING(8) "i"); |
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123 | MODULE_PARM(rx_copybreak, "i"); |
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124 | MODULE_PARM(max_interrupt_work, "i"); |
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125 | MODULE_PARM(compaq_ioaddr, "i"); |
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126 | MODULE_PARM(compaq_irq, "i"); |
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127 | MODULE_PARM(compaq_device_id, "i"); |
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128 | #endif |
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129 | |||
130 | /* Operational parameter that usually are not changed. */ |
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131 | |||
132 | /* The Vortex size is twice that of the original EtherLinkIII series: the |
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133 | runtime register window, window 1, is now always mapped in. |
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134 | The Boomerang size is twice as large as the Vortex -- it has additional |
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135 | bus master control registers. */ |
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136 | #define VORTEX_TOTAL_SIZE 0x20 |
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137 | #define BOOMERANG_TOTAL_SIZE 0x40 |
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138 | |||
139 | /* Set iff a MII transceiver on any interface requires mdio preamble. |
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140 | This only set with the original DP83840 on older 3c905 boards, so the extra |
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141 | code size of a per-interface flag is not worthwhile. */ |
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142 | static char mii_preamble_required = 0; |
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143 | |||
144 | /* |
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145 | Theory of Operation |
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146 | |||
147 | I. Board Compatibility |
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148 | |||
149 | This device driver is designed for the 3Com FastEtherLink and FastEtherLink |
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150 | XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs |
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151 | versions of the FastEtherLink cards. The supported product IDs are |
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152 | 3c590, 3c592, 3c595, 3c597, 3c900, 3c905 |
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153 | |||
154 | The related ISA 3c515 is supported with a separate driver, 3c515.c, included |
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155 | with the kernel source or available from |
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156 | cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html |
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157 | |||
158 | II. Board-specific settings |
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159 | |||
160 | PCI bus devices are configured by the system at boot time, so no jumpers |
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161 | need to be set on the board. The system BIOS should be set to assign the |
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162 | PCI INTA signal to an otherwise unused system IRQ line. |
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163 | |||
164 | The EEPROM settings for media type and forced-full-duplex are observed. |
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165 | The EEPROM media type should be left at the default "autoselect" unless using |
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166 | 10base2 or AUI connections which cannot be reliably detected. |
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167 | |||
168 | III. Driver operation |
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169 | |||
170 | The 3c59x series use an interface that's very similar to the previous 3c5x9 |
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171 | series. The primary interface is two programmed-I/O FIFOs, with an |
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172 | alternate single-contiguous-region bus-master transfer (see next). |
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173 | |||
174 | The 3c900 "Boomerang" series uses a full-bus-master interface with separate |
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175 | lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet, |
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176 | DEC Tulip and Intel Speedo3. The first chip version retains a compatible |
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177 | programmed-I/O interface that has been removed in 'B' and subsequent board |
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178 | revisions. |
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179 | |||
180 | One extension that is advertised in a very large font is that the adapters |
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181 | are capable of being bus masters. On the Vortex chip this capability was |
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182 | only for a single contiguous region making it far less useful than the full |
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183 | bus master capability. There is a significant performance impact of taking |
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184 | an extra interrupt or polling for the completion of each transfer, as well |
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185 | as difficulty sharing the single transfer engine between the transmit and |
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186 | receive threads. Using DMA transfers is a win only with large blocks or |
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187 | with the flawed versions of the Intel Orion motherboard PCI controller. |
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188 | |||
189 | The Boomerang chip's full-bus-master interface is useful, and has the |
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190 | currently-unused advantages over other similar chips that queued transmit |
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191 | packets may be reordered and receive buffer groups are associated with a |
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192 | single frame. |
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193 | |||
194 | With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme. |
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195 | Rather than a fixed intermediate receive buffer, this scheme allocates |
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196 | full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as |
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197 | the copying breakpoint: it is chosen to trade-off the memory wasted by |
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198 | passing the full-sized skbuff to the queue layer for all frames vs. the |
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199 | copying cost of copying a frame to a correctly-sized skbuff. |
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200 | |||
201 | |||
202 | IIIC. Synchronization |
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203 | The driver runs as two independent, single-threaded flows of control. One |
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204 | is the send-packet routine, which enforces single-threaded use by the |
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205 | dev->tbusy flag. The other thread is the interrupt handler, which is single |
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206 | threaded by the hardware and other software. |
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207 | |||
208 | IV. Notes |
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209 | |||
210 | Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development |
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211 | 3c590, 3c595, and 3c900 boards. |
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212 | The name "Vortex" is the internal 3Com project name for the PCI ASIC, and |
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213 | the EISA version is called "Demon". According to Terry these names come |
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214 | from rides at the local amusement park. |
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215 | |||
216 | The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes! |
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217 | This driver only supports ethernet packets because of the skbuff allocation |
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218 | limit of 4K. |
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219 | */ |
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220 | |||
221 | /* This table drives the PCI probe routines. It's mostly boilerplate in all |
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222 | of the drivers, and will likely be provided by some future kernel. |
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223 | */ |
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224 | enum pci_flags_bit { |
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225 | PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4, |
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226 | PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3, |
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227 | }; |
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228 | struct pci_id_info { |
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229 | const char *name; |
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230 | u16 vendor_id, device_id, device_id_mask, flags; |
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231 | int drv_flags, io_size; |
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232 | struct device *(*probe1)(int pci_bus, int pci_devfn, struct device *dev, |
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233 | long ioaddr, int irq, int chip_idx, int fnd_cnt); |
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234 | }; |
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235 | |||
236 | enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, |
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237 | HAS_PWR_CTRL=0x10, HAS_MII=0x20, HAS_NWAY=0x40, HAS_CB_FNS=0x80, }; |
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238 | static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
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239 | struct device *dev, long ioaddr, |
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240 | int irq, int dev_id, int card_idx); |
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241 | static struct pci_id_info pci_tbl[] = { |
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242 | {"3c590 Vortex 10Mbps", 0x10B7, 0x5900, 0xffff, |
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243 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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244 | {"3c595 Vortex 100baseTx", 0x10B7, 0x5950, 0xffff, |
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245 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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246 | {"3c595 Vortex 100baseT4", 0x10B7, 0x5951, 0xffff, |
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247 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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248 | {"3c595 Vortex 100base-MII", 0x10B7, 0x5952, 0xffff, |
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249 | PCI_USES_IO|PCI_USES_MASTER, IS_VORTEX, 32, vortex_probe1}, |
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250 | {"3Com Vortex", 0x10B7, 0x5900, 0xff00, |
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251 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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252 | {"3c900 Boomerang 10baseT", 0x10B7, 0x9000, 0xffff, |
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253 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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254 | {"3c900 Boomerang 10Mbps Combo", 0x10B7, 0x9001, 0xffff, |
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255 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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256 | {"3c900 Cyclone 10Mbps Combo", 0x10B7, 0x9005, 0xffff, |
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257 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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258 | {"3c900B-FL Cyclone 10base-FL", 0x10B7, 0x900A, 0xffff, |
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259 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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260 | {"3c905 Boomerang 100baseTx", 0x10B7, 0x9050, 0xffff, |
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261 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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262 | {"3c905 Boomerang 100baseT4", 0x10B7, 0x9051, 0xffff, |
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263 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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264 | {"3c905B Cyclone 100baseTx", 0x10B7, 0x9055, 0xffff, |
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265 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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266 | {"3c905B Cyclone 10/100/BNC", 0x10B7, 0x9058, 0xffff, |
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267 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY, 128, vortex_probe1}, |
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268 | {"3c905B-FX Cyclone 100baseFx", 0x10B7, 0x905A, 0xffff, |
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269 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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270 | {"3c905C Tornado", 0x10B7, 0x9200, 0xffff, |
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271 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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272 | {"3c980 Cyclone", 0x10B7, 0x9800, 0xfff0, |
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273 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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274 | {"3cSOHO100-TX Hurricane", 0x10B7, 0x7646, 0xffff, |
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275 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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276 | {"3c555 Laptop Hurricane", 0x10B7, 0x5055, 0xffff, |
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277 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE, 128, vortex_probe1}, |
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278 | {"3c575 Boomerang CardBus", 0x10B7, 0x5057, 0xffff, |
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279 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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280 | {"3CCFE575 Cyclone CardBus", 0x10B7, 0x5157, 0xffff, |
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281 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
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282 | 128, vortex_probe1}, |
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283 | {"3CCFE656 Cyclone CardBus", 0x10B7, 0x6560, 0xffff, |
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284 | PCI_USES_IO|PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS, |
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285 | 128, vortex_probe1}, |
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286 | {"3c575 series CardBus (unknown version)", 0x10B7, 0x5057, 0xf0ff, |
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287 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG|HAS_MII, 64, vortex_probe1}, |
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288 | {"3Com Boomerang (unknown version)", 0x10B7, 0x9000, 0xff00, |
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289 | PCI_USES_IO|PCI_USES_MASTER, IS_BOOMERANG, 64, vortex_probe1}, |
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290 | {0,}, /* 0 terminated list. */ |
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291 | }; |
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292 | |||
293 | /* Operational definitions. |
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294 | These are not used by other compilation units and thus are not |
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295 | exported in a ".h" file. |
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296 | |||
297 | First the windows. There are eight register windows, with the command |
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298 | and status registers available in each. |
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299 | */ |
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300 | #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD) |
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301 | #define EL3_CMD 0x0e |
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302 | #define EL3_STATUS 0x0e |
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303 | |||
304 | /* The top five bits written to EL3_CMD are a command, the lower |
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305 | 11 bits are the parameter, if applicable. |
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306 | Note that 11 parameters bits was fine for ethernet, but the new chip |
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307 | can handle FDDI length frames (~4500 octets) and now parameters count |
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308 | 32-bit 'Dwords' rather than octets. */ |
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309 | |||
310 | enum vortex_cmd { |
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311 | TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11, |
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312 | RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11, |
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313 | UpStall = 6<<11, UpUnstall = (6<<11)+1, |
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314 | DownStall = (6<<11)+2, DownUnstall = (6<<11)+3, |
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315 | RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11, |
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316 | FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11, |
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317 | SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11, |
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318 | SetTxThreshold = 18<<11, SetTxStart = 19<<11, |
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319 | StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11, |
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320 | StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,}; |
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321 | |||
322 | /* The SetRxFilter command accepts the following classes: */ |
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323 | enum RxFilter { |
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324 | RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 }; |
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325 | |||
326 | /* Bits in the general status register. */ |
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327 | enum vortex_status { |
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328 | IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004, |
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329 | TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020, |
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330 | IntReq = 0x0040, StatsFull = 0x0080, |
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331 | DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10, |
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332 | DMAInProgress = 1<<11, /* DMA controller is still busy.*/ |
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333 | CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/ |
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334 | }; |
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335 | |||
336 | /* Register window 1 offsets, the window used in normal operation. |
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337 | On the Vortex this window is always mapped at offsets 0x10-0x1f. */ |
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338 | enum Window1 { |
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339 | TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14, |
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340 | RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B, |
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341 | TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */ |
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342 | }; |
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343 | enum Window0 { |
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344 | Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */ |
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345 | Wn0EepromData = 12, /* Window 0: EEPROM results register. */ |
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346 | IntrStatus=0x0E, /* Valid in all windows. */ |
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347 | }; |
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348 | enum Win0_EEPROM_bits { |
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349 | EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0, |
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350 | EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */ |
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351 | EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */ |
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352 | }; |
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353 | /* EEPROM locations. */ |
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354 | enum eeprom_offset { |
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355 | PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3, |
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356 | EtherLink3ID=7, IFXcvrIO=8, IRQLine=9, |
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357 | NodeAddr01=10, NodeAddr23=11, NodeAddr45=12, |
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358 | DriverTune=13, Checksum=15}; |
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359 | |||
360 | enum Window2 { /* Window 2. */ |
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361 | Wn2_ResetOptions=12, |
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362 | }; |
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363 | enum Window3 { /* Window 3: MAC/config bits. */ |
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364 | Wn3_Config=0, Wn3_MAC_Ctrl=6, Wn3_Options=8, |
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365 | }; |
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366 | union wn3_config { |
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367 | int i; |
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368 | struct w3_config_fields { |
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369 | unsigned int ram_size:3, ram_width:1, ram_speed:2, rom_size:2; |
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370 | int pad8:8; |
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371 | unsigned int ram_split:2, pad18:2, xcvr:4, autoselect:1; |
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372 | int pad24:7; |
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373 | } u; |
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374 | }; |
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375 | |||
376 | enum Window4 { /* Window 4: Xcvr/media bits. */ |
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377 | Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10, |
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378 | }; |
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379 | enum Win4_Media_bits { |
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380 | Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */ |
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381 | Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */ |
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382 | Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */ |
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383 | Media_LnkBeat = 0x0800, |
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384 | }; |
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385 | enum Window7 { /* Window 7: Bus Master control. */ |
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386 | Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12, |
||
387 | }; |
||
388 | /* Boomerang bus master control registers. */ |
||
389 | enum MasterCtrl { |
||
390 | PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c, |
||
391 | TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38, |
||
392 | }; |
||
393 | |||
394 | /* The Rx and Tx descriptor lists. |
||
395 | Caution Alpha hackers: these types are 32 bits! Note also the 8 byte |
||
396 | alignment contraint on tx_ring[] and rx_ring[]. */ |
||
397 | #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */ |
||
398 | struct boom_rx_desc { |
||
399 | u32 next; /* Last entry points to 0. */ |
||
400 | s32 status; |
||
401 | u32 addr; /* Up to 63 addr/len pairs possible. */ |
||
402 | s32 length; /* Set LAST_FRAG to indicate last pair. */ |
||
403 | }; |
||
404 | /* Values for the Rx status entry. */ |
||
405 | enum rx_desc_status { |
||
406 | RxDComplete=0x00008000, RxDError=0x4000, |
||
407 | /* See boomerang_rx() for actual error bits */ |
||
408 | IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27, |
||
409 | IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31, |
||
410 | }; |
||
411 | |||
412 | struct boom_tx_desc { |
||
413 | u32 next; /* Last entry points to 0. */ |
||
414 | s32 status; /* bits 0:12 length, others see below. */ |
||
415 | u32 addr; |
||
416 | s32 length; |
||
417 | }; |
||
418 | |||
419 | /* Values for the Tx status entry. */ |
||
420 | enum tx_desc_status { |
||
421 | CRCDisable=0x2000, TxDComplete=0x8000, |
||
422 | AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000, |
||
423 | TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */ |
||
424 | }; |
||
425 | |||
426 | /* Chip features we care about in vp->capabilities, read from the EEPROM. */ |
||
427 | enum ChipCaps { CapBusMaster=0x20 }; |
||
428 | |||
429 | struct vortex_private { |
||
430 | /* The Rx and Tx rings should be quad-word-aligned. */ |
||
431 | struct boom_rx_desc rx_ring[RX_RING_SIZE]; |
||
432 | struct boom_tx_desc tx_ring[TX_RING_SIZE]; |
||
433 | /* The addresses of transmit- and receive-in-place skbuffs. */ |
||
434 | struct sk_buff* rx_skbuff[RX_RING_SIZE]; |
||
435 | struct sk_buff* tx_skbuff[TX_RING_SIZE]; |
||
436 | struct device *next_module; |
||
437 | void *priv_addr; |
||
438 | unsigned int cur_rx, cur_tx; /* The next free ring entry */ |
||
439 | unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */ |
||
440 | struct net_device_stats stats; |
||
441 | struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */ |
||
442 | |||
443 | /* PCI configuration space information. */ |
||
444 | u8 pci_bus, pci_devfn; /* PCI bus location, for power management. */ |
||
445 | char *cb_fn_base; /* CardBus function status addr space. */ |
||
446 | int chip_id; |
||
447 | |||
448 | /* The remainder are related to chip state, mostly media selection. */ |
||
449 | unsigned long in_interrupt; |
||
450 | struct timer_list timer; /* Media selection timer. */ |
||
451 | int options; /* User-settable misc. driver options. */ |
||
452 | unsigned int media_override:3, /* Passed-in media type. */ |
||
453 | default_media:4, /* Read from the EEPROM/Wn3_Config. */ |
||
454 | full_duplex:1, force_fd:1, autoselect:1, |
||
455 | bus_master:1, /* Vortex can only do a fragment bus-m. */ |
||
456 | full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */ |
||
457 | hw_csums:1, /* Has hardware checksums. */ |
||
458 | tx_full:1; |
||
459 | u16 status_enable; |
||
460 | u16 intr_enable; |
||
461 | u16 available_media; /* From Wn3_Options. */ |
||
462 | u16 capabilities, info1, info2; /* Various, from EEPROM. */ |
||
463 | u16 advertising; /* NWay media advertisement */ |
||
464 | unsigned char phys[2]; /* MII device addresses. */ |
||
465 | }; |
||
466 | |||
467 | /* The action to take with a media selection timer tick. |
||
468 | Note that we deviate from the 3Com order by checking 10base2 before AUI. |
||
469 | */ |
||
470 | enum xcvr_types { |
||
471 | XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx, |
||
472 | XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10, |
||
473 | }; |
||
474 | |||
475 | static struct media_table { |
||
476 | char *name; |
||
477 | unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */ |
||
478 | mask:8, /* The transceiver-present bit in Wn3_Config.*/ |
||
479 | next:8; /* The media type to try next. */ |
||
480 | int wait; /* Time before we check media status. */ |
||
481 | } media_tbl[] = { |
||
482 | { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10}, |
||
483 | { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10}, |
||
484 | { "undefined", 0, 0x80, XCVR_10baseT, 10000}, |
||
485 | { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10}, |
||
486 | { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10}, |
||
487 | { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10}, |
||
488 | { "MII", 0, 0x41, XCVR_10baseT, 3*HZ }, |
||
489 | { "undefined", 0, 0x01, XCVR_10baseT, 10000}, |
||
490 | { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ}, |
||
491 | { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ }, |
||
492 | { "Default", 0, 0xFF, XCVR_10baseT, 10000}, |
||
493 | }; |
||
494 | |||
495 | #ifndef CARDBUS |
||
496 | static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]); |
||
497 | #endif |
||
498 | static int vortex_open(struct device *dev); |
||
499 | static void mdio_sync(long ioaddr, int bits); |
||
500 | static int mdio_read(long ioaddr, int phy_id, int location); |
||
501 | static void mdio_write(long ioaddr, int phy_id, int location, int value); |
||
502 | static void vortex_timer(unsigned long arg); |
||
503 | static int vortex_start_xmit(struct sk_buff *skb, struct device *dev); |
||
504 | static int boomerang_start_xmit(struct sk_buff *skb, struct device *dev); |
||
505 | static int vortex_rx(struct device *dev); |
||
506 | static int boomerang_rx(struct device *dev); |
||
507 | static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs); |
||
508 | static int vortex_close(struct device *dev); |
||
509 | static void update_stats(long ioaddr, struct device *dev); |
||
510 | static struct net_device_stats *vortex_get_stats(struct device *dev); |
||
511 | static void set_rx_mode(struct device *dev); |
||
512 | static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd); |
||
513 | |||
514 | |||
515 | /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */ |
||
516 | /* Option count limit only -- unlimited interfaces are supported. */ |
||
517 | #define MAX_UNITS 8 |
||
518 | static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1,}; |
||
519 | static int full_duplex[MAX_UNITS] = {-1, -1, -1, -1, -1, -1, -1, -1}; |
||
520 | /* A list of all installed Vortex devices, for removing the driver module. */ |
||
521 | static struct device *root_vortex_dev = NULL; |
||
522 | |||
523 | #ifdef MODULE |
||
524 | #ifndef CARDBUS |
||
525 | /* Variables to work-around the Compaq PCI BIOS32 problem. */ |
||
526 | static int compaq_ioaddr = 0, compaq_irq = 0, compaq_device_id = 0x5900; |
||
527 | #endif |
||
528 | |||
529 | #ifdef CARDBUS |
||
530 | |||
531 | #include <pcmcia/driver_ops.h> |
||
532 | |||
533 | static dev_node_t *vortex_attach(dev_locator_t *loc) |
||
534 | { |
||
535 | u16 dev_id, vendor_id; |
||
536 | u32 io; |
||
537 | u8 bus, devfn, irq; |
||
538 | struct device *dev; |
||
539 | int chip_idx; |
||
540 | |||
541 | if (loc->bus != LOC_PCI) return NULL; |
||
542 | bus = loc->b.pci.bus; devfn = loc->b.pci.devfn; |
||
543 | pcibios_read_config_dword(bus, devfn, PCI_BASE_ADDRESS_0, &io); |
||
544 | pcibios_read_config_byte(bus, devfn, PCI_INTERRUPT_LINE, &irq); |
||
545 | pcibios_read_config_word(bus, devfn, PCI_VENDOR_ID, &vendor_id); |
||
546 | pcibios_read_config_word(bus, devfn, PCI_DEVICE_ID, &dev_id); |
||
547 | printk(KERN_INFO "vortex_attach(bus %d, function %d, device %4.4x)\n", |
||
548 | bus, devfn, dev_id); |
||
549 | io &= ~3; |
||
550 | if (io == 0 || irq == 0) { |
||
551 | printk(KERN_ERR "The 3Com CardBus Ethernet interface was not " |
||
552 | "assigned an %s.\n" KERN_ERR " It will not be activated.\n", |
||
553 | io == 0 ? "I/O address" : "IRQ"); |
||
554 | return NULL; |
||
555 | } |
||
556 | for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) |
||
557 | if (vendor_id == pci_tbl[chip_idx].vendor_id |
||
558 | && (dev_id & pci_tbl[chip_idx].device_id_mask) == |
||
559 | pci_tbl[chip_idx].device_id) |
||
560 | break; |
||
561 | if (pci_tbl[chip_idx].vendor_id == 0) { /* Compiled out! */ |
||
562 | printk(KERN_INFO "Unable to match chip type %4.4x %4.4x in " |
||
563 | "vortex_attach().\n", vendor_id, dev_id); |
||
564 | return NULL; |
||
565 | } |
||
566 | dev = vortex_probe1(bus, devfn, NULL, io, irq, chip_idx, MAX_UNITS+1); |
||
567 | if (dev) { |
||
568 | dev_node_t *node = kmalloc(sizeof(dev_node_t), GFP_KERNEL); |
||
569 | strcpy(node->dev_name, dev->name); |
||
570 | node->major = node->minor = 0; |
||
571 | node->next = NULL; |
||
572 | MOD_INC_USE_COUNT; |
||
573 | return node; |
||
574 | } |
||
575 | return NULL; |
||
576 | } |
||
577 | |||
578 | static void vortex_detach(dev_node_t *node) |
||
579 | { |
||
580 | struct device **devp, **next; |
||
581 | printk(KERN_INFO "vortex_detach(%s)\n", node->dev_name); |
||
582 | for (devp = &root_vortex_dev; *devp; devp = next) { |
||
583 | next = &((struct vortex_private *)(*devp)->priv)->next_module; |
||
584 | if (strcmp((*devp)->name, node->dev_name) == 0) break; |
||
585 | } |
||
586 | if (*devp) { |
||
587 | struct device *dev = *devp; |
||
588 | struct vortex_private *vp = dev->priv; |
||
589 | if (dev->flags & IFF_UP) |
||
590 | vortex_close(dev); |
||
591 | dev->flags &= ~(IFF_UP|IFF_RUNNING); |
||
592 | unregister_netdev(dev); |
||
593 | if (vp->cb_fn_base) iounmap(vp->cb_fn_base); |
||
594 | kfree(dev); |
||
595 | *devp = *next; |
||
596 | kfree(vp); |
||
597 | kfree(node); |
||
598 | MOD_DEC_USE_COUNT; |
||
599 | } |
||
600 | } |
||
601 | |||
602 | struct driver_operations vortex_ops = { |
||
603 | "3c575_cb", vortex_attach, NULL, NULL, vortex_detach |
||
604 | }; |
||
605 | |||
606 | #endif /* Cardbus support */ |
||
607 | |||
608 | |||
609 | int init_module(void) |
||
610 | { |
||
611 | if (vortex_debug) |
||
612 | printk(KERN_INFO "%s", version); |
||
613 | #ifdef CARDBUS |
||
614 | register_driver(&vortex_ops); |
||
615 | return 0; |
||
616 | #else |
||
617 | return vortex_scan(0, pci_tbl); |
||
618 | #endif |
||
619 | } |
||
620 | |||
621 | #else |
||
622 | int tc59x_probe(struct device *dev) |
||
623 | { |
||
624 | static int scanned=0; |
||
625 | if(scanned++) |
||
626 | return -ENODEV; |
||
627 | printk(KERN_INFO "%s", version); |
||
628 | return vortex_scan(dev, pci_tbl); |
||
629 | } |
||
630 | #endif /* not MODULE */ |
||
631 | |||
632 | #ifndef CARDBUS |
||
633 | static int vortex_scan(struct device *dev, struct pci_id_info pci_tbl[]) |
||
634 | { |
||
635 | int cards_found = 0; |
||
636 | |||
637 | /* Allow an EISA-only driver. */ |
||
638 | #if defined(CONFIG_PCI) || (defined(MODULE) && !defined(NO_PCI)) |
||
639 | /* Ideally we would detect all cards in slot order. That would |
||
640 | be best done a central PCI probe dispatch, which wouldn't work |
||
641 | well with the current structure. So instead we detect 3Com cards |
||
642 | in slot order. */ |
||
643 | if (pcibios_present()) { |
||
644 | static int pci_index = 0; |
||
645 | unsigned char pci_bus, pci_device_fn; |
||
646 | |||
647 | for (;pci_index < 0xff; pci_index++) { |
||
648 | u16 vendor, device, pci_command, new_command, pwr_cmd; |
||
649 | int chip_idx, irq; |
||
650 | long ioaddr; |
||
651 | |||
652 | if (pcibios_find_class (PCI_CLASS_NETWORK_ETHERNET << 8, pci_index, |
||
653 | &pci_bus, &pci_device_fn) |
||
654 | != PCIBIOS_SUCCESSFUL) |
||
655 | break; |
||
656 | pcibios_read_config_word(pci_bus, pci_device_fn, |
||
657 | PCI_VENDOR_ID, &vendor); |
||
658 | pcibios_read_config_word(pci_bus, pci_device_fn, |
||
659 | PCI_DEVICE_ID, &device); |
||
660 | for (chip_idx = 0; pci_tbl[chip_idx].vendor_id; chip_idx++) |
||
661 | if (vendor == pci_tbl[chip_idx].vendor_id |
||
662 | && (device & pci_tbl[chip_idx].device_id_mask) == |
||
663 | pci_tbl[chip_idx].device_id) |
||
664 | break; |
||
665 | if (pci_tbl[chip_idx].vendor_id == 0) /* Compiled out! */ |
||
666 | continue; |
||
667 | |||
668 | { |
||
669 | #if LINUX_VERSION_CODE >= 0x20155 |
||
670 | struct pci_dev *pdev = pci_find_slot(pci_bus, pci_device_fn); |
||
671 | ioaddr = pdev->base_address[0] & ~3; |
||
672 | irq = pdev->irq; |
||
673 | #else |
||
674 | u32 pci_ioaddr; |
||
675 | u8 pci_irq_line; |
||
676 | pcibios_read_config_byte(pci_bus, pci_device_fn, |
||
677 | PCI_INTERRUPT_LINE, &pci_irq_line); |
||
678 | pcibios_read_config_dword(pci_bus, pci_device_fn, |
||
679 | PCI_BASE_ADDRESS_0, &pci_ioaddr); |
||
680 | ioaddr = pci_ioaddr & ~3;; |
||
681 | irq = pci_irq_line; |
||
682 | #endif |
||
683 | } |
||
684 | |||
685 | /* Power-up the card. */ |
||
686 | pcibios_read_config_word(pci_bus, pci_device_fn, |
||
687 | 0xe0, &pwr_cmd); |
||
688 | if (pwr_cmd & 0x3) { |
||
689 | /* Save the ioaddr and IRQ info! */ |
||
690 | printk(KERN_INFO " A 3Com network adapter is powered down!" |
||
691 | " Setting the power state %4.4x->%4.4x.\n", |
||
692 | pwr_cmd, pwr_cmd & ~3); |
||
693 | pcibios_write_config_word(pci_bus, pci_device_fn, |
||
694 | 0xe0, pwr_cmd & ~3); |
||
695 | printk(KERN_INFO " Setting the IRQ to %d, IOADDR to %#lx.\n", |
||
696 | irq, ioaddr); |
||
697 | pcibios_write_config_byte(pci_bus, pci_device_fn, |
||
698 | PCI_INTERRUPT_LINE, irq); |
||
699 | pcibios_write_config_dword(pci_bus, pci_device_fn, |
||
700 | PCI_BASE_ADDRESS_0, ioaddr); |
||
701 | } |
||
702 | |||
703 | if (ioaddr == 0) { |
||
704 | printk(KERN_WARNING " A 3Com network adapter has been found, " |
||
705 | "however it has not been assigned an I/O address.\n" |
||
706 | " You may need to power-cycle the machine for this " |
||
707 | "device to work!\n"); |
||
708 | continue; |
||
709 | } |
||
710 | |||
711 | if (check_region(ioaddr, pci_tbl[chip_idx].io_size)) |
||
712 | continue; |
||
713 | |||
714 | /* Activate the card. */ |
||
715 | pcibios_read_config_word(pci_bus, pci_device_fn, |
||
716 | PCI_COMMAND, &pci_command); |
||
717 | new_command = pci_command | PCI_COMMAND_MASTER|PCI_COMMAND_IO; |
||
718 | if (pci_command != new_command) { |
||
719 | printk(KERN_INFO " The PCI BIOS has not enabled the device " |
||
720 | "at %d/%d. Updating PCI command %4.4x->%4.4x.\n", |
||
721 | pci_bus, pci_device_fn, pci_command, new_command); |
||
722 | pcibios_write_config_word(pci_bus, pci_device_fn, |
||
723 | PCI_COMMAND, new_command); |
||
724 | } |
||
725 | |||
726 | dev = vortex_probe1(pci_bus, pci_device_fn, dev, ioaddr, irq, |
||
727 | chip_idx, cards_found); |
||
728 | |||
729 | if (dev) { |
||
730 | /* Get and check the latency values. On the 3c590 series |
||
731 | the latency timer must be set to the maximum value to avoid |
||
732 | data corruption that occurs when the timer expires during |
||
733 | a transfer -- a bug in the Vortex chip only. */ |
||
734 | u8 pci_latency; |
||
735 | u8 new_latency = (device & 0xff00) == 0x5900 ? 248 : 32; |
||
736 | |||
737 | pcibios_read_config_byte(pci_bus, pci_device_fn, |
||
738 | PCI_LATENCY_TIMER, &pci_latency); |
||
739 | if (pci_latency < new_latency) { |
||
740 | printk(KERN_INFO "%s: Overriding PCI latency" |
||
741 | " timer (CFLT) setting of %d, new value is %d.\n", |
||
742 | dev->name, pci_latency, new_latency); |
||
743 | pcibios_write_config_byte(pci_bus, pci_device_fn, |
||
744 | PCI_LATENCY_TIMER, new_latency); |
||
745 | } |
||
746 | dev = 0; |
||
747 | cards_found++; |
||
748 | } |
||
749 | } |
||
750 | } |
||
751 | #endif /* NO_PCI */ |
||
752 | |||
753 | /* Now check all slots of the EISA bus. */ |
||
754 | if (EISA_bus) { |
||
755 | static long ioaddr = 0x1000; |
||
756 | for ( ; ioaddr < 0x9000; ioaddr += 0x1000) { |
||
757 | int device_id; |
||
758 | if (check_region(ioaddr, VORTEX_TOTAL_SIZE)) |
||
759 | continue; |
||
760 | /* Check the standard EISA ID register for an encoded '3Com'. */ |
||
761 | if (inw(ioaddr + 0xC80) != 0x6d50) |
||
762 | continue; |
||
763 | /* Check for a product that we support, 3c59{2,7} any rev. */ |
||
764 | device_id = (inb(ioaddr + 0xC82)<<8) + inb(ioaddr + 0xC83); |
||
765 | if ((device_id & 0xFF00) != 0x5900) |
||
766 | continue; |
||
767 | vortex_probe1(0, 0, dev, ioaddr, inw(ioaddr + 0xC88) >> 12, |
||
768 | 4, cards_found); |
||
769 | dev = 0; |
||
770 | cards_found++; |
||
771 | } |
||
772 | } |
||
773 | |||
774 | #ifdef MODULE |
||
775 | /* Special code to work-around the Compaq PCI BIOS32 problem. */ |
||
776 | if (compaq_ioaddr) { |
||
777 | vortex_probe1(0, 0, dev, compaq_ioaddr, compaq_irq, |
||
778 | compaq_device_id, cards_found++); |
||
779 | dev = 0; |
||
780 | } |
||
781 | #endif |
||
782 | |||
783 | return cards_found ? 0 : -ENODEV; |
||
784 | } |
||
785 | #endif /* ! Cardbus */ |
||
786 | |||
787 | static struct device *vortex_probe1(int pci_bus, int pci_devfn, |
||
788 | struct device *dev, long ioaddr, |
||
789 | int irq, int chip_idx, int card_idx) |
||
790 | { |
||
791 | struct vortex_private *vp; |
||
792 | int option; |
||
793 | unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */ |
||
794 | int i; |
||
795 | |||
796 | dev = init_etherdev(dev, 0); |
||
797 | |||
798 | printk(KERN_INFO "%s: 3Com %s at 0x%lx, ", |
||
799 | dev->name, pci_tbl[chip_idx].name, ioaddr); |
||
800 | |||
801 | dev->base_addr = ioaddr; |
||
802 | dev->irq = irq; |
||
803 | dev->mtu = mtu; |
||
804 | |||
805 | /* Make certain the descriptor lists are aligned. */ |
||
806 | { |
||
807 | void *mem = kmalloc(sizeof(*vp) + 15, GFP_KERNEL); |
||
808 | vp = (void *)(((long)mem + 15) & ~15); |
||
809 | vp->priv_addr = mem; |
||
810 | } |
||
811 | memset(vp, 0, sizeof(*vp)); |
||
812 | dev->priv = vp; |
||
813 | |||
814 | vp->next_module = root_vortex_dev; |
||
815 | root_vortex_dev = dev; |
||
816 | |||
817 | vp->chip_id = chip_idx; |
||
818 | vp->pci_bus = pci_bus; |
||
819 | vp->pci_devfn = pci_devfn; |
||
820 | |||
821 | /* The lower four bits are the media type. */ |
||
822 | if (dev->mem_start) |
||
823 | option = dev->mem_start; |
||
824 | else if (card_idx < MAX_UNITS) |
||
825 | option = options[card_idx]; |
||
826 | else |
||
827 | option = -1; |
||
828 | |||
829 | if (option >= 0) { |
||
830 | vp->media_override = ((option & 7) == 2) ? 0 : option & 7; |
||
831 | vp->full_duplex = (option & 8) ? 1 : 0; |
||
832 | vp->bus_master = (option & 16) ? 1 : 0; |
||
833 | } else { |
||
834 | vp->media_override = 7; |
||
835 | vp->full_duplex = 0; |
||
836 | vp->bus_master = 0; |
||
837 | } |
||
838 | if (card_idx < MAX_UNITS && full_duplex[card_idx] > 0) |
||
839 | vp->full_duplex = 1; |
||
840 | |||
841 | vp->force_fd = vp->full_duplex; |
||
842 | vp->options = option; |
||
843 | |||
844 | /* Read the station address from the EEPROM. */ |
||
845 | EL3WINDOW(0); |
||
846 | for (i = 0; i < 0x40; i++) { |
||
847 | int timer; |
||
848 | #ifdef CARDBUS |
||
849 | outw(0x230 + i, ioaddr + Wn0EepromCmd); |
||
850 | #else |
||
851 | outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd); |
||
852 | #endif |
||
853 | /* Pause for at least 162 us. for the read to take place. */ |
||
854 | for (timer = 10; timer >= 0; timer--) { |
||
855 | udelay(162); |
||
856 | if ((inw(ioaddr + Wn0EepromCmd) & 0x8000) == 0) |
||
857 | break; |
||
858 | } |
||
859 | eeprom[i] = inw(ioaddr + Wn0EepromData); |
||
860 | } |
||
861 | for (i = 0; i < 0x18; i++) |
||
862 | checksum ^= eeprom[i]; |
||
863 | checksum = (checksum ^ (checksum >> 8)) & 0xff; |
||
864 | if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */ |
||
865 | while (i < 0x21) |
||
866 | checksum ^= eeprom[i++]; |
||
867 | checksum = (checksum ^ (checksum >> 8)) & 0xff; |
||
868 | } |
||
869 | if (checksum != 0x00) |
||
870 | printk(" ***INVALID CHECKSUM %4.4x*** ", checksum); |
||
871 | |||
872 | for (i = 0; i < 3; i++) |
||
873 | ((u16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]); |
||
874 | for (i = 0; i < 6; i++) |
||
875 | printk("%c%2.2x", i ? ':' : ' ', dev->dev_addr[i]); |
||
876 | #ifdef __sparc__ |
||
877 | printk(", IRQ %s\n", __irq_itoa(dev->irq)); |
||
878 | #else |
||
879 | printk(", IRQ %d\n", dev->irq); |
||
880 | /* Tell them about an invalid IRQ. */ |
||
881 | if (vortex_debug && (dev->irq <= 0 || dev->irq >= NR_IRQS)) |
||
882 | printk(KERN_WARNING " *** Warning: IRQ %d is unlikely to work! ***\n", |
||
883 | dev->irq); |
||
884 | #endif |
||
885 | |||
886 | if (pci_tbl[vp->chip_id].drv_flags & HAS_CB_FNS) { |
||
887 | u32 fn_st_addr; /* Cardbus function status space */ |
||
888 | pcibios_read_config_dword(pci_bus, pci_devfn, PCI_BASE_ADDRESS_2, |
||
889 | &fn_st_addr); |
||
890 | if (fn_st_addr) |
||
891 | vp->cb_fn_base = ioremap(fn_st_addr & ~3, 128); |
||
892 | printk("%s: CardBus functions mapped %8.8x->%p (PCMCIA committee" |
||
893 | " brain-damage).\n", dev->name, fn_st_addr, vp->cb_fn_base); |
||
894 | EL3WINDOW(2); |
||
895 | outw(0x10 | inw(ioaddr + Wn2_ResetOptions), ioaddr + Wn2_ResetOptions); |
||
896 | } |
||
897 | |||
898 | /* Extract our information from the EEPROM data. */ |
||
899 | vp->info1 = eeprom[13]; |
||
900 | vp->info2 = eeprom[15]; |
||
901 | vp->capabilities = eeprom[16]; |
||
902 | |||
903 | if (vp->info1 & 0x8000) |
||
904 | vp->full_duplex = 1; |
||
905 | |||
906 | { |
||
907 | char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"}; |
||
908 | union wn3_config config; |
||
909 | EL3WINDOW(3); |
||
910 | vp->available_media = inw(ioaddr + Wn3_Options); |
||
911 | if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */ |
||
912 | vp->available_media = 0x40; |
||
913 | config.i = inl(ioaddr + Wn3_Config); |
||
914 | if (vortex_debug > 1) |
||
915 | printk(KERN_DEBUG " Internal config register is %4.4x, " |
||
916 | "transceivers %#x.\n", config.i, inw(ioaddr + Wn3_Options)); |
||
917 | printk(KERN_INFO " %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n", |
||
918 | 8 << config.u.ram_size, |
||
919 | config.u.ram_width ? "word" : "byte", |
||
920 | ram_split[config.u.ram_split], |
||
921 | config.u.autoselect ? "autoselect/" : "", |
||
922 | config.u.xcvr > XCVR_ExtMII ? "<invalid transceiver>" : |
||
923 | media_tbl[config.u.xcvr].name); |
||
924 | vp->default_media = config.u.xcvr; |
||
925 | vp->autoselect = config.u.autoselect; |
||
926 | } |
||
927 | |||
928 | if (vp->media_override != 7) { |
||
929 | printk(KERN_INFO " Media override to transceiver type %d (%s).\n", |
||
930 | vp->media_override, media_tbl[vp->media_override].name); |
||
931 | dev->if_port = vp->media_override; |
||
932 | } else |
||
933 | dev->if_port = vp->default_media; |
||
934 | |||
935 | if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
||
936 | int phy, phy_idx = 0; |
||
937 | EL3WINDOW(4); |
||
938 | mii_preamble_required++; |
||
939 | mii_preamble_required++; |
||
940 | mdio_read(ioaddr, 24, 1); |
||
941 | for (phy = 1; phy <= 32 && phy_idx < sizeof(vp->phys); phy++) { |
||
942 | int mii_status, phyx = phy & 0x1f; |
||
943 | mii_status = mdio_read(ioaddr, phyx, 1); |
||
944 | if (mii_status && mii_status != 0xffff) { |
||
945 | vp->phys[phy_idx++] = phyx; |
||
946 | printk(KERN_INFO " MII transceiver found at address %d," |
||
947 | " status %4x.\n", phyx, mii_status); |
||
948 | if ((mii_status & 0x0040) == 0) |
||
949 | mii_preamble_required++; |
||
950 | } |
||
951 | } |
||
952 | mii_preamble_required--; |
||
953 | if (phy_idx == 0) { |
||
954 | printk(KERN_WARNING" ***WARNING*** No MII transceivers found!\n"); |
||
955 | vp->phys[0] = 24; |
||
956 | } else { |
||
957 | vp->advertising = mdio_read(ioaddr, vp->phys[0], 4); |
||
958 | if (vp->full_duplex) { |
||
959 | /* Only advertise the FD media types. */ |
||
960 | vp->advertising &= ~0x02A0; |
||
961 | mdio_write(ioaddr, vp->phys[0], 4, vp->advertising); |
||
962 | } |
||
963 | } |
||
964 | } |
||
965 | |||
966 | if (vp->capabilities & CapBusMaster) { |
||
967 | vp->full_bus_master_tx = 1; |
||
968 | printk(KERN_INFO" Enabling bus-master transmits and %s receives.\n", |
||
969 | (vp->info2 & 1) ? "early" : "whole-frame" ); |
||
970 | vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2; |
||
971 | } |
||
972 | |||
973 | /* We do a request_region() to register /proc/ioports info. */ |
||
974 | request_region(ioaddr, pci_tbl[chip_idx].io_size, dev->name); |
||
975 | |||
976 | /* The 3c59x-specific entries in the device structure. */ |
||
977 | dev->open = &vortex_open; |
||
978 | dev->hard_start_xmit = &vortex_start_xmit; |
||
979 | dev->stop = &vortex_close; |
||
980 | dev->get_stats = &vortex_get_stats; |
||
981 | dev->do_ioctl = &vortex_ioctl; |
||
982 | dev->set_multicast_list = &set_rx_mode; |
||
983 | |||
984 | return dev; |
||
985 | } |
||
986 | |||
987 | |||
988 | static int |
||
989 | vortex_open(struct device *dev) |
||
990 | { |
||
991 | long ioaddr = dev->base_addr; |
||
992 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
993 | union wn3_config config; |
||
994 | int i; |
||
995 | |||
996 | /* Before initializing select the active media port. */ |
||
997 | EL3WINDOW(3); |
||
998 | config.i = inl(ioaddr + Wn3_Config); |
||
999 | |||
1000 | if (vp->media_override != 7) { |
||
1001 | if (vortex_debug > 1) |
||
1002 | printk(KERN_INFO "%s: Media override to transceiver %d (%s).\n", |
||
1003 | dev->name, vp->media_override, |
||
1004 | media_tbl[vp->media_override].name); |
||
1005 | dev->if_port = vp->media_override; |
||
1006 | } else if (vp->autoselect && pci_tbl[vp->chip_id].drv_flags & HAS_NWAY) { |
||
1007 | dev->if_port = XCVR_NWAY; |
||
1008 | } else if (vp->autoselect) { |
||
1009 | /* Find first available media type, starting with 100baseTx. */ |
||
1010 | dev->if_port = XCVR_100baseTx; |
||
1011 | while (! (vp->available_media & media_tbl[dev->if_port].mask)) |
||
1012 | dev->if_port = media_tbl[dev->if_port].next; |
||
1013 | } else |
||
1014 | dev->if_port = vp->default_media; |
||
1015 | |||
1016 | init_timer(&vp->timer); |
||
1017 | vp->timer.expires = RUN_AT(media_tbl[dev->if_port].wait); |
||
1018 | vp->timer.data = (unsigned long)dev; |
||
1019 | vp->timer.function = &vortex_timer; /* timer handler */ |
||
1020 | add_timer(&vp->timer); |
||
1021 | |||
1022 | if (vortex_debug > 1) |
||
1023 | printk(KERN_DEBUG "%s: Initial media type %s.\n", |
||
1024 | dev->name, media_tbl[dev->if_port].name); |
||
1025 | |||
1026 | vp->full_duplex = vp->force_fd; |
||
1027 | config.u.xcvr = dev->if_port; |
||
1028 | outl(config.i, ioaddr + Wn3_Config); |
||
1029 | |||
1030 | if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) { |
||
1031 | int mii_reg1, mii_reg5; |
||
1032 | EL3WINDOW(4); |
||
1033 | /* Read BMSR (reg1) only to clear old status. */ |
||
1034 | mii_reg1 = mdio_read(ioaddr, vp->phys[0], 1); |
||
1035 | mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
||
1036 | if (mii_reg5 == 0xffff || mii_reg5 == 0x0000) |
||
1037 | ; /* No MII device or no link partner report */ |
||
1038 | else if ((mii_reg5 & 0x0100) != 0 /* 100baseTx-FD */ |
||
1039 | || (mii_reg5 & 0x00C0) == 0x0040) /* 10T-FD, but not 100-HD */ |
||
1040 | vp->full_duplex = 1; |
||
1041 | if (vortex_debug > 1) |
||
1042 | printk(KERN_INFO "%s: MII #%d status %4.4x, link partner capability %4.4x," |
||
1043 | " setting %s-duplex.\n", dev->name, vp->phys[0], |
||
1044 | mii_reg1, mii_reg5, vp->full_duplex ? "full" : "half"); |
||
1045 | EL3WINDOW(3); |
||
1046 | } |
||
1047 | |||
1048 | /* Set the full-duplex bit. */ |
||
1049 | outb(((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) | |
||
1050 | (dev->mtu > 1500 ? 0x40 : 0), ioaddr + Wn3_MAC_Ctrl); |
||
1051 | |||
1052 | if (vortex_debug > 1) { |
||
1053 | printk(KERN_DEBUG "%s: vortex_open() InternalConfig %8.8x.\n", |
||
1054 | dev->name, config.i); |
||
1055 | } |
||
1056 | |||
1057 | outw(TxReset, ioaddr + EL3_CMD); |
||
1058 | for (i = 2000; i >= 0 ; i--) |
||
1059 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1060 | break; |
||
1061 | |||
1062 | outw(RxReset, ioaddr + EL3_CMD); |
||
1063 | /* Wait a few ticks for the RxReset command to complete. */ |
||
1064 | for (i = 2000; i >= 0 ; i--) |
||
1065 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1066 | break; |
||
1067 | |||
1068 | outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD); |
||
1069 | |||
1070 | /* Use the now-standard shared IRQ implementation. */ |
||
1071 | if (request_irq(dev->irq, &vortex_interrupt, SA_SHIRQ, dev->name, dev)) { |
||
1072 | return -EAGAIN; |
||
1073 | } |
||
1074 | |||
1075 | if (vortex_debug > 1) { |
||
1076 | EL3WINDOW(4); |
||
1077 | printk(KERN_DEBUG "%s: vortex_open() irq %d media status %4.4x.\n", |
||
1078 | dev->name, dev->irq, inw(ioaddr + Wn4_Media)); |
||
1079 | } |
||
1080 | |||
1081 | /* Set the station address and mask in window 2 each time opened. */ |
||
1082 | EL3WINDOW(2); |
||
1083 | for (i = 0; i < 6; i++) |
||
1084 | outb(dev->dev_addr[i], ioaddr + i); |
||
1085 | for (; i < 12; i+=2) |
||
1086 | outw(0, ioaddr + i); |
||
1087 | |||
1088 | if (dev->if_port == XCVR_10base2) |
||
1089 | /* Start the thinnet transceiver. We should really wait 50ms...*/ |
||
1090 | outw(StartCoax, ioaddr + EL3_CMD); |
||
1091 | if (dev->if_port != XCVR_NWAY) { |
||
1092 | EL3WINDOW(4); |
||
1093 | outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP|Media_SQE)) | |
||
1094 | media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
||
1095 | } |
||
1096 | |||
1097 | /* Switch to the stats window, and clear all stats by reading. */ |
||
1098 | outw(StatsDisable, ioaddr + EL3_CMD); |
||
1099 | EL3WINDOW(6); |
||
1100 | for (i = 0; i < 10; i++) |
||
1101 | inb(ioaddr + i); |
||
1102 | inw(ioaddr + 10); |
||
1103 | inw(ioaddr + 12); |
||
1104 | /* New: On the Vortex we must also clear the BadSSD counter. */ |
||
1105 | EL3WINDOW(4); |
||
1106 | inb(ioaddr + 12); |
||
1107 | /* ..and on the Boomerang we enable the extra statistics bits. */ |
||
1108 | outw(0x0040, ioaddr + Wn4_NetDiag); |
||
1109 | |||
1110 | /* Switch to register set 7 for normal use. */ |
||
1111 | EL3WINDOW(7); |
||
1112 | |||
1113 | if (vp->full_bus_master_rx) { /* Boomerang bus master. */ |
||
1114 | vp->cur_rx = vp->dirty_rx = 0; |
||
1115 | /* Initialize the RxEarly register as recommended. */ |
||
1116 | outw(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1117 | outl(0x0020, ioaddr + PktStatus); |
||
1118 | if (vortex_debug > 2) |
||
1119 | printk(KERN_DEBUG "%s: Filling in the Rx ring.\n", dev->name); |
||
1120 | for (i = 0; i < RX_RING_SIZE; i++) { |
||
1121 | struct sk_buff *skb; |
||
1122 | vp->rx_ring[i].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[i+1])); |
||
1123 | vp->rx_ring[i].status = 0; /* Clear complete bit. */ |
||
1124 | vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG); |
||
1125 | skb = dev_alloc_skb(PKT_BUF_SZ); |
||
1126 | vp->rx_skbuff[i] = skb; |
||
1127 | if (skb == NULL) |
||
1128 | break; /* Bad news! */ |
||
1129 | skb->dev = dev; /* Mark as being used by this device. */ |
||
1130 | #if LINUX_VERSION_CODE >= 0x10300 |
||
1131 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1132 | vp->rx_ring[i].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
||
1133 | #else |
||
1134 | vp->rx_ring[i].addr = virt_to_bus(skb->data); |
||
1135 | #endif |
||
1136 | } |
||
1137 | /* Wrap the ring. */ |
||
1138 | vp->rx_ring[i-1].next = cpu_to_le32(virt_to_bus(&vp->rx_ring[0])); |
||
1139 | outl(virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr); |
||
1140 | } |
||
1141 | if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */ |
||
1142 | dev->hard_start_xmit = &boomerang_start_xmit; |
||
1143 | vp->cur_tx = vp->dirty_tx = 0; |
||
1144 | outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */ |
||
1145 | /* Clear the Tx ring. */ |
||
1146 | for (i = 0; i < TX_RING_SIZE; i++) |
||
1147 | vp->tx_skbuff[i] = 0; |
||
1148 | outl(0, ioaddr + DownListPtr); |
||
1149 | } |
||
1150 | /* Set reciever mode: presumably accept b-case and phys addr only. */ |
||
1151 | set_rx_mode(dev); |
||
1152 | outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */ |
||
1153 | |||
1154 | vp->in_interrupt = 0; |
||
1155 | dev->tbusy = 0; |
||
1156 | dev->interrupt = 0; |
||
1157 | dev->start = 1; |
||
1158 | |||
1159 | outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */ |
||
1160 | outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */ |
||
1161 | /* Allow status bits to be seen. */ |
||
1162 | vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete| |
||
1163 | (vp->full_bus_master_tx ? DownComplete : TxAvailable) | |
||
1164 | (vp->full_bus_master_rx ? UpComplete : RxComplete) | |
||
1165 | (vp->bus_master ? DMADone : 0); |
||
1166 | vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable | RxComplete | |
||
1167 | StatsFull | HostError | TxComplete | IntReq |
||
1168 | | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete; |
||
1169 | outw(vp->status_enable, ioaddr + EL3_CMD); |
||
1170 | /* Ack all pending events, and set active indicator mask. */ |
||
1171 | outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq, |
||
1172 | ioaddr + EL3_CMD); |
||
1173 | outw(vp->intr_enable, ioaddr + EL3_CMD); |
||
1174 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
||
1175 | writel(0x8000, vp->cb_fn_base + 4); |
||
1176 | |||
1177 | MOD_INC_USE_COUNT; |
||
1178 | |||
1179 | return 0; |
||
1180 | } |
||
1181 | |||
1182 | static void vortex_timer(unsigned long data) |
||
1183 | { |
||
1184 | struct device *dev = (struct device *)data; |
||
1185 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1186 | long ioaddr = dev->base_addr; |
||
1187 | int next_tick = 0; |
||
1188 | int ok = 0; |
||
1189 | int media_status, mii_status, old_window; |
||
1190 | |||
1191 | if (vortex_debug > 1) |
||
1192 | printk(KERN_DEBUG "%s: Media selection timer tick happened, %s.\n", |
||
1193 | dev->name, media_tbl[dev->if_port].name); |
||
1194 | |||
1195 | disable_irq(dev->irq); |
||
1196 | old_window = inw(ioaddr + EL3_CMD) >> 13; |
||
1197 | EL3WINDOW(4); |
||
1198 | media_status = inw(ioaddr + Wn4_Media); |
||
1199 | switch (dev->if_port) { |
||
1200 | case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx: |
||
1201 | if (media_status & Media_LnkBeat) { |
||
1202 | ok = 1; |
||
1203 | if (vortex_debug > 1) |
||
1204 | printk(KERN_DEBUG "%s: Media %s has link beat, %x.\n", |
||
1205 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1206 | } else if (vortex_debug > 1) |
||
1207 | printk(KERN_DEBUG "%s: Media %s is has no link beat, %x.\n", |
||
1208 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1209 | break; |
||
1210 | case XCVR_MII: case XCVR_NWAY: |
||
1211 | mii_status = mdio_read(ioaddr, vp->phys[0], 1); |
||
1212 | ok = 1; |
||
1213 | if (debug > 1) |
||
1214 | printk(KERN_DEBUG "%s: MII transceiver has status %4.4x.\n", |
||
1215 | dev->name, mii_status); |
||
1216 | if (mii_status & 0x0004) { |
||
1217 | int mii_reg5 = mdio_read(ioaddr, vp->phys[0], 5); |
||
1218 | if (! vp->force_fd && mii_reg5 != 0xffff) { |
||
1219 | int duplex = (mii_reg5&0x0100) || |
||
1220 | (mii_reg5 & 0x01C0) == 0x0040; |
||
1221 | if (vp->full_duplex != duplex) { |
||
1222 | vp->full_duplex = duplex; |
||
1223 | printk(KERN_INFO "%s: Setting %s-duplex based on MII " |
||
1224 | "#%d link partner capability of %4.4x.\n", |
||
1225 | dev->name, vp->full_duplex ? "full" : "half", |
||
1226 | vp->phys[0], mii_reg5); |
||
1227 | /* Set the full-duplex bit. */ |
||
1228 | outb((vp->full_duplex ? 0x20 : 0) | |
||
1229 | (dev->mtu > 1500 ? 0x40 : 0), |
||
1230 | ioaddr + Wn3_MAC_Ctrl); |
||
1231 | } |
||
1232 | next_tick = 60*HZ; |
||
1233 | } |
||
1234 | } |
||
1235 | break; |
||
1236 | default: /* Other media types handled by Tx timeouts. */ |
||
1237 | if (vortex_debug > 1) |
||
1238 | printk(KERN_DEBUG "%s: Media %s is has no indication, %x.\n", |
||
1239 | dev->name, media_tbl[dev->if_port].name, media_status); |
||
1240 | ok = 1; |
||
1241 | } |
||
1242 | if ( ! ok) { |
||
1243 | union wn3_config config; |
||
1244 | |||
1245 | do { |
||
1246 | dev->if_port = media_tbl[dev->if_port].next; |
||
1247 | } while ( ! (vp->available_media & media_tbl[dev->if_port].mask)); |
||
1248 | if (dev->if_port == XCVR_Default) { /* Go back to default. */ |
||
1249 | dev->if_port = vp->default_media; |
||
1250 | if (vortex_debug > 1) |
||
1251 | printk(KERN_DEBUG "%s: Media selection failing, using default " |
||
1252 | "%s port.\n", |
||
1253 | dev->name, media_tbl[dev->if_port].name); |
||
1254 | } else { |
||
1255 | if (vortex_debug > 1) |
||
1256 | printk(KERN_DEBUG "%s: Media selection failed, now trying " |
||
1257 | "%s port.\n", |
||
1258 | dev->name, media_tbl[dev->if_port].name); |
||
1259 | next_tick = media_tbl[dev->if_port].wait; |
||
1260 | } |
||
1261 | outw((media_status & ~(Media_10TP|Media_SQE)) | |
||
1262 | media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media); |
||
1263 | |||
1264 | EL3WINDOW(3); |
||
1265 | config.i = inl(ioaddr + Wn3_Config); |
||
1266 | config.u.xcvr = dev->if_port; |
||
1267 | outl(config.i, ioaddr + Wn3_Config); |
||
1268 | |||
1269 | outw(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax, |
||
1270 | ioaddr + EL3_CMD); |
||
1271 | } |
||
1272 | EL3WINDOW(old_window); |
||
1273 | enable_irq(dev->irq); |
||
1274 | |||
1275 | if (vortex_debug > 2) |
||
1276 | printk(KERN_DEBUG "%s: Media selection timer finished, %s.\n", |
||
1277 | dev->name, media_tbl[dev->if_port].name); |
||
1278 | |||
1279 | if (next_tick) { |
||
1280 | vp->timer.expires = RUN_AT(next_tick); |
||
1281 | add_timer(&vp->timer); |
||
1282 | } |
||
1283 | return; |
||
1284 | } |
||
1285 | |||
1286 | static void vortex_tx_timeout(struct device *dev) |
||
1287 | { |
||
1288 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1289 | long ioaddr = dev->base_addr; |
||
1290 | int j; |
||
1291 | |||
1292 | printk(KERN_ERR "%s: transmit timed out, tx_status %2.2x status %4.4x.\n", |
||
1293 | dev->name, inb(ioaddr + TxStatus), |
||
1294 | inw(ioaddr + EL3_STATUS)); |
||
1295 | /* Slight code bloat to be user friendly. */ |
||
1296 | if ((inb(ioaddr + TxStatus) & 0x88) == 0x88) |
||
1297 | printk(KERN_ERR "%s: Transmitter encountered 16 collisions --" |
||
1298 | " network cable problem?\n", dev->name); |
||
1299 | if (inw(ioaddr + EL3_STATUS) & IntLatch) { |
||
1300 | printk(KERN_ERR "%s: Interrupt posted but not delivered --" |
||
1301 | " IRQ blocked by another device?\n", dev->name); |
||
1302 | /* Bad idea here.. but we might as well handle a few events. */ |
||
1303 | vortex_interrupt(dev->irq, dev, 0); |
||
1304 | } |
||
1305 | outw(TxReset, ioaddr + EL3_CMD); |
||
1306 | for (j = 200; j >= 0 ; j--) |
||
1307 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1308 | break; |
||
1309 | |||
1310 | #if ! defined(final_version) && LINUX_VERSION_CODE >= 0x10300 |
||
1311 | if (vp->full_bus_master_tx) { |
||
1312 | int i; |
||
1313 | printk(KERN_DEBUG " Flags; bus-master %d, full %d; dirty %d " |
||
1314 | "current %d.\n", |
||
1315 | vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx, vp->cur_tx); |
||
1316 | printk(KERN_DEBUG " Transmit list %8.8x vs. %p.\n", |
||
1317 | inl(ioaddr + DownListPtr), |
||
1318 | &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]); |
||
1319 | for (i = 0; i < TX_RING_SIZE; i++) { |
||
1320 | printk(KERN_DEBUG " %d: @%p length %8.8x status %8.8x\n", i, |
||
1321 | &vp->tx_ring[i], |
||
1322 | le32_to_cpu(vp->tx_ring[i].length), |
||
1323 | le32_to_cpu(vp->tx_ring[i].status)); |
||
1324 | } |
||
1325 | } |
||
1326 | #endif |
||
1327 | vp->stats.tx_errors++; |
||
1328 | if (vp->full_bus_master_tx) { |
||
1329 | if (vortex_debug > 0) |
||
1330 | printk(KERN_DEBUG "%s: Resetting the Tx ring pointer.\n", |
||
1331 | dev->name); |
||
1332 | if (vp->cur_tx - vp->dirty_tx > 0 && inl(ioaddr + DownListPtr) == 0) |
||
1333 | outl(virt_to_bus(&vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]), |
||
1334 | ioaddr + DownListPtr); |
||
1335 | if (vp->tx_full && (vp->cur_tx - vp->dirty_tx <= TX_RING_SIZE - 1)) { |
||
1336 | vp->tx_full = 0; |
||
1337 | clear_bit(0, (void*)&dev->tbusy); |
||
1338 | } |
||
1339 | outb(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); |
||
1340 | outw(DownUnstall, ioaddr + EL3_CMD); |
||
1341 | } else |
||
1342 | vp->stats.tx_dropped++; |
||
1343 | |||
1344 | /* Issue Tx Enable */ |
||
1345 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1346 | dev->trans_start = jiffies; |
||
1347 | |||
1348 | /* Switch to register set 7 for normal use. */ |
||
1349 | EL3WINDOW(7); |
||
1350 | } |
||
1351 | |||
1352 | /* |
||
1353 | * Handle uncommon interrupt sources. This is a separate routine to minimize |
||
1354 | * the cache impact. |
||
1355 | */ |
||
1356 | static void |
||
1357 | vortex_error(struct device *dev, int status) |
||
1358 | { |
||
1359 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1360 | long ioaddr = dev->base_addr; |
||
1361 | int do_tx_reset = 0; |
||
1362 | int i; |
||
1363 | |||
1364 | if (status & TxComplete) { /* Really "TxError" for us. */ |
||
1365 | unsigned char tx_status = inb(ioaddr + TxStatus); |
||
1366 | /* Presumably a tx-timeout. We must merely re-enable. */ |
||
1367 | if (vortex_debug > 2 |
||
1368 | || (tx_status != 0x88 && vortex_debug > 0)) |
||
1369 | printk(KERN_DEBUG"%s: Transmit error, Tx status register %2.2x.\n", |
||
1370 | dev->name, tx_status); |
||
1371 | if (tx_status & 0x14) vp->stats.tx_fifo_errors++; |
||
1372 | if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
||
1373 | outb(0, ioaddr + TxStatus); |
||
1374 | if (tx_status & 0x30) |
||
1375 | do_tx_reset = 1; |
||
1376 | else /* Merely re-enable the transmitter. */ |
||
1377 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1378 | } |
||
1379 | if (status & RxEarly) { /* Rx early is unused. */ |
||
1380 | vortex_rx(dev); |
||
1381 | outw(AckIntr | RxEarly, ioaddr + EL3_CMD); |
||
1382 | } |
||
1383 | if (status & StatsFull) { /* Empty statistics. */ |
||
1384 | static int DoneDidThat = 0; |
||
1385 | if (vortex_debug > 4) |
||
1386 | printk(KERN_DEBUG "%s: Updating stats.\n", dev->name); |
||
1387 | update_stats(ioaddr, dev); |
||
1388 | /* HACK: Disable statistics as an interrupt source. */ |
||
1389 | /* This occurs when we have the wrong media type! */ |
||
1390 | if (DoneDidThat == 0 && |
||
1391 | inw(ioaddr + EL3_STATUS) & StatsFull) { |
||
1392 | printk(KERN_WARNING "%s: Updating statistics failed, disabling " |
||
1393 | "stats as an interrupt source.\n", dev->name); |
||
1394 | EL3WINDOW(5); |
||
1395 | outw(SetIntrEnb | (inw(ioaddr + 10) & ~StatsFull), ioaddr + EL3_CMD); |
||
1396 | EL3WINDOW(7); |
||
1397 | DoneDidThat++; |
||
1398 | } |
||
1399 | } |
||
1400 | if (status & IntReq) { /* Restore all interrupt sources. */ |
||
1401 | outw(vp->status_enable, ioaddr + EL3_CMD); |
||
1402 | outw(vp->intr_enable, ioaddr + EL3_CMD); |
||
1403 | } |
||
1404 | if (status & HostError) { |
||
1405 | u16 fifo_diag; |
||
1406 | EL3WINDOW(4); |
||
1407 | fifo_diag = inw(ioaddr + Wn4_FIFODiag); |
||
1408 | if (vortex_debug > 0) |
||
1409 | printk(KERN_ERR "%s: Host error, FIFO diagnostic register %4.4x.\n", |
||
1410 | dev->name, fifo_diag); |
||
1411 | /* Adapter failure requires Tx/Rx reset and reinit. */ |
||
1412 | if (vp->full_bus_master_tx) { |
||
1413 | outw(TotalReset | 0xff, ioaddr + EL3_CMD); |
||
1414 | for (i = 2000; i >= 0 ; i--) |
||
1415 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1416 | break; |
||
1417 | /* Re-enable the receiver. */ |
||
1418 | outw(RxEnable, ioaddr + EL3_CMD); |
||
1419 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1420 | } else if (fifo_diag & 0x0400) |
||
1421 | do_tx_reset = 1; |
||
1422 | if (fifo_diag & 0x3000) { |
||
1423 | outw(RxReset, ioaddr + EL3_CMD); |
||
1424 | for (i = 2000; i >= 0 ; i--) |
||
1425 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1426 | break; |
||
1427 | /* Set the Rx filter to the current state. */ |
||
1428 | set_rx_mode(dev); |
||
1429 | outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */ |
||
1430 | outw(AckIntr | HostError, ioaddr + EL3_CMD); |
||
1431 | } |
||
1432 | } |
||
1433 | if (do_tx_reset) { |
||
1434 | int j; |
||
1435 | outw(TxReset, ioaddr + EL3_CMD); |
||
1436 | for (j = 200; j >= 0 ; j--) |
||
1437 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1438 | break; |
||
1439 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1440 | } |
||
1441 | |||
1442 | } |
||
1443 | |||
1444 | |||
1445 | static int |
||
1446 | vortex_start_xmit(struct sk_buff *skb, struct device *dev) |
||
1447 | { |
||
1448 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1449 | long ioaddr = dev->base_addr; |
||
1450 | |||
1451 | if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
||
1452 | if (jiffies - dev->trans_start >= TX_TIMEOUT) |
||
1453 | vortex_tx_timeout(dev); |
||
1454 | return 1; |
||
1455 | } |
||
1456 | |||
1457 | /* Put out the doubleword header... */ |
||
1458 | outl(skb->len, ioaddr + TX_FIFO); |
||
1459 | if (vp->bus_master) { |
||
1460 | /* Set the bus-master controller to transfer the packet. */ |
||
1461 | outl(virt_to_bus(skb->data), ioaddr + Wn7_MasterAddr); |
||
1462 | outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
||
1463 | vp->tx_skb = skb; |
||
1464 | outw(StartDMADown, ioaddr + EL3_CMD); |
||
1465 | /* dev->tbusy will be cleared at the DMADone interrupt. */ |
||
1466 | } else { |
||
1467 | /* ... and the packet rounded to a doubleword. */ |
||
1468 | outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2); |
||
1469 | DEV_FREE_SKB(skb); |
||
1470 | if (inw(ioaddr + TxFree) > 1536) { |
||
1471 | clear_bit(0, (void*)&dev->tbusy); |
||
1472 | } else |
||
1473 | /* Interrupt us when the FIFO has room for max-sized packet. */ |
||
1474 | outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1475 | } |
||
1476 | |||
1477 | dev->trans_start = jiffies; |
||
1478 | |||
1479 | /* Clear the Tx status stack. */ |
||
1480 | { |
||
1481 | int tx_status; |
||
1482 | int i = 32; |
||
1483 | |||
1484 | while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) { |
||
1485 | if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */ |
||
1486 | if (vortex_debug > 2) |
||
1487 | printk(KERN_DEBUG "%s: Tx error, status %2.2x.\n", |
||
1488 | dev->name, tx_status); |
||
1489 | if (tx_status & 0x04) vp->stats.tx_fifo_errors++; |
||
1490 | if (tx_status & 0x38) vp->stats.tx_aborted_errors++; |
||
1491 | if (tx_status & 0x30) { |
||
1492 | int j; |
||
1493 | outw(TxReset, ioaddr + EL3_CMD); |
||
1494 | for (j = 200; j >= 0 ; j--) |
||
1495 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1496 | break; |
||
1497 | } |
||
1498 | outw(TxEnable, ioaddr + EL3_CMD); |
||
1499 | } |
||
1500 | outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */ |
||
1501 | } |
||
1502 | } |
||
1503 | vp->stats.tx_bytes += skb->len; |
||
1504 | return 0; |
||
1505 | } |
||
1506 | |||
1507 | static int |
||
1508 | boomerang_start_xmit(struct sk_buff *skb, struct device *dev) |
||
1509 | { |
||
1510 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1511 | long ioaddr = dev->base_addr; |
||
1512 | |||
1513 | if (test_and_set_bit(0, (void*)&dev->tbusy) != 0) { |
||
1514 | if (jiffies - dev->trans_start >= TX_TIMEOUT) |
||
1515 | vortex_tx_timeout(dev); |
||
1516 | return 1; |
||
1517 | } else { |
||
1518 | /* Calculate the next Tx descriptor entry. */ |
||
1519 | int entry = vp->cur_tx % TX_RING_SIZE; |
||
1520 | struct boom_tx_desc *prev_entry = |
||
1521 | &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE]; |
||
1522 | unsigned long flags; |
||
1523 | int i; |
||
1524 | |||
1525 | if (vortex_debug > 3) |
||
1526 | printk(KERN_DEBUG "%s: Trying to send a packet, Tx index %d.\n", |
||
1527 | dev->name, vp->cur_tx); |
||
1528 | if (vp->tx_full) { |
||
1529 | if (vortex_debug >0) |
||
1530 | printk(KERN_WARNING "%s: Tx Ring full, refusing to send buffer.\n", |
||
1531 | dev->name); |
||
1532 | return 1; |
||
1533 | } |
||
1534 | vp->tx_skbuff[entry] = skb; |
||
1535 | vp->tx_ring[entry].next = 0; |
||
1536 | vp->tx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->data)); |
||
1537 | vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG); |
||
1538 | vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded); |
||
1539 | |||
1540 | save_flags(flags); |
||
1541 | cli(); |
||
1542 | outw(DownStall, ioaddr + EL3_CMD); |
||
1543 | /* Wait for the stall to complete. */ |
||
1544 | for (i = 600; i >= 0 ; i--) |
||
1545 | if ( (inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0) |
||
1546 | break; |
||
1547 | prev_entry->next = cpu_to_le32(virt_to_bus(&vp->tx_ring[entry])); |
||
1548 | if (inl(ioaddr + DownListPtr) == 0) { |
||
1549 | outl(virt_to_bus(&vp->tx_ring[entry]), ioaddr + DownListPtr); |
||
1550 | queued_packet++; |
||
1551 | } |
||
1552 | outw(DownUnstall, ioaddr + EL3_CMD); |
||
1553 | restore_flags(flags); |
||
1554 | |||
1555 | vp->cur_tx++; |
||
1556 | if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) |
||
1557 | vp->tx_full = 1; |
||
1558 | else { /* Clear previous interrupt enable. */ |
||
1559 | prev_entry->status &= cpu_to_le32(~TxIntrUploaded); |
||
1560 | clear_bit(0, (void*)&dev->tbusy); |
||
1561 | } |
||
1562 | dev->trans_start = jiffies; |
||
1563 | vp->stats.tx_bytes += skb->len; |
||
1564 | return 0; |
||
1565 | } |
||
1566 | } |
||
1567 | |||
1568 | /* The interrupt handler does all of the Rx thread work and cleans up |
||
1569 | after the Tx thread. */ |
||
1570 | static void vortex_interrupt(int irq, void *dev_id, struct pt_regs *regs) |
||
1571 | { |
||
1572 | struct device *dev = dev_id; |
||
1573 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1574 | long ioaddr; |
||
1575 | int latency, status; |
||
1576 | int work_done = max_interrupt_work; |
||
1577 | |||
1578 | #if defined(__i386__) |
||
1579 | /* A lock to prevent simultaneous entry bug on Intel SMP machines. */ |
||
1580 | if (test_and_set_bit(0, (void*)&dev->interrupt)) { |
||
1581 | printk(KERN_ERR"%s: SMP simultaneous entry of an interrupt handler.\n", |
||
1582 | dev->name); |
||
1583 | dev->interrupt = 0; /* Avoid halting machine. */ |
||
1584 | return; |
||
1585 | } |
||
1586 | #else |
||
1587 | if (dev->interrupt) { |
||
1588 | printk(KERN_ERR "%s: Re-entering the interrupt handler.\n", dev->name); |
||
1589 | return; |
||
1590 | } |
||
1591 | dev->interrupt = 1; |
||
1592 | #endif |
||
1593 | |||
1594 | dev->interrupt = 1; |
||
1595 | ioaddr = dev->base_addr; |
||
1596 | latency = inb(ioaddr + Timer); |
||
1597 | status = inw(ioaddr + EL3_STATUS); |
||
1598 | |||
1599 | if (vortex_debug > 4) |
||
1600 | printk(KERN_DEBUG "%s: interrupt, status %4.4x, latency %d ticks.\n", |
||
1601 | dev->name, status, latency); |
||
1602 | do { |
||
1603 | if (vortex_debug > 5) |
||
1604 | printk(KERN_DEBUG "%s: In interrupt loop, status %4.4x.\n", |
||
1605 | dev->name, status); |
||
1606 | if (status & RxComplete) |
||
1607 | vortex_rx(dev); |
||
1608 | if (status & UpComplete) { |
||
1609 | outw(AckIntr | UpComplete, ioaddr + EL3_CMD); |
||
1610 | boomerang_rx(dev); |
||
1611 | } |
||
1612 | |||
1613 | if (status & TxAvailable) { |
||
1614 | if (vortex_debug > 5) |
||
1615 | printk(KERN_DEBUG " TX room bit was handled.\n"); |
||
1616 | /* There's room in the FIFO for a full-sized packet. */ |
||
1617 | outw(AckIntr | TxAvailable, ioaddr + EL3_CMD); |
||
1618 | clear_bit(0, (void*)&dev->tbusy); |
||
1619 | mark_bh(NET_BH); |
||
1620 | } |
||
1621 | |||
1622 | if (status & DownComplete) { |
||
1623 | unsigned int dirty_tx = vp->dirty_tx; |
||
1624 | |||
1625 | while (vp->cur_tx - dirty_tx > 0) { |
||
1626 | int entry = dirty_tx % TX_RING_SIZE; |
||
1627 | if (inl(ioaddr + DownListPtr) == |
||
1628 | virt_to_bus(&vp->tx_ring[entry])) |
||
1629 | break; /* It still hasn't been processed. */ |
||
1630 | if (vp->tx_skbuff[entry]) { |
||
1631 | DEV_FREE_SKB(vp->tx_skbuff[entry]); |
||
1632 | vp->tx_skbuff[entry] = 0; |
||
1633 | } |
||
1634 | /* vp->stats.tx_packets++; Counted below. */ |
||
1635 | dirty_tx++; |
||
1636 | } |
||
1637 | vp->dirty_tx = dirty_tx; |
||
1638 | outw(AckIntr | DownComplete, ioaddr + EL3_CMD); |
||
1639 | if (vp->tx_full && (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) { |
||
1640 | vp->tx_full= 0; |
||
1641 | clear_bit(0, (void*)&dev->tbusy); |
||
1642 | mark_bh(NET_BH); |
||
1643 | } |
||
1644 | } |
||
1645 | if (status & DMADone) { |
||
1646 | if (inw(ioaddr + Wn7_MasterStatus) & 0x1000) { |
||
1647 | outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */ |
||
1648 | DEV_FREE_SKB(vp->tx_skb); /* Release the transfered buffer */ |
||
1649 | if (inw(ioaddr + TxFree) > 1536) { |
||
1650 | clear_bit(0, (void*)&dev->tbusy); |
||
1651 | mark_bh(NET_BH); |
||
1652 | } else /* Interrupt when FIFO has room for max-sized packet. */ |
||
1653 | outw(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD); |
||
1654 | } |
||
1655 | } |
||
1656 | /* Check for all uncommon interrupts at once. */ |
||
1657 | if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) { |
||
1658 | if (status == 0xffff) |
||
1659 | break; |
||
1660 | vortex_error(dev, status); |
||
1661 | } |
||
1662 | |||
1663 | if (--work_done < 0) { |
||
1664 | if ((status & (0x7fe - (UpComplete | DownComplete))) == 0) { |
||
1665 | /* Just ack these and return. */ |
||
1666 | outw(AckIntr | UpComplete | DownComplete, ioaddr + EL3_CMD); |
||
1667 | } else { |
||
1668 | printk(KERN_WARNING "%s: Too much work in interrupt, status " |
||
1669 | "%4.4x. Temporarily disabling functions (%4.4x).\n", |
||
1670 | dev->name, status, SetStatusEnb | ((~status) & 0x7FE)); |
||
1671 | /* Disable all pending interrupts. */ |
||
1672 | outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD); |
||
1673 | outw(AckIntr | 0x7FF, ioaddr + EL3_CMD); |
||
1674 | /* The timer will reenable interrupts. */ |
||
1675 | break; |
||
1676 | } |
||
1677 | } |
||
1678 | /* Acknowledge the IRQ. */ |
||
1679 | outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD); |
||
1680 | if (vp->cb_fn_base) /* The PCMCIA people are idiots. */ |
||
1681 | writel(0x8000, vp->cb_fn_base + 4); |
||
1682 | |||
1683 | } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete)); |
||
1684 | |||
1685 | if (vortex_debug > 4) |
||
1686 | printk(KERN_DEBUG "%s: exiting interrupt, status %4.4x.\n", |
||
1687 | dev->name, status); |
||
1688 | |||
1689 | #if defined(__i386__) |
||
1690 | clear_bit(0, (void*)&dev->interrupt); |
||
1691 | #else |
||
1692 | dev->interrupt = 0; |
||
1693 | #endif |
||
1694 | return; |
||
1695 | } |
||
1696 | |||
1697 | static int vortex_rx(struct device *dev) |
||
1698 | { |
||
1699 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1700 | long ioaddr = dev->base_addr; |
||
1701 | int i; |
||
1702 | short rx_status; |
||
1703 | |||
1704 | if (vortex_debug > 5) |
||
1705 | printk(KERN_DEBUG" In rx_packet(), status %4.4x, rx_status %4.4x.\n", |
||
1706 | inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
||
1707 | while ((rx_status = inw(ioaddr + RxStatus)) > 0) { |
||
1708 | if (rx_status & 0x4000) { /* Error, update stats. */ |
||
1709 | unsigned char rx_error = inb(ioaddr + RxErrors); |
||
1710 | if (vortex_debug > 2) |
||
1711 | printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
||
1712 | vp->stats.rx_errors++; |
||
1713 | if (rx_error & 0x01) vp->stats.rx_over_errors++; |
||
1714 | if (rx_error & 0x02) vp->stats.rx_length_errors++; |
||
1715 | if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
||
1716 | if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
||
1717 | if (rx_error & 0x10) vp->stats.rx_length_errors++; |
||
1718 | } else { |
||
1719 | /* The packet length: up to 4.5K!. */ |
||
1720 | int pkt_len = rx_status & 0x1fff; |
||
1721 | struct sk_buff *skb; |
||
1722 | |||
1723 | skb = dev_alloc_skb(pkt_len + 5); |
||
1724 | if (vortex_debug > 4) |
||
1725 | printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
||
1726 | pkt_len, rx_status); |
||
1727 | if (skb != NULL) { |
||
1728 | skb->dev = dev; |
||
1729 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1730 | /* 'skb_put()' points to the start of sk_buff data area. */ |
||
1731 | if (vp->bus_master && |
||
1732 | ! (inw(ioaddr + Wn7_MasterStatus) & 0x8000)) { |
||
1733 | outl(virt_to_bus(skb_put(skb, pkt_len)), |
||
1734 | ioaddr + Wn7_MasterAddr); |
||
1735 | outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen); |
||
1736 | outw(StartDMAUp, ioaddr + EL3_CMD); |
||
1737 | while (inw(ioaddr + Wn7_MasterStatus) & 0x8000) |
||
1738 | ; |
||
1739 | } else { |
||
1740 | insl(ioaddr + RX_FIFO, skb_put(skb, pkt_len), |
||
1741 | (pkt_len + 3) >> 2); |
||
1742 | } |
||
1743 | outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */ |
||
1744 | skb->protocol = eth_type_trans(skb, dev); |
||
1745 | netif_rx(skb); |
||
1746 | dev->last_rx = jiffies; |
||
1747 | vp->stats.rx_packets++; |
||
1748 | vp->stats.rx_bytes += skb->len; |
||
1749 | /* Wait a limited time to go to next packet. */ |
||
1750 | for (i = 200; i >= 0; i--) |
||
1751 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1752 | break; |
||
1753 | continue; |
||
1754 | } else if (vortex_debug) |
||
1755 | printk(KERN_NOTICE "%s: No memory to allocate a sk_buff of " |
||
1756 | "size %d.\n", dev->name, pkt_len); |
||
1757 | } |
||
1758 | outw(RxDiscard, ioaddr + EL3_CMD); |
||
1759 | vp->stats.rx_dropped++; |
||
1760 | /* Wait a limited time to skip this packet. */ |
||
1761 | for (i = 200; i >= 0; i--) |
||
1762 | if ( ! (inw(ioaddr + EL3_STATUS) & CmdInProgress)) |
||
1763 | break; |
||
1764 | } |
||
1765 | |||
1766 | return 0; |
||
1767 | } |
||
1768 | |||
1769 | static int |
||
1770 | boomerang_rx(struct device *dev) |
||
1771 | { |
||
1772 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1773 | int entry = vp->cur_rx % RX_RING_SIZE; |
||
1774 | long ioaddr = dev->base_addr; |
||
1775 | int rx_status; |
||
1776 | int rx_work_limit = vp->dirty_rx + RX_RING_SIZE - vp->cur_rx; |
||
1777 | |||
1778 | if (vortex_debug > 5) |
||
1779 | printk(KERN_DEBUG " In boomerang_rx(), status %4.4x, rx_status " |
||
1780 | "%4.4x.\n", |
||
1781 | inw(ioaddr+EL3_STATUS), inw(ioaddr+RxStatus)); |
||
1782 | while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){ |
||
1783 | if (--rx_work_limit < 0) |
||
1784 | break; |
||
1785 | if (rx_status & RxDError) { /* Error, update stats. */ |
||
1786 | unsigned char rx_error = rx_status >> 16; |
||
1787 | if (vortex_debug > 2) |
||
1788 | printk(KERN_DEBUG " Rx error: status %2.2x.\n", rx_error); |
||
1789 | vp->stats.rx_errors++; |
||
1790 | if (rx_error & 0x01) vp->stats.rx_over_errors++; |
||
1791 | if (rx_error & 0x02) vp->stats.rx_length_errors++; |
||
1792 | if (rx_error & 0x04) vp->stats.rx_frame_errors++; |
||
1793 | if (rx_error & 0x08) vp->stats.rx_crc_errors++; |
||
1794 | if (rx_error & 0x10) vp->stats.rx_length_errors++; |
||
1795 | } else { |
||
1796 | /* The packet length: up to 4.5K!. */ |
||
1797 | int pkt_len = rx_status & 0x1fff; |
||
1798 | struct sk_buff *skb; |
||
1799 | |||
1800 | vp->stats.rx_bytes += pkt_len; |
||
1801 | if (vortex_debug > 4) |
||
1802 | printk(KERN_DEBUG "Receiving packet size %d status %4.4x.\n", |
||
1803 | pkt_len, rx_status); |
||
1804 | |||
1805 | /* Check if the packet is long enough to just accept without |
||
1806 | copying to a properly sized skbuff. */ |
||
1807 | if (pkt_len < rx_copybreak |
||
1808 | && (skb = dev_alloc_skb(pkt_len + 2)) != 0) { |
||
1809 | skb->dev = dev; |
||
1810 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1811 | /* 'skb_put()' points to the start of sk_buff data area. */ |
||
1812 | memcpy(skb_put(skb, pkt_len), |
||
1813 | bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
||
1814 | pkt_len); |
||
1815 | rx_copy++; |
||
1816 | } else { |
||
1817 | void *temp; |
||
1818 | /* Pass up the skbuff already on the Rx ring. */ |
||
1819 | skb = vp->rx_skbuff[entry]; |
||
1820 | vp->rx_skbuff[entry] = NULL; |
||
1821 | temp = skb_put(skb, pkt_len); |
||
1822 | /* Remove this checking code for final release. */ |
||
1823 | if (bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)) != temp) |
||
1824 | printk(KERN_ERR "%s: Warning -- the skbuff addresses do not match" |
||
1825 | " in boomerang_rx: %p vs. %p.\n", dev->name, |
||
1826 | bus_to_virt(le32_to_cpu(vp->rx_ring[entry].addr)), |
||
1827 | temp); |
||
1828 | rx_nocopy++; |
||
1829 | } |
||
1830 | skb->protocol = eth_type_trans(skb, dev); |
||
1831 | { /* Use hardware checksum info. */ |
||
1832 | int csum_bits = rx_status & 0xee000000; |
||
1833 | if (csum_bits && |
||
1834 | (csum_bits == (IPChksumValid | TCPChksumValid) || |
||
1835 | csum_bits == (IPChksumValid | UDPChksumValid))) { |
||
1836 | skb->ip_summed = CHECKSUM_UNNECESSARY; |
||
1837 | rx_csumhits++; |
||
1838 | } |
||
1839 | } |
||
1840 | netif_rx(skb); |
||
1841 | dev->last_rx = jiffies; |
||
1842 | vp->stats.rx_packets++; |
||
1843 | } |
||
1844 | entry = (++vp->cur_rx) % RX_RING_SIZE; |
||
1845 | } |
||
1846 | /* Refill the Rx ring buffers. */ |
||
1847 | for (; vp->dirty_rx < vp->cur_rx; vp->dirty_rx++) { |
||
1848 | struct sk_buff *skb; |
||
1849 | entry = vp->dirty_rx % RX_RING_SIZE; |
||
1850 | if (vp->rx_skbuff[entry] == NULL) { |
||
1851 | skb = dev_alloc_skb(PKT_BUF_SZ); |
||
1852 | if (skb == NULL) |
||
1853 | break; /* Bad news! */ |
||
1854 | skb->dev = dev; /* Mark as being used by this device. */ |
||
1855 | skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */ |
||
1856 | vp->rx_ring[entry].addr = cpu_to_le32(virt_to_bus(skb->tail)); |
||
1857 | vp->rx_skbuff[entry] = skb; |
||
1858 | } |
||
1859 | vp->rx_ring[entry].status = 0; /* Clear complete bit. */ |
||
1860 | outw(UpUnstall, ioaddr + EL3_CMD); |
||
1861 | } |
||
1862 | return 0; |
||
1863 | } |
||
1864 | |||
1865 | static int |
||
1866 | vortex_close(struct device *dev) |
||
1867 | { |
||
1868 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1869 | long ioaddr = dev->base_addr; |
||
1870 | int i; |
||
1871 | |||
1872 | dev->start = 0; |
||
1873 | dev->tbusy = 1; |
||
1874 | |||
1875 | if (vortex_debug > 1) { |
||
1876 | printk(KERN_DEBUG"%s: vortex_close() status %4.4x, Tx status %2.2x.\n", |
||
1877 | dev->name, inw(ioaddr + EL3_STATUS), inb(ioaddr + TxStatus)); |
||
1878 | printk(KERN_DEBUG "%s: vortex close stats: rx_nocopy %d rx_copy %d" |
||
1879 | " tx_queued %d Rx pre-checksummed %d.\n", |
||
1880 | dev->name, rx_nocopy, rx_copy, queued_packet, rx_csumhits); |
||
1881 | } |
||
1882 | |||
1883 | del_timer(&vp->timer); |
||
1884 | |||
1885 | /* Turn off statistics ASAP. We update vp->stats below. */ |
||
1886 | outw(StatsDisable, ioaddr + EL3_CMD); |
||
1887 | |||
1888 | /* Disable the receiver and transmitter. */ |
||
1889 | outw(RxDisable, ioaddr + EL3_CMD); |
||
1890 | outw(TxDisable, ioaddr + EL3_CMD); |
||
1891 | |||
1892 | if (dev->if_port == XCVR_10base2) |
||
1893 | /* Turn off thinnet power. Green! */ |
||
1894 | outw(StopCoax, ioaddr + EL3_CMD); |
||
1895 | |||
1896 | free_irq(dev->irq, dev); |
||
1897 | |||
1898 | outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD); |
||
1899 | |||
1900 | update_stats(ioaddr, dev); |
||
1901 | if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */ |
||
1902 | outl(0, ioaddr + UpListPtr); |
||
1903 | for (i = 0; i < RX_RING_SIZE; i++) |
||
1904 | if (vp->rx_skbuff[i]) { |
||
1905 | #if LINUX_VERSION_CODE < 0x20100 |
||
1906 | vp->rx_skbuff[i]->free = 1; |
||
1907 | #endif |
||
1908 | DEV_FREE_SKB(vp->rx_skbuff[i]); |
||
1909 | vp->rx_skbuff[i] = 0; |
||
1910 | } |
||
1911 | } |
||
1912 | if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */ |
||
1913 | outl(0, ioaddr + DownListPtr); |
||
1914 | for (i = 0; i < TX_RING_SIZE; i++) |
||
1915 | if (vp->tx_skbuff[i]) { |
||
1916 | DEV_FREE_SKB(vp->tx_skbuff[i]); |
||
1917 | vp->tx_skbuff[i] = 0; |
||
1918 | } |
||
1919 | } |
||
1920 | |||
1921 | MOD_DEC_USE_COUNT; |
||
1922 | |||
1923 | return 0; |
||
1924 | } |
||
1925 | |||
1926 | static struct net_device_stats *vortex_get_stats(struct device *dev) |
||
1927 | { |
||
1928 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1929 | unsigned long flags; |
||
1930 | |||
1931 | if (dev->start) { |
||
1932 | save_flags(flags); |
||
1933 | cli(); |
||
1934 | update_stats(dev->base_addr, dev); |
||
1935 | restore_flags(flags); |
||
1936 | } |
||
1937 | return &vp->stats; |
||
1938 | } |
||
1939 | |||
1940 | /* Update statistics. |
||
1941 | Unlike with the EL3 we need not worry about interrupts changing |
||
1942 | the window setting from underneath us, but we must still guard |
||
1943 | against a race condition with a StatsUpdate interrupt updating the |
||
1944 | table. This is done by checking that the ASM (!) code generated uses |
||
1945 | atomic updates with '+='. |
||
1946 | */ |
||
1947 | static void update_stats(long ioaddr, struct device *dev) |
||
1948 | { |
||
1949 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1950 | |||
1951 | /* Unlike the 3c5x9 we need not turn off stats updates while reading. */ |
||
1952 | /* Switch to the stats window, and read everything. */ |
||
1953 | EL3WINDOW(6); |
||
1954 | vp->stats.tx_carrier_errors += inb(ioaddr + 0); |
||
1955 | vp->stats.tx_heartbeat_errors += inb(ioaddr + 1); |
||
1956 | /* Multiple collisions. */ inb(ioaddr + 2); |
||
1957 | vp->stats.collisions += inb(ioaddr + 3); |
||
1958 | vp->stats.tx_window_errors += inb(ioaddr + 4); |
||
1959 | vp->stats.rx_fifo_errors += inb(ioaddr + 5); |
||
1960 | vp->stats.tx_packets += inb(ioaddr + 6); |
||
1961 | vp->stats.tx_packets += (inb(ioaddr + 9)&0x30) << 4; |
||
1962 | /* Rx packets */ inb(ioaddr + 7); /* Must read to clear */ |
||
1963 | /* Tx deferrals */ inb(ioaddr + 8); |
||
1964 | /* Don't bother with register 9, an extension of registers 6&7. |
||
1965 | If we do use the 6&7 values the atomic update assumption above |
||
1966 | is invalid. */ |
||
1967 | inw(ioaddr + 10); /* Total Rx and Tx octets. */ |
||
1968 | inw(ioaddr + 12); |
||
1969 | /* New: On the Vortex we must also clear the BadSSD counter. */ |
||
1970 | EL3WINDOW(4); |
||
1971 | inb(ioaddr + 12); |
||
1972 | |||
1973 | /* We change back to window 7 (not 1) with the Vortex. */ |
||
1974 | EL3WINDOW(7); |
||
1975 | return; |
||
1976 | } |
||
1977 | |||
1978 | static int vortex_ioctl(struct device *dev, struct ifreq *rq, int cmd) |
||
1979 | { |
||
1980 | struct vortex_private *vp = (struct vortex_private *)dev->priv; |
||
1981 | long ioaddr = dev->base_addr; |
||
1982 | u16 *data = (u16 *)&rq->ifr_data; |
||
1983 | int phy = vp->phys[0] & 0x1f; |
||
1984 | |||
1985 | switch(cmd) { |
||
1986 | case SIOCDEVPRIVATE: /* Get the address of the PHY in use. */ |
||
1987 | data[0] = phy; |
||
1988 | case SIOCDEVPRIVATE+1: /* Read the specified MII register. */ |
||
1989 | EL3WINDOW(4); |
||
1990 | data[3] = mdio_read(ioaddr, data[0] & 0x1f, data[1] & 0x1f); |
||
1991 | return 0; |
||
1992 | case SIOCDEVPRIVATE+2: /* Write the specified MII register */ |
||
1993 | if (!suser()) |
||
1994 | return -EPERM; |
||
1995 | EL3WINDOW(4); |
||
1996 | mdio_write(ioaddr, data[0] & 0x1f, data[1] & 0x1f, data[2]); |
||
1997 | return 0; |
||
1998 | default: |
||
1999 | return -EOPNOTSUPP; |
||
2000 | } |
||
2001 | } |
||
2002 | |||
2003 | /* Pre-Cyclone chips have no documented multicast filter, so the only |
||
2004 | multicast setting is to receive all multicast frames. At least |
||
2005 | the chip has a very clean way to set the mode, unlike many others. */ |
||
2006 | static void set_rx_mode(struct device *dev) |
||
2007 | { |
||
2008 | long ioaddr = dev->base_addr; |
||
2009 | int new_mode; |
||
2010 | |||
2011 | if (dev->flags & IFF_PROMISC) { |
||
2012 | if (vortex_debug > 0) |
||
2013 | printk(KERN_NOTICE "%s: Setting promiscuous mode.\n", dev->name); |
||
2014 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm; |
||
2015 | } else if ((dev->mc_list) || (dev->flags & IFF_ALLMULTI)) { |
||
2016 | new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast; |
||
2017 | } else |
||
2018 | new_mode = SetRxFilter | RxStation | RxBroadcast; |
||
2019 | |||
2020 | outw(new_mode, ioaddr + EL3_CMD); |
||
2021 | } |
||
2022 | |||
2023 | |||
2024 | /* MII transceiver control section. |
||
2025 | Read and write the MII registers using software-generated serial |
||
2026 | MDIO protocol. See the MII specifications or DP83840A data sheet |
||
2027 | for details. */ |
||
2028 | |||
2029 | /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually |
||
2030 | met by back-to-back PCI I/O cycles, but we insert a delay to avoid |
||
2031 | "overclocking" issues. */ |
||
2032 | #define mdio_delay() inl(mdio_addr) |
||
2033 | |||
2034 | #define MDIO_SHIFT_CLK 0x01 |
||
2035 | #define MDIO_DIR_WRITE 0x04 |
||
2036 | #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE) |
||
2037 | #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE) |
||
2038 | #define MDIO_DATA_READ 0x02 |
||
2039 | #define MDIO_ENB_IN 0x00 |
||
2040 | |||
2041 | /* Generate the preamble required for initial synchronization and |
||
2042 | a few older transceivers. */ |
||
2043 | static void mdio_sync(long ioaddr, int bits) |
||
2044 | { |
||
2045 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2046 | |||
2047 | /* Establish sync by sending at least 32 logic ones. */ |
||
2048 | while (-- bits >= 0) { |
||
2049 | outw(MDIO_DATA_WRITE1, mdio_addr); |
||
2050 | mdio_delay(); |
||
2051 | outw(MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr); |
||
2052 | mdio_delay(); |
||
2053 | } |
||
2054 | } |
||
2055 | |||
2056 | static int mdio_read(long ioaddr, int phy_id, int location) |
||
2057 | { |
||
2058 | int i; |
||
2059 | int read_cmd = (0xf6 << 10) | (phy_id << 5) | location; |
||
2060 | unsigned int retval = 0; |
||
2061 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2062 | |||
2063 | if (mii_preamble_required) |
||
2064 | mdio_sync(ioaddr, 32); |
||
2065 | |||
2066 | /* Shift the read command bits out. */ |
||
2067 | for (i = 14; i >= 0; i--) { |
||
2068 | int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
||
2069 | outw(dataval, mdio_addr); |
||
2070 | mdio_delay(); |
||
2071 | outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
||
2072 | mdio_delay(); |
||
2073 | } |
||
2074 | /* Read the two transition, 16 data, and wire-idle bits. */ |
||
2075 | for (i = 19; i > 0; i--) { |
||
2076 | outw(MDIO_ENB_IN, mdio_addr); |
||
2077 | mdio_delay(); |
||
2078 | retval = (retval << 1) | ((inw(mdio_addr) & MDIO_DATA_READ) ? 1 : 0); |
||
2079 | outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
||
2080 | mdio_delay(); |
||
2081 | } |
||
2082 | #if 0 |
||
2083 | return (retval>>1) & 0x1ffff; |
||
2084 | #else |
||
2085 | return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff; |
||
2086 | #endif |
||
2087 | } |
||
2088 | |||
2089 | static void mdio_write(long ioaddr, int phy_id, int location, int value) |
||
2090 | { |
||
2091 | int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value; |
||
2092 | long mdio_addr = ioaddr + Wn4_PhysicalMgmt; |
||
2093 | int i; |
||
2094 | |||
2095 | if (mii_preamble_required) |
||
2096 | mdio_sync(ioaddr, 32); |
||
2097 | |||
2098 | /* Shift the command bits out. */ |
||
2099 | for (i = 31; i >= 0; i--) { |
||
2100 | int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0; |
||
2101 | outw(dataval, mdio_addr); |
||
2102 | mdio_delay(); |
||
2103 | outw(dataval | MDIO_SHIFT_CLK, mdio_addr); |
||
2104 | mdio_delay(); |
||
2105 | } |
||
2106 | /* Leave the interface idle. */ |
||
2107 | for (i = 1; i >= 0; i--) { |
||
2108 | outw(MDIO_ENB_IN, mdio_addr); |
||
2109 | mdio_delay(); |
||
2110 | outw(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr); |
||
2111 | mdio_delay(); |
||
2112 | } |
||
2113 | |||
2114 | return; |
||
2115 | } |
||
2116 | |||
2117 | |||
2118 | #ifdef MODULE |
||
2119 | void cleanup_module(void) |
||
2120 | { |
||
2121 | struct device *next_dev; |
||
2122 | |||
2123 | #ifdef CARDBUS |
||
2124 | unregister_driver(&vortex_ops); |
||
2125 | #endif |
||
2126 | |||
2127 | /* No need to check MOD_IN_USE, as sys_delete_module() checks. */ |
||
2128 | while (root_vortex_dev) { |
||
2129 | struct vortex_private *vp=(void *)(root_vortex_dev->priv); |
||
2130 | next_dev = vp->next_module; |
||
2131 | unregister_netdev(root_vortex_dev); |
||
2132 | outw(TotalReset, root_vortex_dev->base_addr + EL3_CMD); |
||
2133 | release_region(root_vortex_dev->base_addr, |
||
2134 | pci_tbl[vp->chip_id].io_size); |
||
2135 | kfree(root_vortex_dev); |
||
2136 | kfree(vp->priv_addr); |
||
2137 | root_vortex_dev = next_dev; |
||
2138 | } |
||
2139 | } |
||
2140 | |||
2141 | #endif /* MODULE */ |
||
2142 | |||
2143 | /* |
||
2144 | * Local variables: |
||
2145 | * compile-command: "gcc -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c `[ -f /usr/include/linux/modversions.h ] && echo -DMODVERSIONS`" |
||
2146 | * SMP-compile-command: "gcc -D__SMP__ -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c" |
||
2147 | * cardbus-compile-command: "gcc -DCARDBUS -DMODULE -D__KERNEL__ -Wall -Wstrict-prototypes -O6 -c 3c59x.c -o 3c575_cb.o -I/usr/src/pcmcia-cs-3.0.5/include/" |
||
2148 | * c-indent-level: 4 |
||
2149 | * c-basic-offset: 4 |
||
2150 | * tab-width: 4 |
||
2151 | * End: |
||
2152 | */ |