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Rev | Author | Line No. | Line |
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428 | giacomo | 1 | /* |
2 | * probe.c - PCI detection and setup code |
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3 | */ |
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4 | |||
430 | giacomo | 5 | #include <linuxcomp.h> |
6 | |||
428 | giacomo | 7 | #include <linux/init.h> |
8 | #include <linux/pci.h> |
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9 | #include <linux/slab.h> |
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10 | #include <linux/module.h> |
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11 | |||
440 | giacomo | 12 | #define DEBUG |
428 | giacomo | 13 | |
14 | #ifdef DEBUG |
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15 | #define DBG(x...) printk(x) |
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16 | #else |
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17 | #define DBG(x...) |
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18 | #endif |
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19 | |||
20 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
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21 | #define CARDBUS_RESERVE_BUSNR 3 |
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22 | |||
23 | /* Ugh. Need to stop exporting this to modules. */ |
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24 | LIST_HEAD(pci_root_buses); |
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25 | EXPORT_SYMBOL(pci_root_buses); |
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26 | |||
27 | LIST_HEAD(pci_devices); |
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28 | |||
29 | /* |
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30 | * Translate the low bits of the PCI base |
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31 | * to the resource type |
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32 | */ |
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33 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
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34 | { |
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35 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
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36 | return IORESOURCE_IO; |
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37 | |||
38 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
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39 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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40 | |||
41 | return IORESOURCE_MEM; |
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42 | } |
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43 | |||
44 | /* |
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45 | * Find the extent of a PCI decode.. |
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46 | */ |
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47 | static u32 pci_size(u32 base, u32 maxbase, unsigned long mask) |
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48 | { |
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49 | u32 size = mask & maxbase; /* Find the significant bits */ |
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50 | if (!size) |
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51 | return 0; |
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52 | |||
53 | /* Get the lowest of them to find the decode size, and |
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54 | from that the extent. */ |
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55 | size = (size & ~(size-1)) - 1; |
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56 | |||
57 | /* base == maxbase can be valid only if the BAR has |
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58 | already been programmed with all 1s. */ |
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59 | if (base == maxbase && ((base | size) & mask) != mask) |
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60 | return 0; |
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61 | |||
62 | return size; |
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63 | } |
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64 | |||
65 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
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66 | { |
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67 | unsigned int pos, reg, next; |
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68 | u32 l, sz; |
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69 | struct resource *res; |
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70 | |||
71 | for(pos=0; pos<howmany; pos = next) { |
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72 | next = pos+1; |
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73 | res = &dev->resource[pos]; |
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74 | res->name = pci_name(dev); |
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75 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
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76 | pci_read_config_dword(dev, reg, &l); |
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77 | pci_write_config_dword(dev, reg, ~0); |
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78 | pci_read_config_dword(dev, reg, &sz); |
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79 | pci_write_config_dword(dev, reg, l); |
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80 | if (!sz || sz == 0xffffffff) |
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81 | continue; |
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82 | if (l == 0xffffffff) |
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83 | l = 0; |
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84 | if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) { |
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85 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK); |
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86 | if (!sz) |
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87 | continue; |
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88 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
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89 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
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90 | } else { |
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91 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
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92 | if (!sz) |
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93 | continue; |
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94 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
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95 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
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96 | } |
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97 | res->end = res->start + (unsigned long) sz; |
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98 | res->flags |= pci_calc_resource_flags(l); |
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99 | if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK)) |
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100 | == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) { |
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101 | pci_read_config_dword(dev, reg+4, &l); |
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102 | next++; |
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103 | #if BITS_PER_LONG == 64 |
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104 | res->start |= ((unsigned long) l) << 32; |
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105 | res->end = res->start + sz; |
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106 | pci_write_config_dword(dev, reg+4, ~0); |
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107 | pci_read_config_dword(dev, reg+4, &sz); |
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108 | pci_write_config_dword(dev, reg+4, l); |
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109 | if (~sz) |
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110 | res->end = res->start + 0xffffffff + |
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111 | (((unsigned long) ~sz) << 32); |
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112 | #else |
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113 | if (l) { |
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114 | printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev)); |
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115 | res->start = 0; |
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116 | res->flags = 0; |
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117 | continue; |
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118 | } |
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119 | #endif |
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120 | } |
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121 | } |
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122 | if (rom) { |
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123 | dev->rom_base_reg = rom; |
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124 | res = &dev->resource[PCI_ROM_RESOURCE]; |
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125 | res->name = pci_name(dev); |
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126 | pci_read_config_dword(dev, rom, &l); |
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127 | pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); |
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128 | pci_read_config_dword(dev, rom, &sz); |
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129 | pci_write_config_dword(dev, rom, l); |
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130 | if (l == 0xffffffff) |
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131 | l = 0; |
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132 | if (sz && sz != 0xffffffff) { |
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133 | sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK); |
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134 | if (sz) { |
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135 | res->flags = (l & PCI_ROM_ADDRESS_ENABLE) | |
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136 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
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137 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
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138 | res->start = l & PCI_ROM_ADDRESS_MASK; |
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139 | res->end = res->start + (unsigned long) sz; |
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140 | } |
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141 | } |
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142 | } |
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143 | } |
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144 | |||
145 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
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146 | { |
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147 | struct pci_dev *dev = child->self; |
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148 | u8 io_base_lo, io_limit_lo; |
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149 | u16 mem_base_lo, mem_limit_lo; |
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150 | unsigned long base, limit; |
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151 | struct resource *res; |
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152 | int i; |
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153 | |||
154 | if (!dev) /* It's a host bus, nothing to read */ |
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155 | return; |
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156 | |||
157 | if (dev->transparent) { |
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158 | printk("Transparent bridge - %s\n", pci_name(dev)); |
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159 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) |
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160 | child->resource[i] = child->parent->resource[i]; |
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161 | return; |
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162 | } |
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163 | |||
164 | for(i=0; i<3; i++) |
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165 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
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166 | |||
167 | res = child->resource[0]; |
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168 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
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169 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
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170 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; |
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171 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; |
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172 | |||
173 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { |
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174 | u16 io_base_hi, io_limit_hi; |
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175 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
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176 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); |
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177 | base |= (io_base_hi << 16); |
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178 | limit |= (io_limit_hi << 16); |
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179 | } |
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180 | |||
181 | if (base && base <= limit) { |
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182 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
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183 | res->start = base; |
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184 | res->end = limit + 0xfff; |
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185 | } |
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186 | |||
187 | res = child->resource[1]; |
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188 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); |
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189 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); |
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190 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
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191 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; |
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192 | if (base && base <= limit) { |
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193 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
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194 | res->start = base; |
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195 | res->end = limit + 0xfffff; |
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196 | } |
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197 | |||
198 | res = child->resource[2]; |
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199 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); |
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200 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); |
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201 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
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202 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; |
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203 | |||
204 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { |
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205 | u32 mem_base_hi, mem_limit_hi; |
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206 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
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207 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); |
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208 | #if BITS_PER_LONG == 64 |
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209 | base |= ((long) mem_base_hi) << 32; |
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210 | limit |= ((long) mem_limit_hi) << 32; |
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211 | #else |
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212 | if (mem_base_hi || mem_limit_hi) { |
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213 | printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name); |
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214 | return; |
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215 | } |
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216 | #endif |
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217 | } |
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218 | if (base && base <= limit) { |
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219 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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220 | res->start = base; |
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221 | res->end = limit + 0xfffff; |
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222 | } |
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223 | } |
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224 | |||
225 | static struct pci_bus * __devinit pci_alloc_bus(void) |
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226 | { |
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227 | struct pci_bus *b; |
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228 | |||
229 | b = kmalloc(sizeof(*b), GFP_KERNEL); |
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230 | if (b) { |
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231 | memset(b, 0, sizeof(*b)); |
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232 | INIT_LIST_HEAD(&b->node); |
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233 | INIT_LIST_HEAD(&b->children); |
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234 | INIT_LIST_HEAD(&b->devices); |
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235 | } |
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236 | return b; |
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237 | } |
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238 | |||
239 | static struct pci_bus * __devinit |
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240 | pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) |
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241 | { |
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242 | struct pci_bus *child; |
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243 | |||
244 | /* |
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245 | * Allocate a new bus, and inherit stuff from the parent.. |
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246 | */ |
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247 | child = pci_alloc_bus(); |
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248 | |||
249 | if (child) { |
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250 | int i; |
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251 | |||
252 | child->self = bridge; |
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253 | child->parent = parent; |
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254 | child->ops = parent->ops; |
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255 | child->sysdata = parent->sysdata; |
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256 | child->dev = &bridge->dev; |
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257 | |||
258 | /* |
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259 | * Set up the primary, secondary and subordinate |
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260 | * bus numbers. |
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261 | */ |
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262 | child->number = child->secondary = busnr; |
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263 | child->primary = parent->secondary; |
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264 | child->subordinate = 0xff; |
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265 | |||
266 | /* Set up default resource pointers and names.. */ |
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267 | for (i = 0; i < 4; i++) { |
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268 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
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269 | child->resource[i]->name = child->name; |
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270 | } |
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271 | |||
272 | bridge->subordinate = child; |
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273 | } |
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274 | |||
275 | return child; |
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276 | } |
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277 | |||
278 | struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
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279 | { |
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280 | struct pci_bus *child; |
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281 | |||
282 | child = pci_alloc_child_bus(parent, dev, busnr); |
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283 | if (child) |
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284 | list_add_tail(&child->node, &parent->children); |
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285 | return child; |
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286 | } |
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287 | |||
288 | static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus); |
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289 | |||
290 | /* |
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291 | * If it's a bridge, configure it and scan the bus behind it. |
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292 | * For CardBus bridges, we don't scan behind as the devices will |
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293 | * be handled by the bridge driver itself. |
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294 | * |
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295 | * We need to process bridges in two passes -- first we scan those |
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296 | * already configured by the BIOS and after we are done with all of |
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297 | * them, we proceed to assigning numbers to the remaining buses in |
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298 | * order to avoid overlaps between old and new bus numbers. |
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299 | */ |
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300 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass) |
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301 | { |
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302 | struct pci_bus *child; |
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303 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
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304 | u32 buses; |
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305 | |||
306 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
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307 | |||
308 | DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", |
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309 | pci_name(dev), buses & 0xffffff, pass); |
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310 | |||
311 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
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312 | unsigned int cmax; |
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313 | /* |
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314 | * Bus already configured by firmware, process it in the first |
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315 | * pass and just note the configuration. |
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316 | */ |
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317 | if (pass) |
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318 | return max; |
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319 | child = pci_alloc_child_bus(bus, dev, 0); |
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320 | child->primary = buses & 0xFF; |
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321 | child->secondary = (buses >> 8) & 0xFF; |
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322 | child->subordinate = (buses >> 16) & 0xFF; |
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323 | child->number = child->secondary; |
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324 | cmax = pci_scan_child_bus(child); |
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325 | if (cmax > max) max = cmax; |
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326 | } else { |
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327 | /* |
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328 | * We need to assign a number to this bus which we always |
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329 | * do in the second pass. |
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330 | */ |
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331 | if (!pass) |
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332 | return max; |
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333 | |||
334 | /* Clear errors */ |
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335 | pci_write_config_word(dev, PCI_STATUS, 0xffff); |
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336 | |||
337 | child = pci_alloc_child_bus(bus, dev, ++max); |
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338 | buses = (buses & 0xff000000) |
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339 | | ((unsigned int)(child->primary) << 0) |
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340 | | ((unsigned int)(child->secondary) << 8) |
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341 | | ((unsigned int)(child->subordinate) << 16); |
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342 | |||
343 | /* |
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344 | * yenta.c forces a secondary latency timer of 176. |
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345 | * Copy that behaviour here. |
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346 | */ |
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347 | if (is_cardbus) { |
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348 | buses &= ~0xff000000; |
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349 | buses |= CARDBUS_LATENCY_TIMER << 24; |
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350 | } |
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351 | |||
352 | /* |
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353 | * We need to blast all three values with a single write. |
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354 | */ |
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355 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
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356 | |||
357 | if (!is_cardbus) { |
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358 | /* Now we can scan all subordinate buses... */ |
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359 | max = pci_scan_child_bus(child); |
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360 | } else { |
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361 | /* |
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362 | * For CardBus bridges, we leave 4 bus numbers |
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363 | * as cards with a PCI-to-PCI bridge can be |
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364 | * inserted later. |
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365 | */ |
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366 | max += CARDBUS_RESERVE_BUSNR; |
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367 | } |
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368 | /* |
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369 | * Set the subordinate bus number to its real value. |
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370 | */ |
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371 | child->subordinate = max; |
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372 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
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373 | } |
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374 | |||
456 | giacomo | 375 | sprintf26(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number); |
428 | giacomo | 376 | |
377 | return max; |
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378 | } |
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379 | |||
380 | /* |
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381 | * Read interrupt line and base address registers. |
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382 | * The architecture-dependent code can tweak these, of course. |
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383 | */ |
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384 | static void pci_read_irq(struct pci_dev *dev) |
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385 | { |
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386 | unsigned char irq; |
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387 | |||
388 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
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389 | if (irq) |
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390 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
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391 | dev->irq = irq; |
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392 | } |
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393 | |||
394 | /** |
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395 | * pci_setup_device - fill in class and map information of a device |
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396 | * @dev: the device structure to fill |
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397 | * |
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398 | * Initialize the device structure with information about the device's |
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399 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
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400 | * Called at initialisation of the PCI subsystem and by CardBus services. |
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401 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge |
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402 | * or CardBus). |
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403 | */ |
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404 | static int pci_setup_device(struct pci_dev * dev) |
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405 | { |
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406 | u32 class; |
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407 | |||
408 | dev->slot_name = dev->dev.bus_id; |
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409 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
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410 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); |
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411 | |||
412 | INIT_LIST_HEAD(&dev->pools); |
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413 | |||
414 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); |
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415 | class >>= 8; /* upper 3 bytes */ |
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416 | dev->class = class; |
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417 | class >>= 8; |
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418 | |||
419 | DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, |
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420 | dev->devfn, dev->vendor, dev->device, class, dev->hdr_type); |
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421 | |||
422 | /* "Unknown power state" */ |
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423 | dev->current_state = 4; |
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424 | |||
425 | switch (dev->hdr_type) { /* header type */ |
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426 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
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427 | if (class == PCI_CLASS_BRIDGE_PCI) |
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428 | goto bad; |
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429 | pci_read_irq(dev); |
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430 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
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431 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
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432 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); |
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433 | break; |
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434 | |||
435 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
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436 | if (class != PCI_CLASS_BRIDGE_PCI) |
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437 | goto bad; |
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438 | /* The PCI-to-PCI bridge spec requires that subtractive |
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439 | decoding (i.e. transparent) bridge must have programming |
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440 | interface code of 0x01. */ |
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441 | dev->transparent = ((dev->class & 0xff) == 1); |
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442 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
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443 | break; |
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444 | |||
445 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
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446 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
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447 | goto bad; |
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448 | pci_read_irq(dev); |
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449 | pci_read_bases(dev, 1, 0); |
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450 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
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451 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); |
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452 | break; |
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453 | |||
454 | default: /* unknown header */ |
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455 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
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456 | pci_name(dev), dev->hdr_type); |
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457 | return -1; |
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458 | |||
459 | bad: |
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460 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
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461 | pci_name(dev), class, dev->hdr_type); |
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462 | dev->class = PCI_CLASS_NOT_DEFINED; |
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463 | } |
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464 | |||
465 | /* We found a fine healthy device, go go go... */ |
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466 | return 0; |
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467 | } |
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468 | |||
469 | /** |
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470 | * pci_release_dev - free a pci device structure when all users of it are finished. |
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471 | * @dev: device that's been disconnected |
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472 | * |
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473 | * Will be called only by the device core when all users of this pci device are |
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474 | * done. |
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475 | */ |
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476 | static void pci_release_dev(struct device *dev) |
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477 | { |
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478 | struct pci_dev *pci_dev; |
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479 | |||
480 | pci_dev = to_pci_dev(dev); |
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481 | kfree(pci_dev); |
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482 | } |
||
483 | |||
484 | /* |
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485 | * Read the config data for a PCI device, sanity-check it |
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486 | * and fill in the dev structure... |
||
487 | */ |
||
488 | static struct pci_dev * __devinit |
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489 | pci_scan_device(struct pci_bus *bus, int devfn) |
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490 | { |
||
491 | struct pci_dev *dev; |
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492 | u32 l; |
||
493 | u8 hdr_type; |
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494 | |||
495 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) |
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496 | return NULL; |
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497 | |||
498 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
||
499 | return NULL; |
||
500 | |||
501 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
||
502 | if (l == 0xffffffff || l == 0x00000000 || |
||
503 | l == 0x0000ffff || l == 0xffff0000) |
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504 | return NULL; |
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505 | |||
506 | dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); |
||
507 | if (!dev) |
||
508 | return NULL; |
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509 | |||
510 | memset(dev, 0, sizeof(struct pci_dev)); |
||
511 | dev->bus = bus; |
||
512 | dev->sysdata = bus->sysdata; |
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513 | dev->dev.parent = bus->dev; |
||
514 | dev->dev.bus = &pci_bus_type; |
||
515 | dev->devfn = devfn; |
||
516 | dev->hdr_type = hdr_type & 0x7f; |
||
517 | dev->multifunction = !!(hdr_type & 0x80); |
||
518 | dev->vendor = l & 0xffff; |
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519 | dev->device = (l >> 16) & 0xffff; |
||
520 | |||
521 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
||
522 | set this higher, assuming the system even supports it. */ |
||
523 | dev->dma_mask = 0xffffffff; |
||
524 | dev->consistent_dma_mask = 0xffffffff; |
||
525 | if (pci_setup_device(dev) < 0) { |
||
526 | kfree(dev); |
||
527 | return NULL; |
||
528 | } |
||
529 | device_initialize(&dev->dev); |
||
530 | dev->dev.release = pci_release_dev; |
||
531 | pci_dev_get(dev); |
||
532 | |||
533 | pci_name_device(dev); |
||
534 | |||
535 | dev->dev.dma_mask = &dev->dma_mask; |
||
536 | |||
537 | return dev; |
||
538 | } |
||
539 | |||
540 | /** |
||
541 | * pci_scan_slot - scan a PCI slot on a bus for devices. |
||
542 | * @bus: PCI bus to scan |
||
543 | * @devfn: slot number to scan (must have zero function.) |
||
544 | * |
||
545 | * Scan a PCI slot on the specified PCI bus for devices, adding |
||
546 | * discovered devices to the @bus->devices list. New devices |
||
547 | * will have an empty dev->global_list head. |
||
548 | */ |
||
549 | int __devinit pci_scan_slot(struct pci_bus *bus, int devfn) |
||
550 | { |
||
551 | int func, nr = 0; |
||
552 | |||
553 | for (func = 0; func < 8; func++, devfn++) { |
||
554 | struct pci_dev *dev; |
||
555 | |||
556 | dev = pci_scan_device(bus, devfn); |
||
557 | if (func == 0) { |
||
558 | if (!dev) |
||
559 | break; |
||
560 | } else { |
||
561 | if (!dev) |
||
562 | continue; |
||
563 | dev->multifunction = 1; |
||
564 | } |
||
565 | |||
566 | /* Fix up broken headers */ |
||
567 | pci_fixup_device(PCI_FIXUP_HEADER, dev); |
||
568 | |||
569 | /* |
||
570 | * Add the device to our list of discovered devices |
||
571 | * and the bus list for fixup functions, etc. |
||
572 | */ |
||
573 | INIT_LIST_HEAD(&dev->global_list); |
||
574 | list_add_tail(&dev->bus_list, &bus->devices); |
||
575 | nr++; |
||
576 | |||
577 | /* |
||
578 | * If this is a single function device, |
||
579 | * don't scan past the first function. |
||
580 | */ |
||
581 | if (!dev->multifunction) |
||
582 | break; |
||
583 | } |
||
584 | return nr; |
||
585 | } |
||
586 | |||
587 | static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
||
588 | { |
||
589 | unsigned int devfn, pass, max = bus->secondary; |
||
590 | struct pci_dev *dev; |
||
591 | |||
592 | DBG("Scanning bus %02x\n", bus->number); |
||
593 | |||
594 | /* Go find them, Rover! */ |
||
595 | for (devfn = 0; devfn < 0x100; devfn += 8) |
||
596 | pci_scan_slot(bus, devfn); |
||
597 | |||
598 | /* |
||
599 | * After performing arch-dependent fixup of the bus, look behind |
||
600 | * all PCI-to-PCI bridges on this bus. |
||
601 | */ |
||
602 | DBG("Fixups for bus %02x\n", bus->number); |
||
603 | pcibios_fixup_bus(bus); |
||
604 | for (pass=0; pass < 2; pass++) |
||
605 | list_for_each_entry(dev, &bus->devices, bus_list) { |
||
606 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
||
607 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) |
||
608 | max = pci_scan_bridge(bus, dev, max, pass); |
||
609 | } |
||
610 | |||
611 | /* |
||
612 | * We've scanned the bus and so we know all about what's on |
||
613 | * the other side of any bridges that may be on this bus plus |
||
614 | * any devices. |
||
615 | * |
||
616 | * Return how far we've got finding sub-buses. |
||
617 | */ |
||
618 | DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max); |
||
619 | return max; |
||
620 | } |
||
621 | |||
622 | unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus) |
||
623 | { |
||
624 | unsigned int max; |
||
625 | |||
626 | max = pci_scan_child_bus(bus); |
||
627 | |||
628 | /* |
||
629 | * Make the discovered devices available. |
||
630 | */ |
||
631 | pci_bus_add_devices(bus); |
||
632 | |||
633 | return max; |
||
634 | } |
||
635 | |||
636 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata) |
||
637 | { |
||
638 | struct pci_bus *b; |
||
639 | |||
640 | b = pci_alloc_bus(); |
||
641 | if (!b) |
||
642 | return NULL; |
||
643 | |||
644 | b->dev = kmalloc(sizeof(*(b->dev)),GFP_KERNEL); |
||
645 | if (!b->dev){ |
||
646 | kfree(b); |
||
647 | return NULL; |
||
648 | } |
||
649 | |||
650 | b->sysdata = sysdata; |
||
651 | b->ops = ops; |
||
652 | |||
653 | if (pci_find_bus(pci_domain_nr(b), bus)) { |
||
654 | /* If we already got to this bus through a different bridge, ignore it */ |
||
655 | DBG("PCI: Bus %02x already known\n", bus); |
||
656 | kfree(b->dev); |
||
657 | kfree(b); |
||
658 | return NULL; |
||
659 | } |
||
660 | |||
661 | list_add_tail(&b->node, &pci_root_buses); |
||
662 | |||
663 | memset(b->dev,0,sizeof(*(b->dev))); |
||
664 | b->dev->parent = parent; |
||
665 | sprintf(b->dev->bus_id,"pci%04x:%02x", pci_domain_nr(b), bus); |
||
666 | device_register(b->dev); |
||
667 | |||
668 | b->number = b->secondary = bus; |
||
669 | b->resource[0] = &ioport_resource; |
||
670 | b->resource[1] = &iomem_resource; |
||
671 | |||
672 | b->subordinate = pci_scan_child_bus(b); |
||
673 | |||
674 | pci_bus_add_devices(b); |
||
675 | |||
676 | return b; |
||
677 | } |
||
678 | EXPORT_SYMBOL(pci_scan_bus_parented); |
||
679 | |||
680 | #ifdef CONFIG_HOTPLUG |
||
681 | EXPORT_SYMBOL(pci_add_new_bus); |
||
682 | EXPORT_SYMBOL(pci_do_scan_bus); |
||
683 | EXPORT_SYMBOL(pci_scan_slot); |
||
684 | EXPORT_SYMBOL(pci_scan_bridge); |
||
685 | #endif |