Rev 430 | Go to most recent revision | Details | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
428 | giacomo | 1 | /* |
2 | * probe.c - PCI detection and setup code |
||
3 | */ |
||
4 | |||
5 | #include <linux/init.h> |
||
6 | #include <linux/pci.h> |
||
7 | #include <linux/slab.h> |
||
8 | #include <linux/module.h> |
||
9 | |||
10 | #undef DEBUG |
||
11 | |||
12 | #ifdef DEBUG |
||
13 | #define DBG(x...) printk(x) |
||
14 | #else |
||
15 | #define DBG(x...) |
||
16 | #endif |
||
17 | |||
18 | #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */ |
||
19 | #define CARDBUS_RESERVE_BUSNR 3 |
||
20 | |||
21 | /* Ugh. Need to stop exporting this to modules. */ |
||
22 | LIST_HEAD(pci_root_buses); |
||
23 | EXPORT_SYMBOL(pci_root_buses); |
||
24 | |||
25 | LIST_HEAD(pci_devices); |
||
26 | |||
27 | /* |
||
28 | * Translate the low bits of the PCI base |
||
29 | * to the resource type |
||
30 | */ |
||
31 | static inline unsigned int pci_calc_resource_flags(unsigned int flags) |
||
32 | { |
||
33 | if (flags & PCI_BASE_ADDRESS_SPACE_IO) |
||
34 | return IORESOURCE_IO; |
||
35 | |||
36 | if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH) |
||
37 | return IORESOURCE_MEM | IORESOURCE_PREFETCH; |
||
38 | |||
39 | return IORESOURCE_MEM; |
||
40 | } |
||
41 | |||
42 | /* |
||
43 | * Find the extent of a PCI decode.. |
||
44 | */ |
||
45 | static u32 pci_size(u32 base, u32 maxbase, unsigned long mask) |
||
46 | { |
||
47 | u32 size = mask & maxbase; /* Find the significant bits */ |
||
48 | if (!size) |
||
49 | return 0; |
||
50 | |||
51 | /* Get the lowest of them to find the decode size, and |
||
52 | from that the extent. */ |
||
53 | size = (size & ~(size-1)) - 1; |
||
54 | |||
55 | /* base == maxbase can be valid only if the BAR has |
||
56 | already been programmed with all 1s. */ |
||
57 | if (base == maxbase && ((base | size) & mask) != mask) |
||
58 | return 0; |
||
59 | |||
60 | return size; |
||
61 | } |
||
62 | |||
63 | static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom) |
||
64 | { |
||
65 | unsigned int pos, reg, next; |
||
66 | u32 l, sz; |
||
67 | struct resource *res; |
||
68 | |||
69 | for(pos=0; pos<howmany; pos = next) { |
||
70 | next = pos+1; |
||
71 | res = &dev->resource[pos]; |
||
72 | res->name = pci_name(dev); |
||
73 | reg = PCI_BASE_ADDRESS_0 + (pos << 2); |
||
74 | pci_read_config_dword(dev, reg, &l); |
||
75 | pci_write_config_dword(dev, reg, ~0); |
||
76 | pci_read_config_dword(dev, reg, &sz); |
||
77 | pci_write_config_dword(dev, reg, l); |
||
78 | if (!sz || sz == 0xffffffff) |
||
79 | continue; |
||
80 | if (l == 0xffffffff) |
||
81 | l = 0; |
||
82 | if ((l & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_MEMORY) { |
||
83 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_MEM_MASK); |
||
84 | if (!sz) |
||
85 | continue; |
||
86 | res->start = l & PCI_BASE_ADDRESS_MEM_MASK; |
||
87 | res->flags |= l & ~PCI_BASE_ADDRESS_MEM_MASK; |
||
88 | } else { |
||
89 | sz = pci_size(l, sz, PCI_BASE_ADDRESS_IO_MASK & 0xffff); |
||
90 | if (!sz) |
||
91 | continue; |
||
92 | res->start = l & PCI_BASE_ADDRESS_IO_MASK; |
||
93 | res->flags |= l & ~PCI_BASE_ADDRESS_IO_MASK; |
||
94 | } |
||
95 | res->end = res->start + (unsigned long) sz; |
||
96 | res->flags |= pci_calc_resource_flags(l); |
||
97 | if ((l & (PCI_BASE_ADDRESS_SPACE | PCI_BASE_ADDRESS_MEM_TYPE_MASK)) |
||
98 | == (PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64)) { |
||
99 | pci_read_config_dword(dev, reg+4, &l); |
||
100 | next++; |
||
101 | #if BITS_PER_LONG == 64 |
||
102 | res->start |= ((unsigned long) l) << 32; |
||
103 | res->end = res->start + sz; |
||
104 | pci_write_config_dword(dev, reg+4, ~0); |
||
105 | pci_read_config_dword(dev, reg+4, &sz); |
||
106 | pci_write_config_dword(dev, reg+4, l); |
||
107 | if (~sz) |
||
108 | res->end = res->start + 0xffffffff + |
||
109 | (((unsigned long) ~sz) << 32); |
||
110 | #else |
||
111 | if (l) { |
||
112 | printk(KERN_ERR "PCI: Unable to handle 64-bit address for device %s\n", pci_name(dev)); |
||
113 | res->start = 0; |
||
114 | res->flags = 0; |
||
115 | continue; |
||
116 | } |
||
117 | #endif |
||
118 | } |
||
119 | } |
||
120 | if (rom) { |
||
121 | dev->rom_base_reg = rom; |
||
122 | res = &dev->resource[PCI_ROM_RESOURCE]; |
||
123 | res->name = pci_name(dev); |
||
124 | pci_read_config_dword(dev, rom, &l); |
||
125 | pci_write_config_dword(dev, rom, ~PCI_ROM_ADDRESS_ENABLE); |
||
126 | pci_read_config_dword(dev, rom, &sz); |
||
127 | pci_write_config_dword(dev, rom, l); |
||
128 | if (l == 0xffffffff) |
||
129 | l = 0; |
||
130 | if (sz && sz != 0xffffffff) { |
||
131 | sz = pci_size(l, sz, PCI_ROM_ADDRESS_MASK); |
||
132 | if (sz) { |
||
133 | res->flags = (l & PCI_ROM_ADDRESS_ENABLE) | |
||
134 | IORESOURCE_MEM | IORESOURCE_PREFETCH | |
||
135 | IORESOURCE_READONLY | IORESOURCE_CACHEABLE; |
||
136 | res->start = l & PCI_ROM_ADDRESS_MASK; |
||
137 | res->end = res->start + (unsigned long) sz; |
||
138 | } |
||
139 | } |
||
140 | } |
||
141 | } |
||
142 | |||
143 | void __devinit pci_read_bridge_bases(struct pci_bus *child) |
||
144 | { |
||
145 | struct pci_dev *dev = child->self; |
||
146 | u8 io_base_lo, io_limit_lo; |
||
147 | u16 mem_base_lo, mem_limit_lo; |
||
148 | unsigned long base, limit; |
||
149 | struct resource *res; |
||
150 | int i; |
||
151 | |||
152 | if (!dev) /* It's a host bus, nothing to read */ |
||
153 | return; |
||
154 | |||
155 | if (dev->transparent) { |
||
156 | printk("Transparent bridge - %s\n", pci_name(dev)); |
||
157 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) |
||
158 | child->resource[i] = child->parent->resource[i]; |
||
159 | return; |
||
160 | } |
||
161 | |||
162 | for(i=0; i<3; i++) |
||
163 | child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i]; |
||
164 | |||
165 | res = child->resource[0]; |
||
166 | pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo); |
||
167 | pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo); |
||
168 | base = (io_base_lo & PCI_IO_RANGE_MASK) << 8; |
||
169 | limit = (io_limit_lo & PCI_IO_RANGE_MASK) << 8; |
||
170 | |||
171 | if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) { |
||
172 | u16 io_base_hi, io_limit_hi; |
||
173 | pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi); |
||
174 | pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi); |
||
175 | base |= (io_base_hi << 16); |
||
176 | limit |= (io_limit_hi << 16); |
||
177 | } |
||
178 | |||
179 | if (base && base <= limit) { |
||
180 | res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO; |
||
181 | res->start = base; |
||
182 | res->end = limit + 0xfff; |
||
183 | } |
||
184 | |||
185 | res = child->resource[1]; |
||
186 | pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo); |
||
187 | pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo); |
||
188 | base = (mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16; |
||
189 | limit = (mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16; |
||
190 | if (base && base <= limit) { |
||
191 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM; |
||
192 | res->start = base; |
||
193 | res->end = limit + 0xfffff; |
||
194 | } |
||
195 | |||
196 | res = child->resource[2]; |
||
197 | pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo); |
||
198 | pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo); |
||
199 | base = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16; |
||
200 | limit = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16; |
||
201 | |||
202 | if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) { |
||
203 | u32 mem_base_hi, mem_limit_hi; |
||
204 | pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi); |
||
205 | pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi); |
||
206 | #if BITS_PER_LONG == 64 |
||
207 | base |= ((long) mem_base_hi) << 32; |
||
208 | limit |= ((long) mem_limit_hi) << 32; |
||
209 | #else |
||
210 | if (mem_base_hi || mem_limit_hi) { |
||
211 | printk(KERN_ERR "PCI: Unable to handle 64-bit address space for %s\n", child->name); |
||
212 | return; |
||
213 | } |
||
214 | #endif |
||
215 | } |
||
216 | if (base && base <= limit) { |
||
217 | res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM | IORESOURCE_PREFETCH; |
||
218 | res->start = base; |
||
219 | res->end = limit + 0xfffff; |
||
220 | } |
||
221 | } |
||
222 | |||
223 | static struct pci_bus * __devinit pci_alloc_bus(void) |
||
224 | { |
||
225 | struct pci_bus *b; |
||
226 | |||
227 | b = kmalloc(sizeof(*b), GFP_KERNEL); |
||
228 | if (b) { |
||
229 | memset(b, 0, sizeof(*b)); |
||
230 | INIT_LIST_HEAD(&b->node); |
||
231 | INIT_LIST_HEAD(&b->children); |
||
232 | INIT_LIST_HEAD(&b->devices); |
||
233 | } |
||
234 | return b; |
||
235 | } |
||
236 | |||
237 | static struct pci_bus * __devinit |
||
238 | pci_alloc_child_bus(struct pci_bus *parent, struct pci_dev *bridge, int busnr) |
||
239 | { |
||
240 | struct pci_bus *child; |
||
241 | |||
242 | /* |
||
243 | * Allocate a new bus, and inherit stuff from the parent.. |
||
244 | */ |
||
245 | child = pci_alloc_bus(); |
||
246 | |||
247 | if (child) { |
||
248 | int i; |
||
249 | |||
250 | child->self = bridge; |
||
251 | child->parent = parent; |
||
252 | child->ops = parent->ops; |
||
253 | child->sysdata = parent->sysdata; |
||
254 | child->dev = &bridge->dev; |
||
255 | |||
256 | /* |
||
257 | * Set up the primary, secondary and subordinate |
||
258 | * bus numbers. |
||
259 | */ |
||
260 | child->number = child->secondary = busnr; |
||
261 | child->primary = parent->secondary; |
||
262 | child->subordinate = 0xff; |
||
263 | |||
264 | /* Set up default resource pointers and names.. */ |
||
265 | for (i = 0; i < 4; i++) { |
||
266 | child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i]; |
||
267 | child->resource[i]->name = child->name; |
||
268 | } |
||
269 | |||
270 | bridge->subordinate = child; |
||
271 | } |
||
272 | |||
273 | return child; |
||
274 | } |
||
275 | |||
276 | struct pci_bus * __devinit pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr) |
||
277 | { |
||
278 | struct pci_bus *child; |
||
279 | |||
280 | child = pci_alloc_child_bus(parent, dev, busnr); |
||
281 | if (child) |
||
282 | list_add_tail(&child->node, &parent->children); |
||
283 | return child; |
||
284 | } |
||
285 | |||
286 | static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus); |
||
287 | |||
288 | /* |
||
289 | * If it's a bridge, configure it and scan the bus behind it. |
||
290 | * For CardBus bridges, we don't scan behind as the devices will |
||
291 | * be handled by the bridge driver itself. |
||
292 | * |
||
293 | * We need to process bridges in two passes -- first we scan those |
||
294 | * already configured by the BIOS and after we are done with all of |
||
295 | * them, we proceed to assigning numbers to the remaining buses in |
||
296 | * order to avoid overlaps between old and new bus numbers. |
||
297 | */ |
||
298 | int __devinit pci_scan_bridge(struct pci_bus *bus, struct pci_dev * dev, int max, int pass) |
||
299 | { |
||
300 | struct pci_bus *child; |
||
301 | int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS); |
||
302 | u32 buses; |
||
303 | |||
304 | pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses); |
||
305 | |||
306 | DBG("Scanning behind PCI bridge %s, config %06x, pass %d\n", |
||
307 | pci_name(dev), buses & 0xffffff, pass); |
||
308 | |||
309 | if ((buses & 0xffff00) && !pcibios_assign_all_busses() && !is_cardbus) { |
||
310 | unsigned int cmax; |
||
311 | /* |
||
312 | * Bus already configured by firmware, process it in the first |
||
313 | * pass and just note the configuration. |
||
314 | */ |
||
315 | if (pass) |
||
316 | return max; |
||
317 | child = pci_alloc_child_bus(bus, dev, 0); |
||
318 | child->primary = buses & 0xFF; |
||
319 | child->secondary = (buses >> 8) & 0xFF; |
||
320 | child->subordinate = (buses >> 16) & 0xFF; |
||
321 | child->number = child->secondary; |
||
322 | cmax = pci_scan_child_bus(child); |
||
323 | if (cmax > max) max = cmax; |
||
324 | } else { |
||
325 | /* |
||
326 | * We need to assign a number to this bus which we always |
||
327 | * do in the second pass. |
||
328 | */ |
||
329 | if (!pass) |
||
330 | return max; |
||
331 | |||
332 | /* Clear errors */ |
||
333 | pci_write_config_word(dev, PCI_STATUS, 0xffff); |
||
334 | |||
335 | child = pci_alloc_child_bus(bus, dev, ++max); |
||
336 | buses = (buses & 0xff000000) |
||
337 | | ((unsigned int)(child->primary) << 0) |
||
338 | | ((unsigned int)(child->secondary) << 8) |
||
339 | | ((unsigned int)(child->subordinate) << 16); |
||
340 | |||
341 | /* |
||
342 | * yenta.c forces a secondary latency timer of 176. |
||
343 | * Copy that behaviour here. |
||
344 | */ |
||
345 | if (is_cardbus) { |
||
346 | buses &= ~0xff000000; |
||
347 | buses |= CARDBUS_LATENCY_TIMER << 24; |
||
348 | } |
||
349 | |||
350 | /* |
||
351 | * We need to blast all three values with a single write. |
||
352 | */ |
||
353 | pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses); |
||
354 | |||
355 | if (!is_cardbus) { |
||
356 | /* Now we can scan all subordinate buses... */ |
||
357 | max = pci_scan_child_bus(child); |
||
358 | } else { |
||
359 | /* |
||
360 | * For CardBus bridges, we leave 4 bus numbers |
||
361 | * as cards with a PCI-to-PCI bridge can be |
||
362 | * inserted later. |
||
363 | */ |
||
364 | max += CARDBUS_RESERVE_BUSNR; |
||
365 | } |
||
366 | /* |
||
367 | * Set the subordinate bus number to its real value. |
||
368 | */ |
||
369 | child->subordinate = max; |
||
370 | pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max); |
||
371 | } |
||
372 | |||
373 | sprintf(child->name, (is_cardbus ? "PCI CardBus #%02x" : "PCI Bus #%02x"), child->number); |
||
374 | |||
375 | return max; |
||
376 | } |
||
377 | |||
378 | /* |
||
379 | * Read interrupt line and base address registers. |
||
380 | * The architecture-dependent code can tweak these, of course. |
||
381 | */ |
||
382 | static void pci_read_irq(struct pci_dev *dev) |
||
383 | { |
||
384 | unsigned char irq; |
||
385 | |||
386 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq); |
||
387 | if (irq) |
||
388 | pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); |
||
389 | dev->irq = irq; |
||
390 | } |
||
391 | |||
392 | /** |
||
393 | * pci_setup_device - fill in class and map information of a device |
||
394 | * @dev: the device structure to fill |
||
395 | * |
||
396 | * Initialize the device structure with information about the device's |
||
397 | * vendor,class,memory and IO-space addresses,IRQ lines etc. |
||
398 | * Called at initialisation of the PCI subsystem and by CardBus services. |
||
399 | * Returns 0 on success and -1 if unknown type of device (not normal, bridge |
||
400 | * or CardBus). |
||
401 | */ |
||
402 | static int pci_setup_device(struct pci_dev * dev) |
||
403 | { |
||
404 | u32 class; |
||
405 | |||
406 | dev->slot_name = dev->dev.bus_id; |
||
407 | sprintf(pci_name(dev), "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus), |
||
408 | dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn)); |
||
409 | |||
410 | INIT_LIST_HEAD(&dev->pools); |
||
411 | |||
412 | pci_read_config_dword(dev, PCI_CLASS_REVISION, &class); |
||
413 | class >>= 8; /* upper 3 bytes */ |
||
414 | dev->class = class; |
||
415 | class >>= 8; |
||
416 | |||
417 | DBG("Found %02x:%02x [%04x/%04x] %06x %02x\n", dev->bus->number, |
||
418 | dev->devfn, dev->vendor, dev->device, class, dev->hdr_type); |
||
419 | |||
420 | /* "Unknown power state" */ |
||
421 | dev->current_state = 4; |
||
422 | |||
423 | switch (dev->hdr_type) { /* header type */ |
||
424 | case PCI_HEADER_TYPE_NORMAL: /* standard header */ |
||
425 | if (class == PCI_CLASS_BRIDGE_PCI) |
||
426 | goto bad; |
||
427 | pci_read_irq(dev); |
||
428 | pci_read_bases(dev, 6, PCI_ROM_ADDRESS); |
||
429 | pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
||
430 | pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device); |
||
431 | break; |
||
432 | |||
433 | case PCI_HEADER_TYPE_BRIDGE: /* bridge header */ |
||
434 | if (class != PCI_CLASS_BRIDGE_PCI) |
||
435 | goto bad; |
||
436 | /* The PCI-to-PCI bridge spec requires that subtractive |
||
437 | decoding (i.e. transparent) bridge must have programming |
||
438 | interface code of 0x01. */ |
||
439 | dev->transparent = ((dev->class & 0xff) == 1); |
||
440 | pci_read_bases(dev, 2, PCI_ROM_ADDRESS1); |
||
441 | break; |
||
442 | |||
443 | case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */ |
||
444 | if (class != PCI_CLASS_BRIDGE_CARDBUS) |
||
445 | goto bad; |
||
446 | pci_read_irq(dev); |
||
447 | pci_read_bases(dev, 1, 0); |
||
448 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor); |
||
449 | pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device); |
||
450 | break; |
||
451 | |||
452 | default: /* unknown header */ |
||
453 | printk(KERN_ERR "PCI: device %s has unknown header type %02x, ignoring.\n", |
||
454 | pci_name(dev), dev->hdr_type); |
||
455 | return -1; |
||
456 | |||
457 | bad: |
||
458 | printk(KERN_ERR "PCI: %s: class %x doesn't match header type %02x. Ignoring class.\n", |
||
459 | pci_name(dev), class, dev->hdr_type); |
||
460 | dev->class = PCI_CLASS_NOT_DEFINED; |
||
461 | } |
||
462 | |||
463 | /* We found a fine healthy device, go go go... */ |
||
464 | return 0; |
||
465 | } |
||
466 | |||
467 | /** |
||
468 | * pci_release_dev - free a pci device structure when all users of it are finished. |
||
469 | * @dev: device that's been disconnected |
||
470 | * |
||
471 | * Will be called only by the device core when all users of this pci device are |
||
472 | * done. |
||
473 | */ |
||
474 | static void pci_release_dev(struct device *dev) |
||
475 | { |
||
476 | struct pci_dev *pci_dev; |
||
477 | |||
478 | pci_dev = to_pci_dev(dev); |
||
479 | kfree(pci_dev); |
||
480 | } |
||
481 | |||
482 | /* |
||
483 | * Read the config data for a PCI device, sanity-check it |
||
484 | * and fill in the dev structure... |
||
485 | */ |
||
486 | static struct pci_dev * __devinit |
||
487 | pci_scan_device(struct pci_bus *bus, int devfn) |
||
488 | { |
||
489 | struct pci_dev *dev; |
||
490 | u32 l; |
||
491 | u8 hdr_type; |
||
492 | |||
493 | if (pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type)) |
||
494 | return NULL; |
||
495 | |||
496 | if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, &l)) |
||
497 | return NULL; |
||
498 | |||
499 | /* some broken boards return 0 or ~0 if a slot is empty: */ |
||
500 | if (l == 0xffffffff || l == 0x00000000 || |
||
501 | l == 0x0000ffff || l == 0xffff0000) |
||
502 | return NULL; |
||
503 | |||
504 | dev = kmalloc(sizeof(struct pci_dev), GFP_KERNEL); |
||
505 | if (!dev) |
||
506 | return NULL; |
||
507 | |||
508 | memset(dev, 0, sizeof(struct pci_dev)); |
||
509 | dev->bus = bus; |
||
510 | dev->sysdata = bus->sysdata; |
||
511 | dev->dev.parent = bus->dev; |
||
512 | dev->dev.bus = &pci_bus_type; |
||
513 | dev->devfn = devfn; |
||
514 | dev->hdr_type = hdr_type & 0x7f; |
||
515 | dev->multifunction = !!(hdr_type & 0x80); |
||
516 | dev->vendor = l & 0xffff; |
||
517 | dev->device = (l >> 16) & 0xffff; |
||
518 | |||
519 | /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer) |
||
520 | set this higher, assuming the system even supports it. */ |
||
521 | dev->dma_mask = 0xffffffff; |
||
522 | dev->consistent_dma_mask = 0xffffffff; |
||
523 | if (pci_setup_device(dev) < 0) { |
||
524 | kfree(dev); |
||
525 | return NULL; |
||
526 | } |
||
527 | device_initialize(&dev->dev); |
||
528 | dev->dev.release = pci_release_dev; |
||
529 | pci_dev_get(dev); |
||
530 | |||
531 | pci_name_device(dev); |
||
532 | |||
533 | dev->dev.dma_mask = &dev->dma_mask; |
||
534 | |||
535 | return dev; |
||
536 | } |
||
537 | |||
538 | /** |
||
539 | * pci_scan_slot - scan a PCI slot on a bus for devices. |
||
540 | * @bus: PCI bus to scan |
||
541 | * @devfn: slot number to scan (must have zero function.) |
||
542 | * |
||
543 | * Scan a PCI slot on the specified PCI bus for devices, adding |
||
544 | * discovered devices to the @bus->devices list. New devices |
||
545 | * will have an empty dev->global_list head. |
||
546 | */ |
||
547 | int __devinit pci_scan_slot(struct pci_bus *bus, int devfn) |
||
548 | { |
||
549 | int func, nr = 0; |
||
550 | |||
551 | for (func = 0; func < 8; func++, devfn++) { |
||
552 | struct pci_dev *dev; |
||
553 | |||
554 | dev = pci_scan_device(bus, devfn); |
||
555 | if (func == 0) { |
||
556 | if (!dev) |
||
557 | break; |
||
558 | } else { |
||
559 | if (!dev) |
||
560 | continue; |
||
561 | dev->multifunction = 1; |
||
562 | } |
||
563 | |||
564 | /* Fix up broken headers */ |
||
565 | pci_fixup_device(PCI_FIXUP_HEADER, dev); |
||
566 | |||
567 | /* |
||
568 | * Add the device to our list of discovered devices |
||
569 | * and the bus list for fixup functions, etc. |
||
570 | */ |
||
571 | INIT_LIST_HEAD(&dev->global_list); |
||
572 | list_add_tail(&dev->bus_list, &bus->devices); |
||
573 | nr++; |
||
574 | |||
575 | /* |
||
576 | * If this is a single function device, |
||
577 | * don't scan past the first function. |
||
578 | */ |
||
579 | if (!dev->multifunction) |
||
580 | break; |
||
581 | } |
||
582 | return nr; |
||
583 | } |
||
584 | |||
585 | static unsigned int __devinit pci_scan_child_bus(struct pci_bus *bus) |
||
586 | { |
||
587 | unsigned int devfn, pass, max = bus->secondary; |
||
588 | struct pci_dev *dev; |
||
589 | |||
590 | DBG("Scanning bus %02x\n", bus->number); |
||
591 | |||
592 | /* Go find them, Rover! */ |
||
593 | for (devfn = 0; devfn < 0x100; devfn += 8) |
||
594 | pci_scan_slot(bus, devfn); |
||
595 | |||
596 | /* |
||
597 | * After performing arch-dependent fixup of the bus, look behind |
||
598 | * all PCI-to-PCI bridges on this bus. |
||
599 | */ |
||
600 | DBG("Fixups for bus %02x\n", bus->number); |
||
601 | pcibios_fixup_bus(bus); |
||
602 | for (pass=0; pass < 2; pass++) |
||
603 | list_for_each_entry(dev, &bus->devices, bus_list) { |
||
604 | if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE || |
||
605 | dev->hdr_type == PCI_HEADER_TYPE_CARDBUS) |
||
606 | max = pci_scan_bridge(bus, dev, max, pass); |
||
607 | } |
||
608 | |||
609 | /* |
||
610 | * We've scanned the bus and so we know all about what's on |
||
611 | * the other side of any bridges that may be on this bus plus |
||
612 | * any devices. |
||
613 | * |
||
614 | * Return how far we've got finding sub-buses. |
||
615 | */ |
||
616 | DBG("Bus scan for %02x returning with max=%02x\n", bus->number, max); |
||
617 | return max; |
||
618 | } |
||
619 | |||
620 | unsigned int __devinit pci_do_scan_bus(struct pci_bus *bus) |
||
621 | { |
||
622 | unsigned int max; |
||
623 | |||
624 | max = pci_scan_child_bus(bus); |
||
625 | |||
626 | /* |
||
627 | * Make the discovered devices available. |
||
628 | */ |
||
629 | pci_bus_add_devices(bus); |
||
630 | |||
631 | return max; |
||
632 | } |
||
633 | |||
634 | struct pci_bus * __devinit pci_scan_bus_parented(struct device *parent, int bus, struct pci_ops *ops, void *sysdata) |
||
635 | { |
||
636 | struct pci_bus *b; |
||
637 | |||
638 | b = pci_alloc_bus(); |
||
639 | if (!b) |
||
640 | return NULL; |
||
641 | |||
642 | b->dev = kmalloc(sizeof(*(b->dev)),GFP_KERNEL); |
||
643 | if (!b->dev){ |
||
644 | kfree(b); |
||
645 | return NULL; |
||
646 | } |
||
647 | |||
648 | b->sysdata = sysdata; |
||
649 | b->ops = ops; |
||
650 | |||
651 | if (pci_find_bus(pci_domain_nr(b), bus)) { |
||
652 | /* If we already got to this bus through a different bridge, ignore it */ |
||
653 | DBG("PCI: Bus %02x already known\n", bus); |
||
654 | kfree(b->dev); |
||
655 | kfree(b); |
||
656 | return NULL; |
||
657 | } |
||
658 | |||
659 | list_add_tail(&b->node, &pci_root_buses); |
||
660 | |||
661 | memset(b->dev,0,sizeof(*(b->dev))); |
||
662 | b->dev->parent = parent; |
||
663 | sprintf(b->dev->bus_id,"pci%04x:%02x", pci_domain_nr(b), bus); |
||
664 | device_register(b->dev); |
||
665 | |||
666 | b->number = b->secondary = bus; |
||
667 | b->resource[0] = &ioport_resource; |
||
668 | b->resource[1] = &iomem_resource; |
||
669 | |||
670 | b->subordinate = pci_scan_child_bus(b); |
||
671 | |||
672 | pci_bus_add_devices(b); |
||
673 | |||
674 | return b; |
||
675 | } |
||
676 | EXPORT_SYMBOL(pci_scan_bus_parented); |
||
677 | |||
678 | #ifdef CONFIG_HOTPLUG |
||
679 | EXPORT_SYMBOL(pci_add_new_bus); |
||
680 | EXPORT_SYMBOL(pci_do_scan_bus); |
||
681 | EXPORT_SYMBOL(pci_scan_slot); |
||
682 | EXPORT_SYMBOL(pci_scan_bridge); |
||
683 | #endif |