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Rev | Author | Line No. | Line |
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428 | giacomo | 1 | /* |
2 | * drivers/pci/setup-bus.c |
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3 | * |
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4 | * Extruded from code written by |
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5 | * Dave Rusling (david.rusling@reo.mts.dec.com) |
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6 | * David Mosberger (davidm@cs.arizona.edu) |
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7 | * David Miller (davem@redhat.com) |
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8 | * |
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9 | * Support routines for initializing a PCI subsystem. |
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10 | */ |
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11 | |||
12 | /* |
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13 | * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
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14 | * PCI-PCI bridges cleanup, sorted resource allocation. |
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15 | * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru> |
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16 | * Converted to allocation in 3 passes, which gives |
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17 | * tighter packing. Prefetchable range support. |
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18 | */ |
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19 | |||
20 | #include <linux/init.h> |
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21 | #include <linux/kernel.h> |
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22 | #include <linux/module.h> |
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23 | #include <linux/pci.h> |
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24 | #include <linux/errno.h> |
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25 | #include <linux/ioport.h> |
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26 | #include <linux/cache.h> |
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27 | #include <linux/slab.h> |
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28 | |||
29 | |||
30 | #define DEBUG_CONFIG 1 |
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31 | #if DEBUG_CONFIG |
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32 | # define DBGC(args) printk args |
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33 | #else |
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34 | # define DBGC(args) |
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35 | #endif |
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36 | |||
37 | #define ROUND_UP(x, a) (((x) + (a) - 1) & ~((a) - 1)) |
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38 | |||
39 | /* |
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40 | * FIXME: IO should be max 256 bytes. However, since we may |
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41 | * have a P2P bridge below a cardbus bridge, we need 4K. |
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42 | */ |
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43 | #define CARDBUS_IO_SIZE (4096) |
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44 | #define CARDBUS_MEM_SIZE (32*1024*1024) |
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45 | |||
46 | static int __devinit |
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47 | pbus_assign_resources_sorted(struct pci_bus *bus) |
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48 | { |
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49 | struct pci_dev *dev; |
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50 | struct resource *res; |
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51 | struct resource_list head, *list, *tmp; |
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52 | int idx, found_vga = 0; |
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53 | |||
54 | head.next = NULL; |
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55 | list_for_each_entry(dev, &bus->devices, bus_list) { |
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56 | u16 class = dev->class >> 8; |
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57 | |||
58 | if (class == PCI_CLASS_DISPLAY_VGA |
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59 | || class == PCI_CLASS_NOT_DEFINED_VGA) |
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60 | found_vga = 1; |
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61 | |||
62 | pdev_sort_resources(dev, &head); |
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63 | } |
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64 | |||
65 | for (list = head.next; list;) { |
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66 | res = list->res; |
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67 | idx = res - &list->dev->resource[0]; |
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68 | pci_assign_resource(list->dev, idx); |
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69 | tmp = list; |
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70 | list = list->next; |
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71 | kfree(tmp); |
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72 | } |
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73 | |||
74 | return found_vga; |
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75 | } |
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76 | |||
77 | static void __devinit |
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78 | pci_setup_cardbus(struct pci_bus *bus) |
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79 | { |
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80 | struct pci_dev *bridge = bus->self; |
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81 | struct pci_bus_region region; |
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82 | |||
83 | printk("PCI: Bus %d, cardbus bridge: %s\n", |
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84 | bus->number, pci_name(bridge)); |
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85 | |||
86 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
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87 | if (bus->resource[0]->flags & IORESOURCE_IO) { |
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88 | /* |
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89 | * The IO resource is allocated a range twice as large as it |
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90 | * would normally need. This allows us to set both IO regs. |
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91 | */ |
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92 | printk(" IO window: %08lx-%08lx\n", |
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93 | region.start, region.end); |
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94 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_0, |
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95 | region.start); |
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96 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0, |
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97 | region.end); |
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98 | } |
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99 | |||
100 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); |
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101 | if (bus->resource[1]->flags & IORESOURCE_IO) { |
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102 | printk(" IO window: %08lx-%08lx\n", |
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103 | region.start, region.end); |
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104 | pci_write_config_dword(bridge, PCI_CB_IO_BASE_1, |
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105 | region.start); |
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106 | pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1, |
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107 | region.end); |
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108 | } |
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109 | |||
110 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
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111 | if (bus->resource[2]->flags & IORESOURCE_MEM) { |
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112 | printk(" PREFETCH window: %08lx-%08lx\n", |
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113 | region.start, region.end); |
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114 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0, |
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115 | region.start); |
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116 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0, |
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117 | region.end); |
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118 | } |
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119 | |||
120 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[3]); |
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121 | if (bus->resource[3]->flags & IORESOURCE_MEM) { |
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122 | printk(" MEM window: %08lx-%08lx\n", |
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123 | region.start, region.end); |
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124 | pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1, |
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125 | region.start); |
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126 | pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1, |
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127 | region.end); |
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128 | } |
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129 | } |
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130 | |||
131 | /* Initialize bridges with base/limit values we have collected. |
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132 | PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998) |
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133 | requires that if there is no I/O ports or memory behind the |
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134 | bridge, corresponding range must be turned off by writing base |
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135 | value greater than limit to the bridge's base/limit registers. |
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136 | |||
137 | Note: care must be taken when updating I/O base/limit registers |
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138 | of bridges which support 32-bit I/O. This update requires two |
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139 | config space writes, so it's quite possible that an I/O window of |
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140 | the bridge will have some undesirable address (e.g. 0) after the |
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141 | first write. Ditto 64-bit prefetchable MMIO. */ |
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142 | static void __devinit |
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143 | pci_setup_bridge(struct pci_bus *bus) |
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144 | { |
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145 | struct pci_dev *bridge = bus->self; |
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146 | struct pci_bus_region region; |
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147 | u32 l, io_upper16; |
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148 | |||
149 | DBGC((KERN_INFO "PCI: Bus %d, bridge: %s\n", |
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150 | bus->number, pci_name(bridge))); |
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151 | |||
152 | /* Set up the top and bottom of the PCI I/O segment for this bus. */ |
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153 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[0]); |
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154 | if (bus->resource[0]->flags & IORESOURCE_IO) { |
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155 | pci_read_config_dword(bridge, PCI_IO_BASE, &l); |
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156 | l &= 0xffff0000; |
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157 | l |= (region.start >> 8) & 0x00f0; |
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158 | l |= region.end & 0xf000; |
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159 | /* Set up upper 16 bits of I/O base/limit. */ |
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160 | io_upper16 = (region.end & 0xffff0000) | (region.start >> 16); |
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161 | DBGC((KERN_INFO " IO window: %04lx-%04lx\n", |
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162 | region.start, region.end)); |
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163 | } |
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164 | else { |
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165 | /* Clear upper 16 bits of I/O base/limit. */ |
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166 | io_upper16 = 0; |
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167 | l = 0x00f0; |
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168 | DBGC((KERN_INFO " IO window: disabled.\n")); |
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169 | } |
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170 | /* Temporarily disable the I/O range before updating PCI_IO_BASE. */ |
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171 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff); |
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172 | /* Update lower 16 bits of I/O base/limit. */ |
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173 | pci_write_config_dword(bridge, PCI_IO_BASE, l); |
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174 | /* Update upper 16 bits of I/O base/limit. */ |
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175 | pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16); |
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176 | |||
177 | /* Set up the top and bottom of the PCI Memory segment |
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178 | for this bus. */ |
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179 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[1]); |
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180 | if (bus->resource[1]->flags & IORESOURCE_MEM) { |
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181 | l = (region.start >> 16) & 0xfff0; |
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182 | l |= region.end & 0xfff00000; |
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183 | DBGC((KERN_INFO " MEM window: %08lx-%08lx\n", |
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184 | region.start, region.end)); |
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185 | } |
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186 | else { |
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187 | l = 0x0000fff0; |
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188 | DBGC((KERN_INFO " MEM window: disabled.\n")); |
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189 | } |
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190 | pci_write_config_dword(bridge, PCI_MEMORY_BASE, l); |
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191 | |||
192 | /* Clear out the upper 32 bits of PREF limit. |
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193 | If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily |
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194 | disables PREF range, which is ok. */ |
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195 | pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0); |
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196 | |||
197 | /* Set up PREF base/limit. */ |
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198 | pcibios_resource_to_bus(bridge, ®ion, bus->resource[2]); |
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199 | if (bus->resource[2]->flags & IORESOURCE_PREFETCH) { |
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200 | l = (region.start >> 16) & 0xfff0; |
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201 | l |= region.end & 0xfff00000; |
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202 | DBGC((KERN_INFO " PREFETCH window: %08lx-%08lx\n", |
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203 | region.start, region.end)); |
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204 | } |
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205 | else { |
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206 | l = 0x0000fff0; |
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207 | DBGC((KERN_INFO " PREFETCH window: disabled.\n")); |
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208 | } |
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209 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l); |
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210 | |||
211 | /* Clear out the upper 32 bits of PREF base. */ |
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212 | pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, 0); |
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213 | |||
214 | /* Check if we have VGA behind the bridge. |
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215 | Enable ISA in either case (FIXME!). */ |
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216 | l = (bus->resource[0]->flags & IORESOURCE_BUS_HAS_VGA) ? 0x0c : 0x04; |
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217 | pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, l); |
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218 | } |
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219 | |||
220 | /* Check whether the bridge supports optional I/O and |
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221 | prefetchable memory ranges. If not, the respective |
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222 | base/limit registers must be read-only and read as 0. */ |
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223 | static void __devinit |
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224 | pci_bridge_check_ranges(struct pci_bus *bus) |
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225 | { |
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226 | u16 io; |
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227 | u32 pmem; |
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228 | struct pci_dev *bridge = bus->self; |
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229 | struct resource *b_res; |
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230 | |||
231 | b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
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232 | b_res[1].flags |= IORESOURCE_MEM; |
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233 | |||
234 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
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235 | if (!io) { |
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236 | pci_write_config_word(bridge, PCI_IO_BASE, 0xf0f0); |
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237 | pci_read_config_word(bridge, PCI_IO_BASE, &io); |
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238 | pci_write_config_word(bridge, PCI_IO_BASE, 0x0); |
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239 | } |
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240 | if (io) |
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241 | b_res[0].flags |= IORESOURCE_IO; |
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242 | /* DECchip 21050 pass 2 errata: the bridge may miss an address |
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243 | disconnect boundary by one PCI data phase. |
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244 | Workaround: do not use prefetching on this device. */ |
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245 | if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001) |
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246 | return; |
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247 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
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248 | if (!pmem) { |
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249 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, |
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250 | 0xfff0fff0); |
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251 | pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem); |
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252 | pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0); |
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253 | } |
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254 | if (pmem) |
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255 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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256 | } |
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257 | |||
258 | /* Helper function for sizing routines: find first available |
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259 | bus resource of a given type. Note: we intentionally skip |
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260 | the bus resources which have already been assigned (that is, |
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261 | have non-NULL parent resource). */ |
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262 | static struct resource * __devinit |
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263 | find_free_bus_resource(struct pci_bus *bus, unsigned long type) |
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264 | { |
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265 | int i; |
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266 | struct resource *r; |
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267 | unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM | |
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268 | IORESOURCE_PREFETCH; |
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269 | |||
270 | for (i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { |
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271 | r = bus->resource[i]; |
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272 | if (r && (r->flags & type_mask) == type && !r->parent) |
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273 | return r; |
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274 | } |
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275 | return NULL; |
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276 | } |
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277 | |||
278 | /* Sizing the IO windows of the PCI-PCI bridge is trivial, |
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279 | since these windows have 4K granularity and the IO ranges |
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280 | of non-bridge PCI devices are limited to 256 bytes. |
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281 | We must be careful with the ISA aliasing though. */ |
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282 | static void __devinit |
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283 | pbus_size_io(struct pci_bus *bus) |
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284 | { |
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285 | struct pci_dev *dev; |
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286 | struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO); |
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287 | unsigned long size = 0, size1 = 0; |
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288 | |||
289 | if (!b_res) |
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290 | return; |
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291 | |||
292 | list_for_each_entry(dev, &bus->devices, bus_list) { |
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293 | int i; |
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294 | |||
295 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
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296 | struct resource *r = &dev->resource[i]; |
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297 | unsigned long r_size; |
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298 | |||
299 | if (r->parent || !(r->flags & IORESOURCE_IO)) |
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300 | continue; |
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301 | r_size = r->end - r->start + 1; |
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302 | |||
303 | if (r_size < 0x400) |
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304 | /* Might be re-aligned for ISA */ |
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305 | size += r_size; |
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306 | else |
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307 | size1 += r_size; |
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308 | } |
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309 | } |
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310 | /* To be fixed in 2.5: we should have sort of HAVE_ISA |
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311 | flag in the struct pci_bus. */ |
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312 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
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313 | size = (size & 0xff) + ((size & ~0xffUL) << 2); |
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314 | #endif |
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315 | size = ROUND_UP(size + size1, 4096); |
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316 | if (!size) { |
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317 | b_res->flags = 0; |
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318 | return; |
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319 | } |
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320 | /* Alignment of the IO window is always 4K */ |
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321 | b_res->start = 4096; |
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322 | b_res->end = b_res->start + size - 1; |
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323 | } |
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324 | |||
325 | /* Calculate the size of the bus and minimal alignment which |
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326 | guarantees that all child resources fit in this size. */ |
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327 | static int __devinit |
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328 | pbus_size_mem(struct pci_bus *bus, unsigned long mask, unsigned long type) |
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329 | { |
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330 | struct pci_dev *dev; |
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331 | unsigned long min_align, align, size; |
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332 | unsigned long aligns[12]; /* Alignments from 1Mb to 2Gb */ |
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333 | int order, max_order; |
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334 | struct resource *b_res = find_free_bus_resource(bus, type); |
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335 | |||
336 | if (!b_res) |
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337 | return 0; |
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338 | |||
339 | memset(aligns, 0, sizeof(aligns)); |
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340 | max_order = 0; |
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341 | size = 0; |
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342 | |||
343 | list_for_each_entry(dev, &bus->devices, bus_list) { |
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344 | int i; |
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345 | |||
346 | for (i = 0; i < PCI_NUM_RESOURCES; i++) { |
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347 | struct resource *r = &dev->resource[i]; |
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348 | unsigned long r_size; |
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349 | |||
350 | if (r->parent || (r->flags & mask) != type) |
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351 | continue; |
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352 | r_size = r->end - r->start + 1; |
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353 | /* For bridges size != alignment */ |
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354 | align = (i < PCI_BRIDGE_RESOURCES) ? r_size : r->start; |
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355 | order = __ffs(align) - 20; |
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356 | if (order > 11) { |
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357 | printk(KERN_WARNING "PCI: region %s/%d " |
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358 | "too large: %lx-%lx\n", |
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359 | pci_name(dev), i, r->start, r->end); |
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360 | r->flags = 0; |
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361 | continue; |
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362 | } |
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363 | size += r_size; |
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364 | if (order < 0) |
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365 | order = 0; |
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366 | /* Exclude ranges with size > align from |
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367 | calculation of the alignment. */ |
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368 | if (r_size == align) |
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369 | aligns[order] += align; |
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370 | if (order > max_order) |
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371 | max_order = order; |
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372 | } |
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373 | } |
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374 | |||
375 | align = 0; |
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376 | min_align = 0; |
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377 | for (order = 0; order <= max_order; order++) { |
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378 | unsigned long align1 = 1UL << (order + 20); |
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379 | |||
380 | if (!align) |
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381 | min_align = align1; |
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382 | else if (ROUND_UP(align + min_align, min_align) < align1) |
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383 | min_align = align1 >> 1; |
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384 | align += aligns[order]; |
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385 | } |
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386 | size = ROUND_UP(size, min_align); |
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387 | if (!size) { |
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388 | b_res->flags = 0; |
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389 | return 1; |
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390 | } |
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391 | b_res->start = min_align; |
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392 | b_res->end = size + min_align - 1; |
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393 | return 1; |
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394 | } |
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395 | |||
396 | static void __devinit |
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397 | pci_bus_size_cardbus(struct pci_bus *bus) |
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398 | { |
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399 | struct pci_dev *bridge = bus->self; |
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400 | struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES]; |
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401 | u16 ctrl; |
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402 | |||
403 | /* |
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404 | * Reserve some resources for CardBus. We reserve |
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405 | * a fixed amount of bus space for CardBus bridges. |
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406 | */ |
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407 | b_res[0].start = CARDBUS_IO_SIZE; |
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408 | b_res[0].end = b_res[0].start + CARDBUS_IO_SIZE - 1; |
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409 | b_res[0].flags |= IORESOURCE_IO; |
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410 | |||
411 | b_res[1].start = CARDBUS_IO_SIZE; |
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412 | b_res[1].end = b_res[1].start + CARDBUS_IO_SIZE - 1; |
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413 | b_res[1].flags |= IORESOURCE_IO; |
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414 | |||
415 | /* |
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416 | * Check whether prefetchable memory is supported |
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417 | * by this bridge. |
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418 | */ |
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419 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
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420 | if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) { |
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421 | ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0; |
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422 | pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl); |
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423 | pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl); |
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424 | } |
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425 | |||
426 | /* |
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427 | * If we have prefetchable memory support, allocate |
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428 | * two regions. Otherwise, allocate one region of |
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429 | * twice the size. |
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430 | */ |
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431 | if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) { |
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432 | b_res[2].start = CARDBUS_MEM_SIZE; |
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433 | b_res[2].end = b_res[2].start + CARDBUS_MEM_SIZE - 1; |
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434 | b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH; |
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435 | |||
436 | b_res[3].start = CARDBUS_MEM_SIZE; |
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437 | b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE - 1; |
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438 | b_res[3].flags |= IORESOURCE_MEM; |
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439 | } else { |
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440 | b_res[3].start = CARDBUS_MEM_SIZE * 2; |
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441 | b_res[3].end = b_res[3].start + CARDBUS_MEM_SIZE * 2 - 1; |
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442 | b_res[3].flags |= IORESOURCE_MEM; |
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443 | } |
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444 | } |
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445 | |||
446 | void __devinit |
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447 | pci_bus_size_bridges(struct pci_bus *bus) |
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448 | { |
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449 | struct pci_dev *dev; |
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450 | unsigned long mask, prefmask; |
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451 | |||
452 | list_for_each_entry(dev, &bus->devices, bus_list) { |
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453 | struct pci_bus *b = dev->subordinate; |
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454 | if (!b) |
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455 | continue; |
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456 | |||
457 | switch (dev->class >> 8) { |
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458 | case PCI_CLASS_BRIDGE_CARDBUS: |
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459 | pci_bus_size_cardbus(b); |
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460 | break; |
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461 | |||
462 | case PCI_CLASS_BRIDGE_PCI: |
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463 | default: |
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464 | pci_bus_size_bridges(b); |
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465 | break; |
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466 | } |
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467 | } |
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468 | |||
469 | /* The root bus? */ |
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470 | if (!bus->self) |
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471 | return; |
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472 | |||
473 | switch (bus->self->class >> 8) { |
||
474 | case PCI_CLASS_BRIDGE_CARDBUS: |
||
475 | /* don't size cardbuses yet. */ |
||
476 | break; |
||
477 | |||
478 | case PCI_CLASS_BRIDGE_PCI: |
||
479 | pci_bridge_check_ranges(bus); |
||
480 | default: |
||
481 | pbus_size_io(bus); |
||
482 | /* If the bridge supports prefetchable range, size it |
||
483 | separately. If it doesn't, or its prefetchable window |
||
484 | has already been allocated by arch code, try |
||
485 | non-prefetchable range for both types of PCI memory |
||
486 | resources. */ |
||
487 | mask = IORESOURCE_MEM; |
||
488 | prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH; |
||
489 | if (pbus_size_mem(bus, prefmask, prefmask)) |
||
490 | mask = prefmask; /* Success, size non-prefetch only. */ |
||
491 | pbus_size_mem(bus, mask, IORESOURCE_MEM); |
||
492 | break; |
||
493 | } |
||
494 | } |
||
495 | EXPORT_SYMBOL(pci_bus_size_bridges); |
||
496 | |||
497 | void __devinit |
||
498 | pci_bus_assign_resources(struct pci_bus *bus) |
||
499 | { |
||
500 | struct pci_bus *b; |
||
501 | int found_vga = pbus_assign_resources_sorted(bus); |
||
502 | struct pci_dev *dev; |
||
503 | |||
504 | if (found_vga) { |
||
505 | /* Propagate presence of the VGA to upstream bridges */ |
||
506 | for (b = bus; b->parent; b = b->parent) { |
||
507 | b->resource[0]->flags |= IORESOURCE_BUS_HAS_VGA; |
||
508 | } |
||
509 | } |
||
510 | list_for_each_entry(dev, &bus->devices, bus_list) { |
||
511 | b = dev->subordinate; |
||
512 | if (!b) |
||
513 | continue; |
||
514 | |||
515 | pci_bus_assign_resources(b); |
||
516 | |||
517 | switch (dev->class >> 8) { |
||
518 | case PCI_CLASS_BRIDGE_PCI: |
||
519 | pci_setup_bridge(b); |
||
520 | break; |
||
521 | |||
522 | case PCI_CLASS_BRIDGE_CARDBUS: |
||
523 | pci_setup_cardbus(b); |
||
524 | break; |
||
525 | |||
526 | default: |
||
527 | printk(KERN_INFO "PCI: not setting up bridge %s " |
||
528 | "for bus %d\n", pci_name(dev), b->number); |
||
529 | break; |
||
530 | } |
||
531 | } |
||
532 | } |
||
533 | EXPORT_SYMBOL(pci_bus_assign_resources); |
||
534 | |||
535 | void __init |
||
536 | pci_assign_unassigned_resources(void) |
||
537 | { |
||
538 | struct list_head *ln; |
||
539 | |||
540 | /* Depth first, calculate sizes and alignments of all |
||
541 | subordinate buses. */ |
||
542 | for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) |
||
543 | pci_bus_size_bridges(pci_bus_b(ln)); |
||
544 | /* Depth last, allocate resources and update the hardware. */ |
||
545 | for(ln=pci_root_buses.next; ln != &pci_root_buses; ln=ln->next) { |
||
546 | pci_bus_assign_resources(pci_bus_b(ln)); |
||
547 | pci_enable_bridges(pci_bus_b(ln)); |
||
548 | } |
||
549 | } |