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Rev | Author | Line No. | Line |
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587 | giacomo | 1 | /* |
2 | * $Id: pci.c,v 1.7 2004-04-25 12:07:34 giacomo Exp $ |
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3 | * |
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4 | * PCI Bus Services, see include/linux/pci.h for further explanation. |
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5 | * |
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6 | * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter, |
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7 | * David Mosberger-Tang |
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8 | * |
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9 | * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz> |
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10 | */ |
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11 | |||
12 | #include <linuxcomp.h> |
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13 | |||
14 | #include <linux/delay.h> |
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15 | #include <linux/init.h> |
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16 | #include <linux/pci.h> |
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17 | #include <linux/module.h> |
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18 | #include <linux/spinlock.h> |
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19 | #include <asm/dma.h> /* isa_dma_bridge_buggy */ |
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20 | |||
21 | //#define DEBUG |
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22 | |||
23 | #ifdef DEBUG |
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24 | #define DBG(x...) printk(x) |
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25 | #else |
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26 | #define DBG(x...) |
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27 | #endif |
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28 | |||
29 | /** |
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30 | * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children |
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31 | * @bus: pointer to PCI bus structure to search |
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32 | * |
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33 | * Given a PCI bus, returns the highest PCI bus number present in the set |
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34 | * including the given PCI bus and its list of child PCI buses. |
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35 | */ |
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36 | unsigned char __devinit |
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37 | pci_bus_max_busnr(struct pci_bus* bus) |
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38 | { |
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39 | struct list_head *tmp; |
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40 | unsigned char max, n; |
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41 | |||
42 | max = bus->number; |
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43 | list_for_each(tmp, &bus->children) { |
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44 | n = pci_bus_max_busnr(pci_bus_b(tmp)); |
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45 | if(n > max) |
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46 | max = n; |
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47 | } |
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48 | return max; |
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49 | } |
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50 | |||
51 | /** |
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52 | * pci_max_busnr - returns maximum PCI bus number |
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53 | * |
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54 | * Returns the highest PCI bus number present in the system global list of |
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55 | * PCI buses. |
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56 | */ |
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57 | unsigned char __devinit |
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58 | pci_max_busnr(void) |
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59 | { |
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60 | struct pci_bus *bus = NULL; |
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61 | unsigned char max, n; |
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62 | |||
63 | max = 0; |
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64 | while ((bus = pci_find_next_bus(bus)) != NULL) { |
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65 | n = pci_bus_max_busnr(bus); |
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66 | if(n > max) |
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67 | max = n; |
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68 | } |
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69 | return max; |
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70 | } |
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71 | |||
72 | /** |
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73 | * pci_find_capability - query for devices' capabilities |
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74 | * @dev: PCI device to query |
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75 | * @cap: capability code |
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76 | * |
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77 | * Tell if a device supports a given PCI capability. |
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78 | * Returns the address of the requested capability structure within the |
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79 | * device's PCI configuration space or 0 in case the device does not |
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80 | * support it. Possible values for @cap: |
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81 | * |
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82 | * %PCI_CAP_ID_PM Power Management |
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83 | * |
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84 | * %PCI_CAP_ID_AGP Accelerated Graphics Port |
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85 | * |
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86 | * %PCI_CAP_ID_VPD Vital Product Data |
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87 | * |
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88 | * %PCI_CAP_ID_SLOTID Slot Identification |
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89 | * |
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90 | * %PCI_CAP_ID_MSI Message Signalled Interrupts |
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91 | * |
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92 | * %PCI_CAP_ID_CHSWP CompactPCI HotSwap |
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93 | * |
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94 | * %PCI_CAP_ID_PCIX PCI-X |
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95 | */ |
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96 | int |
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97 | pci_find_capability(struct pci_dev *dev, int cap) |
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98 | { |
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99 | u16 status; |
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100 | u8 pos, id; |
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101 | int ttl = 48; |
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102 | |||
103 | pci_read_config_word(dev, PCI_STATUS, &status); |
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104 | if (!(status & PCI_STATUS_CAP_LIST)) |
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105 | return 0; |
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106 | switch (dev->hdr_type) { |
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107 | case PCI_HEADER_TYPE_NORMAL: |
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108 | case PCI_HEADER_TYPE_BRIDGE: |
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109 | pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &pos); |
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110 | break; |
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111 | case PCI_HEADER_TYPE_CARDBUS: |
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112 | pci_read_config_byte(dev, PCI_CB_CAPABILITY_LIST, &pos); |
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113 | break; |
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114 | default: |
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115 | return 0; |
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116 | } |
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117 | while (ttl-- && pos >= 0x40) { |
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118 | pos &= ~3; |
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119 | pci_read_config_byte(dev, pos + PCI_CAP_LIST_ID, &id); |
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120 | if (id == 0xff) |
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121 | break; |
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122 | if (id == cap) |
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123 | return pos; |
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124 | pci_read_config_byte(dev, pos + PCI_CAP_LIST_NEXT, &pos); |
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125 | } |
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126 | return 0; |
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127 | } |
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128 | |||
129 | /** |
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130 | * pci_bus_find_capability - query for devices' capabilities |
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131 | * @bus: the PCI bus to query |
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132 | * @devfn: PCI device to query |
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133 | * @cap: capability code |
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134 | * |
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135 | * Like pci_find_capability() but works for pci devices that do not have a |
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136 | * pci_dev structure set up yet. |
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137 | * |
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138 | * Returns the address of the requested capability structure within the |
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139 | * device's PCI configuration space or 0 in case the device does not |
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140 | * support it. |
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141 | */ |
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142 | int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) |
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143 | { |
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144 | u16 status; |
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145 | u8 pos, id; |
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146 | int ttl = 48; |
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147 | struct pci_dev *dev = bus->self; |
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148 | |||
149 | pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status); |
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150 | if (!(status & PCI_STATUS_CAP_LIST)) |
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151 | return 0; |
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152 | switch (dev->hdr_type) { |
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153 | case PCI_HEADER_TYPE_NORMAL: |
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154 | case PCI_HEADER_TYPE_BRIDGE: |
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155 | pci_bus_read_config_byte(bus, devfn, PCI_CAPABILITY_LIST, &pos); |
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156 | break; |
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157 | case PCI_HEADER_TYPE_CARDBUS: |
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158 | pci_bus_read_config_byte(bus, devfn, PCI_CB_CAPABILITY_LIST, &pos); |
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159 | break; |
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160 | default: |
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161 | return 0; |
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162 | } |
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163 | while (ttl-- && pos >= 0x40) { |
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164 | pos &= ~3; |
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165 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_ID, &id); |
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166 | if (id == 0xff) |
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167 | break; |
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168 | if (id == cap) |
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169 | return pos; |
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170 | pci_bus_read_config_byte(bus, devfn, pos + PCI_CAP_LIST_NEXT, &pos); |
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171 | } |
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172 | return 0; |
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173 | } |
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174 | |||
175 | /** |
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176 | * pci_find_parent_resource - return resource region of parent bus of given region |
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177 | * @dev: PCI device structure contains resources to be searched |
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178 | * @res: child resource record for which parent is sought |
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179 | * |
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180 | * For given resource region of given device, return the resource |
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181 | * region of parent bus the given region is contained in or where |
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182 | * it should be allocated from. |
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183 | */ |
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184 | struct resource * |
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185 | pci_find_parent_resource(const struct pci_dev *dev, struct resource *res) |
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186 | { |
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187 | const struct pci_bus *bus = dev->bus; |
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188 | int i; |
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189 | struct resource *best = NULL; |
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190 | |||
191 | for(i = 0; i < PCI_BUS_NUM_RESOURCES; i++) { |
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192 | struct resource *r = bus->resource[i]; |
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193 | if (!r) |
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194 | continue; |
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195 | if (res->start && !(res->start >= r->start && res->end <= r->end)) |
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196 | continue; /* Not contained */ |
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197 | if ((res->flags ^ r->flags) & (IORESOURCE_IO | IORESOURCE_MEM)) |
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198 | continue; /* Wrong type */ |
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199 | if (!((res->flags ^ r->flags) & IORESOURCE_PREFETCH)) |
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200 | return r; /* Exact match */ |
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201 | if ((res->flags & IORESOURCE_PREFETCH) && !(r->flags & IORESOURCE_PREFETCH)) |
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202 | best = r; /* Approximating prefetchable by non-prefetchable */ |
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203 | } |
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204 | return best; |
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205 | } |
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206 | |||
207 | /** |
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208 | * pci_set_power_state - Set the power state of a PCI device |
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209 | * @dev: PCI device to be suspended |
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210 | * @state: Power state we're entering |
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211 | * |
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212 | * Transition a device to a new power state, using the Power Management |
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213 | * Capabilities in the device's config space. |
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214 | * |
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215 | * RETURN VALUE: |
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216 | * -EINVAL if trying to enter a lower state than we're already in. |
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217 | * 0 if we're already in the requested state. |
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218 | * -EIO if device does not support PCI PM. |
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219 | * 0 if we can successfully change the power state. |
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220 | */ |
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221 | |||
222 | int |
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223 | pci_set_power_state(struct pci_dev *dev, int state) |
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224 | { |
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225 | int pm; |
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226 | u16 pmcsr; |
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227 | |||
228 | /* bound the state we're entering */ |
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229 | if (state > 3) state = 3; |
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230 | |||
231 | /* Validate current state: |
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232 | * Can enter D0 from any state, but if we can only go deeper |
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233 | * to sleep if we're already in a low power state |
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234 | */ |
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235 | if (state > 0 && dev->current_state > state) |
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236 | return -EINVAL; |
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237 | else if (dev->current_state == state) |
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238 | return 0; /* we're already there */ |
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239 | |||
240 | /* find PCI PM capability in list */ |
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241 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
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242 | |||
243 | /* abort if the device doesn't support PM capabilities */ |
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244 | if (!pm) return -EIO; |
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245 | |||
246 | /* check if this device supports the desired state */ |
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247 | if (state == 1 || state == 2) { |
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248 | u16 pmc; |
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249 | pci_read_config_word(dev,pm + PCI_PM_PMC,&pmc); |
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250 | if (state == 1 && !(pmc & PCI_PM_CAP_D1)) return -EIO; |
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251 | else if (state == 2 && !(pmc & PCI_PM_CAP_D2)) return -EIO; |
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252 | } |
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253 | |||
254 | /* If we're in D3, force entire word to 0. |
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255 | * This doesn't affect PME_Status, disables PME_En, and |
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256 | * sets PowerState to 0. |
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257 | */ |
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258 | if (dev->current_state >= 3) |
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259 | pmcsr = 0; |
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260 | else { |
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261 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &pmcsr); |
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262 | pmcsr &= ~PCI_PM_CTRL_STATE_MASK; |
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263 | pmcsr |= state; |
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264 | } |
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265 | |||
266 | /* enter specified state */ |
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267 | pci_write_config_word(dev, pm + PCI_PM_CTRL, pmcsr); |
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268 | |||
269 | /* Mandatory power management transition delays */ |
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270 | /* see PCI PM 1.1 5.6.1 table 18 */ |
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271 | if(state == 3 || dev->current_state == 3) |
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272 | { |
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273 | //set_current_state(TASK_UNINTERRUPTIBLE); |
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274 | schedule_timeout(HZ/100); |
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275 | } |
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276 | else if(state == 2 || dev->current_state == 2) |
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277 | udelay(200); |
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278 | dev->current_state = state; |
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279 | |||
280 | return 0; |
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281 | } |
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282 | |||
283 | /** |
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284 | * pci_save_state - save the PCI configuration space of a device before suspending |
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285 | * @dev: - PCI device that we're dealing with |
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286 | * @buffer: - buffer to hold config space context |
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287 | * |
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288 | * @buffer must be large enough to hold the entire PCI 2.2 config space |
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289 | * (>= 64 bytes). |
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290 | */ |
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291 | int |
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292 | pci_save_state(struct pci_dev *dev, u32 *buffer) |
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293 | { |
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294 | int i; |
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295 | if (buffer) { |
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296 | /* XXX: 100% dword access ok here? */ |
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297 | for (i = 0; i < 16; i++) |
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298 | pci_read_config_dword(dev, i * 4,&buffer[i]); |
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299 | } |
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300 | return 0; |
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301 | } |
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302 | |||
303 | /** |
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304 | * pci_restore_state - Restore the saved state of a PCI device |
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305 | * @dev: - PCI device that we're dealing with |
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306 | * @buffer: - saved PCI config space |
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307 | * |
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308 | */ |
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309 | int |
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310 | pci_restore_state(struct pci_dev *dev, u32 *buffer) |
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311 | { |
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312 | int i; |
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313 | |||
314 | if (buffer) { |
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315 | for (i = 0; i < 16; i++) |
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316 | pci_write_config_dword(dev,i * 4, buffer[i]); |
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317 | } |
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318 | /* |
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319 | * otherwise, write the context information we know from bootup. |
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320 | * This works around a problem where warm-booting from Windows |
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321 | * combined with a D3(hot)->D0 transition causes PCI config |
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322 | * header data to be forgotten. |
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323 | */ |
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324 | else { |
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325 | for (i = 0; i < 6; i ++) |
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326 | pci_write_config_dword(dev, |
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327 | PCI_BASE_ADDRESS_0 + (i * 4), |
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328 | dev->resource[i].start); |
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329 | pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq); |
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330 | } |
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331 | return 0; |
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332 | } |
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333 | |||
334 | /** |
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335 | * pci_enable_device_bars - Initialize some of a device for use |
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336 | * @dev: PCI device to be initialized |
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337 | * @bars: bitmask of BAR's that must be configured |
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338 | * |
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339 | * Initialize device before it's used by a driver. Ask low-level code |
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340 | * to enable selected I/O and memory resources. Wake up the device if it |
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341 | * was suspended. Beware, this function can fail. |
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342 | */ |
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343 | |||
344 | int |
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345 | pci_enable_device_bars(struct pci_dev *dev, int bars) |
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346 | { |
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347 | int err; |
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348 | |||
349 | pci_set_power_state(dev, 0); |
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350 | if ((err = pcibios_enable_device(dev, bars)) < 0) |
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351 | return err; |
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352 | |||
353 | return 0; |
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354 | } |
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355 | |||
356 | /** |
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357 | * pci_enable_device - Initialize device before it's used by a driver. |
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358 | * @dev: PCI device to be initialized |
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359 | * |
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360 | * Initialize device before it's used by a driver. Ask low-level code |
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361 | * to enable I/O and memory. Wake up the device if it was suspended. |
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362 | * Beware, this function can fail. |
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363 | */ |
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364 | int |
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365 | pci_enable_device(struct pci_dev *dev) |
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366 | { |
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367 | return pci_enable_device_bars(dev, (1 << PCI_NUM_RESOURCES) - 1); |
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368 | } |
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369 | |||
370 | /** |
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371 | * pci_disable_device - Disable PCI device after use |
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372 | * @dev: PCI device to be disabled |
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373 | * |
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374 | * Signal to the system that the PCI device is not in use by the system |
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375 | * anymore. This only involves disabling PCI bus-mastering, if active. |
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376 | */ |
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377 | void |
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378 | pci_disable_device(struct pci_dev *dev) |
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379 | { |
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380 | u16 pci_command; |
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381 | |||
382 | pci_read_config_word(dev, PCI_COMMAND, &pci_command); |
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383 | if (pci_command & PCI_COMMAND_MASTER) { |
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384 | pci_command &= ~PCI_COMMAND_MASTER; |
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385 | pci_write_config_word(dev, PCI_COMMAND, pci_command); |
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386 | } |
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387 | } |
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388 | |||
389 | /** |
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390 | * pci_enable_wake - enable device to generate PME# when suspended |
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391 | * @dev: - PCI device to operate on |
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392 | * @state: - Current state of device. |
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393 | * @enable: - Flag to enable or disable generation |
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394 | * |
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395 | * Set the bits in the device's PM Capabilities to generate PME# when |
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396 | * the system is suspended. |
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397 | * |
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398 | * -EIO is returned if device doesn't have PM Capabilities. |
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399 | * -EINVAL is returned if device supports it, but can't generate wake events. |
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400 | * 0 if operation is successful. |
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401 | * |
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402 | */ |
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403 | int pci_enable_wake(struct pci_dev *dev, u32 state, int enable) |
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404 | { |
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405 | int pm; |
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406 | u16 value; |
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407 | |||
408 | /* find PCI PM capability in list */ |
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409 | pm = pci_find_capability(dev, PCI_CAP_ID_PM); |
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410 | |||
411 | /* If device doesn't support PM Capabilities, but request is to disable |
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412 | * wake events, it's a nop; otherwise fail */ |
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413 | if (!pm) |
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414 | return enable ? -EIO : 0; |
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415 | |||
416 | /* Check device's ability to generate PME# */ |
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417 | pci_read_config_word(dev,pm+PCI_PM_PMC,&value); |
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418 | |||
419 | value &= PCI_PM_CAP_PME_MASK; |
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420 | value >>= ffs(value); /* First bit of mask */ |
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421 | |||
422 | /* Check if it can generate PME# from requested state. */ |
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423 | if (!value || !(value & (1 << state))) |
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424 | return enable ? -EINVAL : 0; |
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425 | |||
426 | pci_read_config_word(dev, pm + PCI_PM_CTRL, &value); |
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427 | |||
428 | /* Clear PME_Status by writing 1 to it and enable PME# */ |
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429 | value |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE; |
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430 | |||
431 | if (!enable) |
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432 | value &= ~PCI_PM_CTRL_PME_ENABLE; |
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433 | |||
434 | pci_write_config_word(dev, pm + PCI_PM_CTRL, value); |
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435 | |||
436 | return 0; |
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437 | } |
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438 | |||
439 | int |
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440 | pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge) |
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441 | { |
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442 | u8 pin; |
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443 | |||
444 | pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin); |
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445 | if (!pin) |
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446 | return -1; |
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447 | pin--; |
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448 | while (dev->bus->self) { |
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449 | pin = (pin + PCI_SLOT(dev->devfn)) % 4; |
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450 | dev = dev->bus->self; |
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451 | } |
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452 | *bridge = dev; |
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453 | return pin; |
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454 | } |
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455 | |||
456 | /** |
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457 | * pci_release_region - Release a PCI bar |
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458 | * @pdev: PCI device whose resources were previously reserved by pci_request_region |
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459 | * @bar: BAR to release |
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460 | * |
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461 | * Releases the PCI I/O and memory resources previously reserved by a |
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462 | * successful call to pci_request_region. Call this function only |
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463 | * after all use of the PCI regions has ceased. |
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464 | */ |
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465 | void pci_release_region(struct pci_dev *pdev, int bar) |
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466 | { |
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467 | if (pci_resource_len(pdev, bar) == 0) |
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468 | return; |
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469 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) |
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470 | release_region(pci_resource_start(pdev, bar), |
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471 | pci_resource_len(pdev, bar)); |
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472 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) |
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473 | release_mem_region(pci_resource_start(pdev, bar), |
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474 | pci_resource_len(pdev, bar)); |
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475 | } |
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476 | |||
477 | /** |
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478 | * pci_request_region - Reserved PCI I/O and memory resource |
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479 | * @pdev: PCI device whose resources are to be reserved |
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480 | * @bar: BAR to be reserved |
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481 | * @res_name: Name to be associated with resource. |
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482 | * |
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483 | * Mark the PCI region associated with PCI device @pdev BR @bar as |
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484 | * being reserved by owner @res_name. Do not access any |
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485 | * address inside the PCI regions unless this call returns |
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486 | * successfully. |
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487 | * |
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488 | * Returns 0 on success, or %EBUSY on error. A warning |
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489 | * message is also printed on failure. |
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490 | */ |
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491 | int pci_request_region(struct pci_dev *pdev, int bar, char *res_name) |
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492 | { |
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493 | if (pci_resource_len(pdev, bar) == 0) |
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494 | return 0; |
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495 | |||
496 | if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) { |
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497 | if (!request_region(pci_resource_start(pdev, bar), |
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498 | pci_resource_len(pdev, bar), res_name)) |
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499 | goto err_out; |
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500 | } |
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501 | else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) { |
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502 | if (!request_mem_region(pci_resource_start(pdev, bar), |
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503 | pci_resource_len(pdev, bar), res_name)) |
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504 | goto err_out; |
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505 | } |
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506 | |||
507 | return 0; |
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508 | |||
509 | err_out: |
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510 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", |
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511 | pci_resource_flags(pdev, bar) & IORESOURCE_IO ? "I/O" : "mem", |
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512 | bar + 1, /* PCI BAR # */ |
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513 | pci_resource_len(pdev, bar), pci_resource_start(pdev, bar), |
||
514 | pci_name(pdev)); |
||
515 | return -EBUSY; |
||
516 | } |
||
517 | |||
518 | |||
519 | /** |
||
520 | * pci_release_regions - Release reserved PCI I/O and memory resources |
||
521 | * @pdev: PCI device whose resources were previously reserved by pci_request_regions |
||
522 | * |
||
523 | * Releases all PCI I/O and memory resources previously reserved by a |
||
524 | * successful call to pci_request_regions. Call this function only |
||
525 | * after all use of the PCI regions has ceased. |
||
526 | */ |
||
527 | |||
528 | void pci_release_regions(struct pci_dev *pdev) |
||
529 | { |
||
530 | int i; |
||
531 | |||
532 | for (i = 0; i < 6; i++) |
||
533 | pci_release_region(pdev, i); |
||
534 | } |
||
535 | |||
536 | /** |
||
537 | * pci_request_regions - Reserved PCI I/O and memory resources |
||
538 | * @pdev: PCI device whose resources are to be reserved |
||
539 | * @res_name: Name to be associated with resource. |
||
540 | * |
||
541 | * Mark all PCI regions associated with PCI device @pdev as |
||
542 | * being reserved by owner @res_name. Do not access any |
||
543 | * address inside the PCI regions unless this call returns |
||
544 | * successfully. |
||
545 | * |
||
546 | * Returns 0 on success, or %EBUSY on error. A warning |
||
547 | * message is also printed on failure. |
||
548 | */ |
||
549 | int pci_request_regions(struct pci_dev *pdev, char *res_name) |
||
550 | { |
||
551 | int i; |
||
552 | |||
553 | for (i = 0; i < 6; i++) |
||
554 | if(pci_request_region(pdev, i, res_name)) |
||
555 | goto err_out; |
||
556 | return 0; |
||
557 | |||
558 | err_out: |
||
559 | printk (KERN_WARNING "PCI: Unable to reserve %s region #%d:%lx@%lx for device %s\n", |
||
560 | pci_resource_flags(pdev, i) & IORESOURCE_IO ? "I/O" : "mem", |
||
561 | i + 1, /* PCI BAR # */ |
||
562 | pci_resource_len(pdev, i), pci_resource_start(pdev, i), |
||
563 | pci_name(pdev)); |
||
564 | while(--i >= 0) |
||
565 | pci_release_region(pdev, i); |
||
566 | |||
567 | return -EBUSY; |
||
568 | } |
||
569 | |||
570 | /** |
||
571 | * pci_set_master - enables bus-mastering for device dev |
||
572 | * @dev: the PCI device to enable |
||
573 | * |
||
574 | * Enables bus-mastering on the device and calls pcibios_set_master() |
||
575 | * to do the needed arch specific settings. |
||
576 | */ |
||
577 | void |
||
578 | pci_set_master(struct pci_dev *dev) |
||
579 | { |
||
580 | u16 cmd; |
||
581 | |||
582 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
||
583 | if (! (cmd & PCI_COMMAND_MASTER)) { |
||
584 | DBG("PCI: Enabling bus mastering for device %s\n", pci_name(dev)); |
||
585 | cmd |= PCI_COMMAND_MASTER; |
||
586 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
587 | } |
||
588 | pcibios_set_master(dev); |
||
589 | } |
||
590 | |||
591 | #ifndef HAVE_ARCH_PCI_MWI |
||
592 | /* This can be overridden by arch code. */ |
||
593 | u8 pci_cache_line_size = L1_CACHE_BYTES >> 2; |
||
594 | |||
595 | /** |
||
596 | * pci_generic_prep_mwi - helper function for pci_set_mwi |
||
597 | * @dev: the PCI device for which MWI is enabled |
||
598 | * |
||
599 | * Helper function for generic implementation of pcibios_prep_mwi |
||
600 | * function. Originally copied from drivers/net/acenic.c. |
||
601 | * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>. |
||
602 | * |
||
603 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
||
604 | */ |
||
605 | static int |
||
606 | pci_generic_prep_mwi(struct pci_dev *dev) |
||
607 | { |
||
608 | u8 cacheline_size; |
||
609 | |||
610 | if (!pci_cache_line_size) |
||
611 | return -EINVAL; /* The system doesn't support MWI. */ |
||
612 | |||
613 | /* Validate current setting: the PCI_CACHE_LINE_SIZE must be |
||
614 | equal to or multiple of the right value. */ |
||
615 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
||
616 | if (cacheline_size >= pci_cache_line_size && |
||
617 | (cacheline_size % pci_cache_line_size) == 0) |
||
618 | return 0; |
||
619 | |||
620 | /* Write the correct value. */ |
||
621 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size); |
||
622 | /* Read it back. */ |
||
623 | pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size); |
||
624 | if (cacheline_size == pci_cache_line_size) |
||
625 | return 0; |
||
626 | |||
627 | printk(KERN_WARNING "PCI: cache line size of %d is not supported " |
||
628 | "by device %s\n", pci_cache_line_size << 2, pci_name(dev)); |
||
629 | |||
630 | return -EINVAL; |
||
631 | } |
||
632 | #endif /* !HAVE_ARCH_PCI_MWI */ |
||
633 | |||
634 | /** |
||
635 | * pci_set_mwi - enables memory-write-invalidate PCI transaction |
||
636 | * @dev: the PCI device for which MWI is enabled |
||
637 | * |
||
638 | * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND, |
||
639 | * and then calls @pcibios_set_mwi to do the needed arch specific |
||
640 | * operations or a generic mwi-prep function. |
||
641 | * |
||
642 | * RETURNS: An appropriate -ERRNO error value on error, or zero for success. |
||
643 | */ |
||
644 | int |
||
645 | pci_set_mwi(struct pci_dev *dev) |
||
646 | { |
||
647 | int rc; |
||
648 | u16 cmd; |
||
649 | |||
650 | #ifdef HAVE_ARCH_PCI_MWI |
||
651 | rc = pcibios_prep_mwi(dev); |
||
652 | #else |
||
653 | rc = pci_generic_prep_mwi(dev); |
||
654 | #endif |
||
655 | |||
656 | if (rc) |
||
657 | return rc; |
||
658 | |||
659 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
||
660 | if (! (cmd & PCI_COMMAND_INVALIDATE)) { |
||
661 | DBG("PCI: Enabling Mem-Wr-Inval for device %s\n", pci_name(dev)); |
||
662 | cmd |= PCI_COMMAND_INVALIDATE; |
||
663 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
664 | } |
||
665 | |||
666 | return 0; |
||
667 | } |
||
668 | |||
669 | /** |
||
670 | * pci_clear_mwi - disables Memory-Write-Invalidate for device dev |
||
671 | * @dev: the PCI device to disable |
||
672 | * |
||
673 | * Disables PCI Memory-Write-Invalidate transaction on the device |
||
674 | */ |
||
675 | void |
||
676 | pci_clear_mwi(struct pci_dev *dev) |
||
677 | { |
||
678 | u16 cmd; |
||
679 | |||
680 | pci_read_config_word(dev, PCI_COMMAND, &cmd); |
||
681 | if (cmd & PCI_COMMAND_INVALIDATE) { |
||
682 | cmd &= ~PCI_COMMAND_INVALIDATE; |
||
683 | pci_write_config_word(dev, PCI_COMMAND, cmd); |
||
684 | } |
||
685 | } |
||
686 | |||
687 | int |
||
688 | pci_set_dma_mask(struct pci_dev *dev, u64 mask) |
||
689 | { |
||
690 | if (!pci_dma_supported(dev, mask)) |
||
691 | return -EIO; |
||
692 | |||
693 | dev->dma_mask = mask; |
||
694 | |||
695 | return 0; |
||
696 | } |
||
697 | |||
698 | int |
||
699 | pci_dac_set_dma_mask(struct pci_dev *dev, u64 mask) |
||
700 | { |
||
701 | if (!pci_dac_dma_supported(dev, mask)) |
||
702 | return -EIO; |
||
703 | |||
704 | dev->dma_mask = mask; |
||
705 | |||
706 | return 0; |
||
707 | } |
||
708 | |||
709 | int |
||
710 | pci_set_consistent_dma_mask(struct pci_dev *dev, u64 mask) |
||
711 | { |
||
712 | if (!pci_dma_supported(dev, mask)) |
||
713 | return -EIO; |
||
714 | |||
715 | dev->consistent_dma_mask = mask; |
||
716 | |||
717 | return 0; |
||
718 | } |
||
719 | |||
720 | int __devinit pci_init(void) |
||
721 | { |
||
722 | struct pci_dev *dev = NULL; |
||
723 | |||
724 | while ((dev = pci_find_device(PCI_ANY_ID, PCI_ANY_ID, dev)) != NULL) { |
||
725 | pci_fixup_device(PCI_FIXUP_FINAL, dev); |
||
726 | } |
||
727 | |||
728 | return 0; |
||
729 | } |
||
730 | |||
731 | static int __devinit pci_setup(char *str) |
||
732 | { |
||
733 | while (str) { |
||
734 | char *k = strchr(str, ','); |
||
735 | if (k) |
||
736 | *k++ = 0; |
||
737 | if (*str && (str = pcibios_setup(str)) && *str) { |
||
738 | /* PCI layer options should be handled here */ |
||
739 | printk(KERN_ERR "PCI: Unknown option `%s'\n", str); |
||
740 | } |
||
741 | str = k; |
||
742 | } |
||
743 | return 1; |
||
744 | } |
||
745 | |||
746 | device_initcall(pci_init); |
||
747 | |||
748 | __setup("pci=", pci_setup); |
||
749 | |||
750 | #if defined(CONFIG_ISA) || defined(CONFIG_EISA) |
||
751 | /* FIXME: Some boxes have multiple ISA bridges! */ |
||
752 | struct pci_dev *isa_bridge; |
||
753 | EXPORT_SYMBOL(isa_bridge); |
||
754 | #endif |
||
755 | |||
756 | EXPORT_SYMBOL(pci_enable_device_bars); |
||
757 | EXPORT_SYMBOL(pci_enable_device); |
||
758 | EXPORT_SYMBOL(pci_disable_device); |
||
759 | EXPORT_SYMBOL(pci_max_busnr); |
||
760 | EXPORT_SYMBOL(pci_bus_max_busnr); |
||
761 | EXPORT_SYMBOL(pci_find_capability); |
||
762 | EXPORT_SYMBOL(pci_bus_find_capability); |
||
763 | EXPORT_SYMBOL(pci_release_regions); |
||
764 | EXPORT_SYMBOL(pci_request_regions); |
||
765 | EXPORT_SYMBOL(pci_release_region); |
||
766 | EXPORT_SYMBOL(pci_request_region); |
||
767 | EXPORT_SYMBOL(pci_set_master); |
||
768 | EXPORT_SYMBOL(pci_set_mwi); |
||
769 | EXPORT_SYMBOL(pci_clear_mwi); |
||
770 | EXPORT_SYMBOL(pci_set_dma_mask); |
||
771 | EXPORT_SYMBOL(pci_dac_set_dma_mask); |
||
772 | EXPORT_SYMBOL(pci_set_consistent_dma_mask); |
||
773 | EXPORT_SYMBOL(pci_assign_resource); |
||
774 | EXPORT_SYMBOL(pci_find_parent_resource); |
||
775 | |||
776 | EXPORT_SYMBOL(pci_set_power_state); |
||
777 | EXPORT_SYMBOL(pci_save_state); |
||
778 | EXPORT_SYMBOL(pci_restore_state); |
||
779 | EXPORT_SYMBOL(pci_enable_wake); |
||
780 | |||
781 | /* Quirk info */ |
||
782 | |||
783 | EXPORT_SYMBOL(isa_dma_bridge_buggy); |
||
784 | EXPORT_SYMBOL(pci_pci_problems); |