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Rev | Author | Line No. | Line |
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658 | giacomo | 1 | /* File name ......... : pcl833.c |
2 | * Object ............ : Port per SHARK dei driver del encoder PCL833 della Advantech |
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3 | * scaricati per DOS al sito della Advantech www.advantech.com |
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4 | * Author ............ : Cerri Pietro, Fracassi Matteo |
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5 | * Language .......... : C |
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6 | * Operative system .. : SHARK |
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7 | * Creation data ..... : 26/06/2001 |
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8 | * Last modify ....... : 29/06/2001 |
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9 | */ |
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10 | |||
11 | #include <ll/ll.h> |
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12 | #include "drivers/pcl833.h" |
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13 | |||
14 | //Output Registers and Input Registers |
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15 | |||
16 | int OutReg[16]; |
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17 | int InReg[16]; |
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18 | int Base; |
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19 | |||
20 | //All fuctions are called through pcl833() |
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21 | |||
22 | int pcl833(int func, int option); |
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23 | |||
24 | //Functions |
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25 | |||
26 | int vCh_SetInputMode(int ChannelNo, int option); |
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27 | int vCh_SetInputMode(int ChannelNo, int option); |
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28 | int vCh_SetInputMode(int ChannelNo, int option); |
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29 | int vCh_DefineResetValue(int ChannelNo, int option); |
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30 | int vCh_DefineResetValue(int ChannelNo, int option); |
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31 | int vCh_DefineResetValue(int ChannelNo, int option); |
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32 | int vCh_SetLatchSource(int ChannelNo, int option); |
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33 | int vCh_SetLatchSource(int ChannelNo, int option); |
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34 | int vCh_SetLatchSource(int ChannelNo, int option); |
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35 | int vCh_IfResetOnLatch(int ChannelNo, int option); |
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36 | int vCh_IfResetOnLatch(int ChannelNo, int option); |
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37 | int vCh_IfResetOnLatch(int ChannelNo, int option); |
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38 | int vLatchWhenOverflow(int option); |
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39 | int vCounterReset(int option); |
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40 | int vChooseSysClock(int option); |
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41 | int vSetCascadeMode(int option); |
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42 | int vSet16C54TimeBase(int option); |
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43 | int vSetDI1orTimerInt(int option); |
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44 | int vSet16C54Divider(int option); |
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45 | int vCh_Read(int option); |
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46 | int vStatus_Read(void); |
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47 | int vOverflow_Read(void); |
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48 | int vInitialize833(int option); |
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49 | |||
50 | //:::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
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51 | //: : |
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52 | //: All fuctions are called through pcl833() : |
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53 | //: : |
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54 | //:::::::::::::::::::::::::::::::::::::::::::::::::::::::: |
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55 | |||
56 | int pcl833(int func, int option) { |
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57 | |||
58 | switch(func) { |
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59 | case Ch1_SetInputMode : return(vCh_SetInputMode(ch1, option)); |
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60 | case Ch2_SetInputMode : return(vCh_SetInputMode(ch2, option)); |
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61 | case Ch3_SetInputMode : return(vCh_SetInputMode(ch3, option)); |
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62 | case Ch1_DefineResetValue : return(vCh_DefineResetValue(ch1, option)); |
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63 | case Ch2_DefineResetValue : return(vCh_DefineResetValue(ch2, option)); |
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64 | case Ch3_DefineResetValue : return(vCh_DefineResetValue(ch3, option)); |
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65 | case Ch1_SetLatchSource : return(vCh_SetLatchSource(ch1, option)); |
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66 | case Ch2_SetLatchSource : return(vCh_SetLatchSource(ch2, option)); |
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67 | case Ch3_SetLatchSource : return(vCh_SetLatchSource(ch3, option)); |
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68 | case Ch1_IfResetOnLatch : return(vCh_IfResetOnLatch(ch1, option)); |
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69 | case Ch2_IfResetOnLatch : return(vCh_IfResetOnLatch(ch2, option)); |
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70 | case Ch3_IfResetOnLatch : return(vCh_IfResetOnLatch(ch3, option)); |
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71 | case LatchWhenOverflow : return(vLatchWhenOverflow(option)); |
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72 | case CounterReset : return(vCounterReset(option)); |
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73 | case ChooseSysClock : return(vChooseSysClock(option)); |
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74 | case SetCascadeMode : return(vSetCascadeMode(option)); |
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75 | case Set16C54TimeBase : return(vSet16C54TimeBase(option)); |
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76 | case SetDI1orTimerInt : return(vSetDI1orTimerInt(option)); |
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77 | case Set16C54Divider : return(vSet16C54Divider(option)); |
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78 | case Ch_Read : return(vCh_Read(option)); |
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79 | case Status_Read : return(vStatus_Read()); |
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80 | case Overflow_Read : return(vOverflow_Read()); |
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81 | case Initialize833 : return(vInitialize833(option)); |
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82 | default : return(FUNCTION_NUM_ERR); |
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83 | } |
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84 | } |
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85 | |||
86 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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87 | //: |
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88 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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89 | |||
90 | int vInitialize833(int option) { |
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91 | |||
92 | register int i; |
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93 | |||
94 | Base = option; |
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95 | |||
96 | for(i = 0; i < 16; i++) |
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97 | OutReg[i] = InReg[i] = 0; |
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98 | |||
99 | vCh_SetInputMode(ch1, PclDisable); |
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100 | vCh_SetInputMode(ch2, PclDisable); |
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101 | vCh_SetInputMode(ch3, PclDisable); |
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102 | vCh_DefineResetValue(ch1, start); |
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103 | vCh_DefineResetValue(ch2, start); |
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104 | vCh_DefineResetValue(ch3, start); |
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105 | vCh_SetLatchSource(ch1, SwReadLatch); |
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106 | vCh_SetLatchSource(ch2, SwReadLatch); |
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107 | vCh_SetLatchSource(ch3, SwReadLatch); |
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108 | vCh_IfResetOnLatch(ch1, ResetNo); |
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109 | vCh_IfResetOnLatch(ch2, ResetNo); |
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110 | vCh_IfResetOnLatch(ch3, ResetNo); |
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111 | vLatchWhenOverflow(Latch_Ch1); |
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112 | vLatchWhenOverflow(Latch_Ch2); |
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113 | vLatchWhenOverflow(Latch_Ch3); |
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114 | vCounterReset(Reset_Ch1); |
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115 | vCounterReset(Reset_Ch2); |
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116 | vCounterReset(Reset_Ch3); |
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117 | vChooseSysClock(Sys8MHZ); |
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118 | vSetCascadeMode(c24bits); //no cascade |
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119 | vSet16C54TimeBase(tPoint1ms); |
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120 | vSetDI1orTimerInt(TimerInt); |
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121 | vSet16C54Divider(0); // 0-255 divider |
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122 | |||
123 | return(OK); |
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124 | } |
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125 | |||
126 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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127 | //: |
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128 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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129 | |||
130 | int vCh_SetInputMode(int ChannelNo, int option) { |
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131 | |||
132 | int OutputReg, PortAddress, RegIndex; |
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133 | |||
134 | switch(ChannelNo) { |
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135 | case ch1: PortAddress = Base + 0; RegIndex = 0; break; |
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136 | case ch2: PortAddress = Base + 1; RegIndex = 1; break; |
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137 | case ch3: PortAddress = Base + 2; RegIndex = 2; break; |
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138 | default: return(CHANNEL_NUM_ERR); |
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139 | } |
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140 | |||
141 | OutputReg = OutReg[RegIndex] & 0x08; |
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142 | |||
143 | switch(option) { |
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144 | case x1: |
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145 | case x2: |
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146 | case x4: |
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147 | case PclDisable: |
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148 | case TwoPulseIn: |
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149 | case OnePulseIn: outp(PortAddress, OutputReg | option); break; |
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150 | default: return(PARAMETER_ERR); |
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151 | } |
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152 | |||
153 | OutReg[RegIndex] = OutputReg | option; |
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154 | |||
155 | return(OK); |
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156 | } |
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157 | |||
158 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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159 | //: |
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160 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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161 | |||
162 | int vCh_DefineResetValue(int ChannelNo, int option) { |
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163 | |||
164 | int OutputReg, PortAddress, RegIndex; |
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165 | |||
166 | switch(ChannelNo) { |
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167 | case ch1: PortAddress = Base + 0; RegIndex = 0; break; |
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168 | case ch2: PortAddress = Base + 1; RegIndex = 1; break; |
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169 | case ch3: PortAddress = Base + 2; RegIndex = 2; break; |
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170 | default: return(CHANNEL_NUM_ERR); |
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171 | } |
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172 | |||
173 | OutputReg = OutReg[RegIndex] & 0x07; |
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174 | |||
175 | switch(option) { |
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176 | case start: |
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177 | case middle: outp(PortAddress, OutputReg | option); break; |
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178 | default: return(PARAMETER_ERR); |
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179 | } |
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180 | |||
181 | OutReg[RegIndex] = OutputReg | option; |
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182 | |||
183 | return(OK); |
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184 | } |
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185 | |||
186 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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187 | //: |
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188 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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189 | |||
190 | int vCh_SetLatchSource(int ChannelNo, int option) { |
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191 | |||
192 | int OutputReg, PortAddress, RegIndex; |
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193 | |||
194 | switch(ChannelNo) { |
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195 | case ch1: PortAddress = Base + 3; RegIndex = 3; break; |
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196 | case ch2: PortAddress = Base + 4; RegIndex = 4; break; |
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197 | case ch3: PortAddress = Base + 5; RegIndex = 5; break; |
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198 | default: return(CHANNEL_NUM_ERR); |
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199 | } |
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200 | |||
201 | OutputReg = OutReg[RegIndex] & 0x08; |
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202 | |||
203 | switch(option) { |
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204 | case SwReadLatch: |
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205 | case IndexInLatch: |
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206 | case DI0Latch: |
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207 | case DI1Latch: |
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208 | case TimerLatch: outp(PortAddress, OutputReg | option); break; |
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209 | default: return(PARAMETER_ERR); |
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210 | } |
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211 | |||
212 | OutReg[RegIndex] = OutputReg | option; |
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213 | |||
214 | return(OK); |
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215 | } |
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216 | |||
217 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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218 | //: |
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219 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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220 | |||
221 | int vCh_IfResetOnLatch(int ChannelNo, int option) { |
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222 | |||
223 | int OutputReg, PortAddress, RegIndex; |
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224 | |||
225 | switch(ChannelNo) { |
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226 | case ch1: PortAddress= Base + 3; RegIndex = 3; break; |
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227 | case ch2: PortAddress= Base + 4; RegIndex = 4; break; |
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228 | case ch3: PortAddress= Base + 5; RegIndex = 5; break; |
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229 | default: return(CHANNEL_NUM_ERR); |
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230 | } |
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231 | |||
232 | OutputReg = OutReg[RegIndex] & 0x07; |
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233 | |||
234 | switch(option) { |
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235 | case ResetNo: |
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236 | case ResetYes: outp(PortAddress, OutputReg | option); break; |
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237 | default: return(PARAMETER_ERR); |
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238 | } |
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239 | |||
240 | OutReg[RegIndex] = OutputReg | option; |
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241 | |||
242 | return(OK); |
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243 | } |
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244 | |||
245 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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246 | //: |
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247 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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248 | |||
249 | int vLatchWhenOverflow(int option) { |
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250 | |||
251 | switch(option){ |
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252 | case Latch_Ch1: OutReg[6] &= 0x06; break; |
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253 | case Latch_Ch2: OutReg[6] &= 0x05; break; |
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254 | case Latch_Ch3: OutReg[6] &= 0x03; break; |
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255 | case FreeAll: OutReg[6] = 0x07; break; |
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256 | default: return(PARAMETER_ERR); |
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257 | } |
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258 | |||
259 | outp(Base + 6, OutReg[6]); |
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260 | |||
261 | return(OK); |
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262 | } |
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263 | |||
264 | |||
265 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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266 | //: |
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267 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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268 | |||
269 | int vCounterReset(int option) { |
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270 | |||
271 | switch(option) { |
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272 | case Reset_Ch1: OutReg[7] &= 0x06; |
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273 | OutReg[7] |= 0x01; |
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274 | break; |
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275 | case Reset_Ch2: OutReg[7] &= 0x05; |
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276 | OutReg[7] |= 0x02; |
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277 | break; |
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278 | case Reset_Ch3: OutReg[7] &= 0x03; |
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279 | OutReg[7] |= 0x04; |
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280 | break; |
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281 | case NoneReset: OutReg[7] = 0; |
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282 | break; |
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283 | default: return(PARAMETER_ERR); |
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284 | } |
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285 | |||
286 | outp(Base + 7, OutReg[7]); |
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287 | |||
288 | return(OK); |
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289 | } |
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290 | |||
291 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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292 | //: |
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293 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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294 | |||
295 | int vChooseSysClock(option) { |
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296 | |||
297 | int OutputReg; |
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298 | |||
299 | OutputReg = OutReg[8] & 0x0c; |
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300 | |||
301 | switch(option) { |
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302 | case Sys8MHZ: |
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303 | case Sys4MHZ: |
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304 | case Sys2MHZ: outp(Base + 8, OutputReg | option); break; |
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305 | default: return(PARAMETER_ERR); |
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306 | } |
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307 | |||
308 | OutReg[8] = OutputReg | option; |
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309 | |||
310 | return(OK); |
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311 | } |
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312 | |||
313 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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314 | //: |
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315 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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316 | |||
317 | int vSetCascadeMode(option) { |
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318 | |||
319 | int OutputReg; |
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320 | |||
321 | OutputReg = OutReg[8] & 0x03; |
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322 | |||
323 | switch(option) { |
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324 | case c24bits: // no cascade |
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325 | outp(Base + 8, OutputReg | option); |
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326 | break; |
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327 | |||
328 | case c48bits: // ch1 ch2 cascade |
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329 | OutReg[1] |= 0x07; // set ch2 cascade mode |
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330 | OutReg[0] &= 0x07; // set ch1 reset value '000000' |
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331 | outp(Base + 1, OutReg[1]); |
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332 | outp(Base, OutReg[0]); |
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333 | outp(Base + 8, OutputReg | option); |
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334 | vCh_SetInputMode(ch2, cascade); |
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335 | break; |
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336 | |||
337 | default: |
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338 | return(PARAMETER_ERR); |
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339 | } |
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340 | |||
341 | OutReg[8] = OutputReg | option; |
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342 | |||
343 | return(OK); |
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344 | } |
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345 | |||
346 | |||
347 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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348 | //: |
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349 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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350 | |||
351 | int vSet16C54TimeBase(option) { |
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352 | |||
353 | int OutputReg; |
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354 | |||
355 | OutputReg = OutReg[9] & 0x08; |
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356 | |||
357 | switch(option) { |
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358 | case tPoint1ms: |
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359 | case t1ms: |
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360 | case t10ms: |
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361 | case t100ms: |
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362 | case t1s: outp(Base + 9, OutputReg | option); break; |
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363 | default: return(PARAMETER_ERR); |
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364 | } |
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365 | |||
366 | OutReg[9] = OutputReg | option; |
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367 | |||
368 | return(OK); |
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369 | } |
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370 | |||
371 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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372 | //: |
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373 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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374 | |||
375 | int vSetDI1orTimerInt(option) { |
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376 | |||
377 | int OutputReg; |
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378 | |||
379 | OutputReg = OutReg[9] & 0x07; |
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380 | switch(option) { |
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381 | case DI1Int : |
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382 | case TimerInt : outp(Base + 9, OutputReg | option); break; |
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383 | default: return(PARAMETER_ERR); |
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384 | } |
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385 | |||
386 | OutReg[9] = OutputReg | option; |
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387 | |||
388 | return(OK); |
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389 | } |
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390 | |||
391 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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392 | //: |
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393 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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394 | |||
395 | int vSet16C54Divider(option) { |
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396 | |||
397 | outp(Base + 10, option); |
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398 | OutReg[10] = option; |
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399 | |||
400 | return(OK); |
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401 | } |
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402 | |||
403 | |||
404 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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405 | //: READ FUNCTION |
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406 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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407 | |||
408 | int vCh_Read(int ChannelNo) { |
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409 | |||
410 | switch(ChannelNo) { |
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411 | |||
412 | case ch1: |
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413 | InReg[2] = inp(Base + 2); |
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414 | InReg[0] = inp(Base); |
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415 | InReg[1] = inp(Base + 1); |
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416 | break; |
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417 | |||
418 | case ch2: |
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419 | InReg[6] = inp(Base + 6); |
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420 | InReg[4] = inp(Base + 4); |
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421 | InReg[5] = inp(Base + 5); |
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422 | break; |
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423 | |||
424 | case ch3: |
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425 | InReg[10] = inp(Base + 10); |
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426 | InReg[8] = inp(Base + 8); |
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427 | InReg[9] = inp(Base + 9); |
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428 | break; |
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429 | |||
430 | default: |
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431 | return(CHANNEL_NUM_ERR); |
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432 | } |
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433 | |||
434 | return(OK); |
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435 | } |
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436 | |||
437 | |||
438 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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439 | //: |
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440 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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441 | |||
442 | int vOverflow_Read(void) { |
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443 | |||
444 | InReg[3] = inp(Base + 3); |
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445 | InReg[7] = inp(Base + 7); |
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446 | InReg[11] = inp(Base + 11); |
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447 | |||
448 | return(OK); |
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449 | } |
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450 | |||
451 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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452 | //: |
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453 | //::::::::::::::::::::::::::::::::::::::::::::::::: |
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454 | |||
455 | int vStatus_Read(void) { |
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456 | |||
457 | InReg[14] = inp(Base + 14); |
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458 | |||
459 | return(OK); |
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460 | } |